Dmitri Strukov. UC Santa Barbara
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1 Paern Classificaion wih Memrisive Xbar Circuis Dmiri Srukov UC Sana Barbara Acknowledgmens: Fabien Alibar, Elham Zamanidoos, Brian Hoskins, Gina Adam, Farnood Merrikh Baya, Xinjie Guo, Ligang Gao, Chrisof Teuscher, John Carruhers, Tim Cheng, Luke Theogarajan, Susanne Semmer, Konsanin i Likharev Funding: AFOSR MURI, AFOSR STTR II, NSF CDI
2 Moivaion: SuperVision wih convoluional neworks A. Krizhevsky e al, ImageNe classificaion wih deep convoluional neural neworks, NIPS 12 65, neurons 6,, parameers 63,,, synapses Backpropagaion learning rule June 213 Inel, Porland 2
3 Moivaion: SuperVision wih convoluional neworks Implemened wih GPUs June 213 Inel, Porland 3
4 Moivaion: SuperVision wih convoluional neworks Problem: Concurren sae of ar implemenaions are no suiable for realime and low energy operaion Proposed soluion: Hybrid HbidCMOS/ CMOS/memrisor neworks (so called CMOL CrossNes) Esimaed performance for 64x64 image fragmen Implemenaion Propagaion ime (s) Power (W) Energy per operaion (J) CPU 2.66 GHz [1] o 4 ~3 1-1 GPU 1 GHz [1] [] ~1 1-2 FPGA 2 MHz [1] ~1 1-3 ASIC 65 nm, 4 MHz [1] ~3 ~1 1-4 CMOL CrossNe 9 nm [2] ~3 1-8 ~1 ~3 1-8 CMOL CrossNe 1 nm [2] ~2 1-8 ~.1 ~2 1-9 [1] C. Farabe e al., Large scale FPGA based convoluional neworks, in: Machine Learning on Very Large Daa Ses, ed. by R. Bekkerman e al., Cambridge U. Press, 21, pp [2] K. Likharev, 212 (unpublished) June 213 Inel, Porland 4
5 Percepron: Main idea Single layer percepron Bias, x x 1 hw boleneck x w 1 2 w 9 x 3 y sgn[ w i x i ] i Binary pixel array x 1 x 4 x 7 x 2 x x x = +1 x 5 x 8 x 3 x 6 x 9 x = 1 w 9 w x 9 9 Considered raining/es paerns Percepron raining rule: w i = αx (p) i (d (p) y (p) ) Paern X, class d = +1 Crossbar implemenaion V x G + -G - = G w V V 1 V 9 V 2 G + G 1+ G + 2 G + 9 I + G G 1 G 2 G 9 I y = sgn[i I + -II - ] A A + param. analyzerbased Paern T, class d = 1 Alibar e al., Naure Comm, 213 June 213 Inel, Porland 5
6 Windrow s memisor AdaLiNe concep and hardware implemenaion Bernard Widrow Marcian Hoff June 213 Inel, Porland B. Widrow and M.E. Hoff, Jr., IRE WESCON Convenion Record, 4:
7 P/TiO 2-x /P devices g=i(.2v)/.2 V 1. S = 25 nm Au / 15 nm P op elecrode e beam 3 nm TiO 2 x paerned P prorusion 5 nm Ti / 25 nm P boom elecrode Curr ren (ma) 1. Alibar e al., Naure Comm, 213 S A Volage (V) V swich +V swich V 2 nm Any sae beween ON and OFF In principle dynamic sysem wih frequency dependen loop size bu. Srongly (superexp) nonlinear swiching dynamics Gray area = no change Sae defined wihin gray area June 213 Inel, Porland 7
8 Swiching dynamics volage se iniialize o R FF ime read rese iniialize o R N Small pulse amp = finer sae change bu may require exp long ime Large pulse amp faser bu a cruder sep RESET: R =R ON SET: R =R OFF R/R -2 mv (A) 1E-4 1E-5 June V o -.8V -.9V -1.V -1.1V -1.2V -1.3V 1x1-5 2x1-5 Time (s) Pulse volage (V) ( Inel, Porland E-8 1E-6 1E-4.1 Time (s) F. Alibar e al. Nanoechnology, , 212 8
9 Nonlinear swiching dynamics effecive barrier modulaion due o: 1 2 elecric field 1 heaing ~ k B T U A ion hopping iniial profile elecrode e oxidaion ion hoping z + + v z + elecrode e reducion 2 ~Eaq/2 energy 3 U A hop disance a 3 phase ransiion or redox reacion posiion J. Yang e al. submied 212 June 213 Inel, Porland 9
10 Speed vs. reenion linear ionic ranspor sore ~ wrie ( v ) ( v V ) V I D I V V T nonlinear effec due o emperaure and/or elecric field e.g. emperaure only: A A sore V kbtsore kbtwrie ~ ( e e wrie V T U U ) D.Srukov e al. Appl.Phys.A (29) June 213 Inel, Porland 1
11 Joule heaing K 14K 3K INTERMEDIATE I (ma) 5 ON OFF V (V) 6 Domain fied on daa Exrapolaion Local Tem mperaure (K) ON OFF SHORT I (ma) J. Borghei e al. JAP (29) June 213 Inel, Porland 11
12 Variaions in swiching behavior (I) RESET SET.6.8 Volag age (V) x1-6 4.x1-6 6.x1-6 8x1 8.x1-6 1.x1-5 Cu 2m mv (A) Cumulaive ime (s) Volage (V) x TiO 2 x devices 1.5x x1-7 1.x Cumula aive ime (s) 2 mv (A) Large swiching dynamics dispersion! Alibar e al., Naure Comm, 213 June 213 Inel, Porland 12
13 Variaions in swiching behavior (II) g = I(.2V)/.2 V Curren (ma) Volage (V) wrie 1 1 g INITIAL g AFTER /g SET S = une read RESET Syn ynapic weigh h, ms) Coninuous sae change ginitial (ms RESET Pulse volage (V) SET Alibar e al., Naure Comm, 213 June 213 Inel, Porland 13
14 Tuning algorihm Processing Wrie V WRITE = V WRITE +sign * T VSTEP oldsign = sign apply pulse V WRITE Sar (inpus: desired sae I desired, desired accuracy A desired ; iniialize: wrie volage o small non disurbing value V WRITE = 2 mv, volage sep T VSTEP = 1 mv; Read (apply V READ = 2 mv and read curren I curren ) Processing Is sae reached wihin required precision, i.e. (I desired I curren )/ I desired < A desired? yes no Processing check for overshoo and se he sign of incremen, i.e. sign = I curren I desired ; if V WRITE!=V READ and sign!=oldsign hen iniialize V WRITE = 2 mv Finish Inuiive algorihm volage se ime read rese Implemened algorihm volage se ime read rese non disurbing pulse F. Alibar e al. Nanoechnology, , 212 June 213 Inel, Porland 14
15 Percepron experimenal seup V Arbirary waveform generaor B153 A Swiching marix (Agilen E525A) Curren measuremen B153 (fas IV mode) Ground (GNDU, Agilen) Agilen B15 Wires implemening crossbar circui Chip packaged wire bonded memrisive devices Alibar e al., Naure Comm, 213 June 213 Inel, Porland 15
16 Percepron: Ex-siu raining s 1 s v read pulse v v s 2 wrie pulse s 2 Synapic weigh, g (m ms) g Evoluion of synapic conducance upon sequenial uning weigh impor accuracy ~1% final weighs afer programming g + uning g g + i+, i weigh slighly affeced by half selec problem. volage a g V swich -V swich Pulse number # Crossbar half selec rick Half seleced l ddevices slighly l affeced (>5 bi precision) ii Alibar e al., Naure Comm, June 213 Inel, Porland 16
17 g 1 + s 1 s 2 g 4 + g 1 - g 4 - Percepron: In-siu raining s 3 s 4 g ± i = ±αx i (d (p) y (p) ) Four seps α (V, g) V rain =.9V Evoluion of synapic conducance upon parallel uning V rain = 1V +V rain /2 v -V rain /2 v v s 1 =PS x=+1 volage a g1 + 1 x= s 2 =PS x= 1 1 s 3=PS + d=+1 volage a g 1 v -V rain volage a g - 1 v volage a g + 4 v g (ms) v +V swich -V swich s 4=PS d=+1 1 volage a g - 4 v Alibar e al., Naure Comm, 213 Training epoch June 213 Inel, Porland 17
18 In siu Training Example v +V rain/2 s 1 -V rain /2 +V swich -V swich s 2 s 3 s 1 s 2 s G + s 3 G s 4 s 4 STAR Phase T June 213 Inel, Porland 18
19 Sofware Simulaion Experimen vs. Simulaion V rain =.9V V rain = 1V ms) g (m w w w 1 w 2 w 3 w 4 w 5 8 w 6 w 7 w w Training epoch Training epoch Similar qualiaive behavior: (1) smooh vs. sudden changes, (2) convergence Alibar e al., Naure Comm, 213 June 213 Inel, Porland 19
20 Resuls Ex siu In siu 1 iniial Iniial (random (a weighs) X T 1 iniial X T Number of paerns accuracy weigh impor ~ 4% accuracy ~4% accuracy weigh impor ~ 1% accuracy ~1% Numb ber of paern ns accuracy weigh impor ~ 2% 1 accuracy ~2% 1 afer 1 epochs wih V rain =.9V afer 7 more epochs wih V rain =1V 1 rain June I + - I - (A) 3 bi is enough for considered ask Inel, Porland I + - I - (A) Alibar e al., Naure Comm, 213 2
21 Reraining Nework a V rain.9v 1V 1.1V Inversion of classes afer full raining b 1 INITIAL class inversion Num mber of Paern # T -1 X +1 T -1 X +1 X -1 T +1 X -1 T +1 X -1 T +1 G = G G (ms) Epoch # G G G G G G G G G G V rain.9v 1V 1.1V I + - I - (A) Iniialsae maers! Alibar e al., Naure Comm, 213 June 213 Inel, Porland 21
22 Big picure add on x 1 weigh x 1 g j1 memrisor CMOS sack x 2 w j1 y j x 2 w j2 x 3 w j3 x 3 g j2 + j3 x g i ji i CMOS CMOS cell Tigh inegraion wih CMOS logic (CMOL) Muli layer percepron nework Example of mapping of 64 inpu / 9 oupu percepron a inpu neurons (pixels) oupu neurons c memrisor crossbar add on CMOS sack inerface pin crossbar wire CMOS cell June 213 Inel, Porland 22
23 ADC and DAC Circuis 6-bi DAC 4-bi ADC (Hopfield Nework) Ampliude (V V) liude (V) Amp Inpu code experimenal resul Volage (V) Digial oupu 11 Analog inpu Inpu code Time (s) June 213 Inel, Porland 23. Digial Code L. Gao e al., NanoArch, 213
24 Summary Small scale paern classificaion experimenal demo Small scale paern recogniion and mixed signal circui experimenal demo Challenges: Device yield, variaions, CMOS inegraion i Work in progress: CMOS inegraion Large-scale sysem simulaion June 213 Inel, Porland 24
25 Govoreanu,e all IEDM, 212 Sae-of-he-Ar Performance 8) I V nonlineariy 1) densiy 9) number of saes 7) OFF sae resisance 1) reproducibiliy 2) endurance 5) reenion 6) ON/OFF curren raio 3) reciprocal swiching energy 4) swiching speed Endruance (cy ycles) 1E13 1E11 1E9 1E7 1, 1, sorage memory logic neuro demonsraed several groups Fujisu Labs HP Labs Panasonic Corp. SAIT ON Year OFF Cu (A) Kawahara e al. Panasonic, 212 1E-4 1E-5 Decrease Weigh Increase Weigh Sand-by (Read only) 12 A 6 A 3 A 15 A 7 A J. Yang, DBS, and D. Sewar Naure Nano (213) Srachan e al, Nanoechnology Schindler, PhD Thesis, 29 June 213 Pulse Number Inel, Porland 25 Torrezan e al, Nanoechnology Alibar e al, Nanoechnology , 212
26 (a) Hybrid CMOS/memrisor demo n anowire layer 2 (ianium) (c) (d) memrisive layer nanowire layer 1 (plainum) CMOS layer (b ) NOT gae NOT gae AND gae OR gae NAND gae AND gae NAND gae NOR gae D flip flop OR gae D flip flop June 213 NOR gae Inel, Porland Q. Xia e al. Nano Leers, 29 26
27 Thank You!
Pattern Classification and NNet applications with memristive crossbar circuits. Fabien ALIBART D. Strukov s group, ECE-UCSB Now at IEMN-CNRS, France
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