5 4 MI L P C V : E T s t e n s o h l m e a t o: C SOR T I T III /I O I ACI G N T I M V I N MI E O S D MES: A t e h e t e h c s, e t s t e

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1 C OURSE MATERIAL S ubject C ode : E C6504 Subject : Microprocesso r and Class : III Y ear E CE Microcontro ller D ept. of ECE

2 EC6504 MICROPROCESSOR AND MIC S S.NO CONTENT S PAGE.NO UNI T 1 THE 8086 MICROPROCES SOR 1 to I ntroduction to Microprocessor architectur e Addressing mo des Instruction set and assembler directive s A ssembly language programming Modular programmi ng Linking and Relo cation S tacks P rocedures Macro s In terrupts and interrupt service routines B yte and String Manipulation 40 UNI T SY STEM BUS STRUCTUR E signals B asic configurations S ystem bus timin System design using IO programmi ng Introduction to Multiprogrammi ng S ystem Bus Structure Multiprocessor configu rations C oprocessor Closely coupled and loosely Coupled configurat ions I ntroduction to advanced processors 58 D ept. of ECE

3 EC6504 MICROPROCESSOR AND MIC S UNI T 3 I/O INTERFA CING 65 to Memory Interfacing and I/ O interfacing Parallel communication interfac e S erial communication interface D/A and A/D Interfa ce Time r Keyboard /display controller I nterrupt controller DMA controller T raffic Light control 103 UNI T 4 MICROCONTROL LER 104 to Architecture of S pecial Function Registers( S FRs) I/O Pins Ports and Circu its I nstruction set Addressing mo des Assembly language programm i ng. 117 UNIT V INTERFACING MICROCON TROLLER 118 to Programming 8051 Time rs S erial Port Programming Interrupts Programmi ng L CD & Keyboard Interfaci ng ADC, DAC & Sensor Inte rfacing E xternal Memory Interface S tepper Motor and Waveform generation. 132 D ept. of ECE

4 EC6504 MICROPROCESSOR AND MIC S EC6504 MICROPROCESSOR AND MICROCO NTROLLER L T P C OBJECTIV E S: student should be made to: Study Architecture of 8086 microprocesso r. Learn design aspects of I / O and Memory Interfacing c ircuits. Study about communication and bus interfacing. Study Architecture o f 8051 microcon troll er. UNIT I THE 8086 MICROPROCESSO R 9 Introducti on to 8086 M icroprocessor a rchitecture A ddressing m odes - Instructio n s et an d assemble r d irectives A ssembly l anguage p rogramming M odular Programmin g - Linking Relocatio n - Sta cks - P rocedures Macro s I n terrupts and interrupt service routines Byte and Strin g Manipu l ation. UNIT II 8086 SY STEM BUS STRUCTURE s ignals B asic configurations S ystem b us timing S ystem d esign u sing 8086 I O programming In troduction t o Multiprogrammi ng System Bus Structure Multiprocessor configurations C oprocessor, Closely coupled and loosely Coupled configurations Introduction to advanced processo r s. UNIT III I/O INTERFACI NG 9 M emory Interfacing and I/O interfacing - P arallel communication interfac e Serial communication interf ace D / A A/D I nterface - Tim er Ke yboard / display controller I nterrupt contr oller DMA c ontroller P rogramming a pplications C ase studi e s: Tr affic Light control, L ED display, L CD display, Keyboard display interface and Alarm Controller. U NIT IV MIC 9 A rchitecture o f 8051 Specia l F unction R egisters(sfrs) - I / O P ins P orts C ircuits - Instructio n s et - Addressing m odes - Assembly language programming. U NIT V INTERFACING MIC 9 P rogramming 8051 Timers - Serial Port Programm ing - Interrupts Programm i ng L CD & Keyboard Interfacing - ADC, DAC & Sensor Interfacing - E xternal Memory Interface- S tepper Motor and W aveform generation. 45 PERIOD S OUTCOMES: A t end of course, student sho uld be able to: Design and implement program s on 8086 microprocesso r. Design I / O circuits. Design Memory I n terfacing circuits. Design and implement 8051 microcont roller based system s. T EXT BOOKS: 1.Yu-Cheng Liu, Glenn A.Gibson, Microcomputer Systems : 8086 / 8088 Fam ily - Architecture, 2. Programming and Design, Second Ed ition, Pren tice Hall of India, Mohamed Ali Mazidi, Janice Gillispie Mazidi, Rolin McKinlay, 8051 Microcontroller and Embedded REFERENCE: Systems: Using Assembly and C, Second Edition, Pea rson Ed ucation, D oughlas V.Hall, Microprocessors and Interfacing, Programming and Hardwar e :, T MH, 2012 D ept. of ECE

5 UNI T I THE 8086 MICROPROCESSOR 1.1 INTRODUCT ION It i s a semi conductor de vice c onsisting of electr onic log ic c ircuits manufacture d by using eir a Large scale (LSI) or Very Large Scale (VLSI) I n tegration Technique. I t i ncludes A LU, regis ter array s c ontrol cir cuits o n a sing le c hip. microproc essor has a s et o f i nstructions, d esigned internall y, to m anipulate c ommunicate periphera l s. era microprocessors in year 1971, Intel introduced first 4-bi t microprocessor is Using this first portable calculator is designed. 16-b it M icroprocessor famili es designe d primarily t o com plete m icrocomputers o riented t owards high-l evel langua g es. y h ave p owerful in struction s ets capable of addressing mega bytes of memory. e ra of 16-b it Microprocess ors began i n 1974 i ntroduction o f PA CE chip by N ational S emiconductor. T exas I nstruments T MS9900 w as i ntroduced i n y ear I ntel 8086 commercially a vailable i n y ear 1978, Z ilog Z 800 i n y ear 1979, Motorola MC68000 in yea r b it M icroprocessors a vailable i n d ifferent p in p ackages. E x: I ntel 8086/ p in p ackage Z ilog Z p in p ackage, Dig ital e quipment LSI-I I 40 p in p ackage, M otorola MC pin package National Semiconductor NS pin package. primary objectives of this 16- b it Microprocessor can be summarized as follows. 1. Increase memory a ddressing capability 2. Increase execution speed 3. Provide a powerful instruction set 4. Facilitate programming in high-level languag e s. 1.2 M icroprocessor Architecture: 8086 C PU i s d ivided i nto t wo i ndependent f unctional p arts, B us i nterface u nit ( BIU) and exe cu tion unit (EU). Bus I nterface U nit c ontains Bus Interface Logic, Se g ment registers, M emory addressing l ogic a S ix byte i nstruction o bject c ode q ueue. B IU s ends o ut a ddress, f etches i nstructions m emory, re ad da ta p orts m emory, w rites th e t o p orts memory. e xecution unit: con tains Data Addre ss reg isters, A rithmetic Log ic U nit, C ontrol U nit f lags. t ells B IU w here t o f etch i nstructions o r, d ecodes i nstructions e xecutes i nstruction. E U c ontains c ontrol circuitry whi ch d irects i nternal ope rat ions. A d ecoder in E U t ranslates instruc tions f etched memo ry i nto a se ries o f a ctions w hich E U c arries o ut. E U i s h as a 16-b it A LU w hich c an a dd, s ubtract, A ND, O R, X OR, i ncrement, d ecrement, c omplement o r s hift b inary n umbers. E U i s decoding an instruction or executing a n instruction which does not require use of buse s. I n o r w ords BI U h andles a ll transfe rs o f a ddresses on b uses exe cu tion unit. Queue: BIU fetches up to 6 instruction bytes for following instructions. B IU s tores se pre fetched byte s i n first-in-first-o ut r egister s et c alled a queu e. Wh en EU i s ready i ts next i nstruction i t simply r eads i nstruction b y te(s) for in struction q ueue i n B IU. T his is m uch f aster t han sendin g o ut a n a ddress t o sys tem memory waiting for memory to send back next instruction byte or by t es.. 1 DEPT. OF ECE

6 Fig Architecture 2 DEPT. OF ECE

7 E xcept i n c ase of JM P C ALL instructi o ns, where queue m ust b e d umped n reloade d s tarting a new a ddress, thi s prefetch-and-queue sch eme greatly s peeds u p p rocessing. F etching n ext i nstruction w hile current i nstruction execute s is called pipelining. W ord Read: Each of 1 M B memory a ddress o f 8086 r epresents a by te w ide location.16-b it words will be stored in two consecutive memory loc ations. If first byte of data i s stored at an even addres s, 8086 can read entire word in one opera t ion. For example if 16 bit data is stored at even address 00520H i s 9634H MOV B X, [00520H] 8086 r eads f irst byte s tores data i n B L r eads 2 nd by te an d s tores data in BH BL= ( 00520H) i. e. BL=34 H B H= (00521H) BH= 96H I f fir st by te o f da ta i s s tored a t a n o dd a ddress, 8086 n eeds t wo o perations t o read 16 bit data. For example if 16 bit data is stored at eve n address 00521H i s 3897H MOV B X, [00521H] I n f irst o peration, 8086 re ads 16 b it data from 00520H l ocation s tores o f 00521H l ocation i n r egister B L discard s dat a o f 00520H loc ation I n 2 nd o peration, 8086 r eads 16 b it 00522H l ocation s tores o f 00522H location in register BH and discards data of 00523H loca t ion. BL= ( 00521H) i. e. BL= 97H B H= (00522H) BH= 38H Byt e Rea d: MOV B H, [Addr] F or Even Addr es s: Ex: MOV BH, [00520H] 8086 r eads f irst by te l ocation and s tores da ta i n B H rea ds 2 nd by te from 00521H loc ation and ignores it B H = [ 00520H] For Odd Addres s MOV BH, [Addr] Ex: MOV BH, [00521H] 8086 r eads f irst byte 00520H l ocation an d i gnores i t r eads 2 nd byte from location and stores data in BH B H = [ 00521H] Physical address forma tion: 8086 a ddresses a s egmented memor y. c omplete phy sical address w hich i s 20- b its l ong i s generated us ing s egment offset r egisters each o f size 16-b it. c ontent o f a s egment r egister a lso c alled a s segme nt a ddress, and content o f a n o ffset r egister a lso c alled a s offs et a ddress. T o g et t otal phy sical a ddress, p ut l ower n ibble 0 H t o s egment addr ess an d a dd offse t addr e ss. Th e fig 1. 3 s hows formatio n o f 20-b it physical addr es s. 3

8 Fig 1.2 Physical Adress fo rmation. Register organizat i on of 8086: A ll r egisters o f b it r egisters. genera l p urpose regis t ers, c an be u sed eir 8-b it registers or 16-b it r egisters u sed ho lding th e, variables i ntermediate r esults temporarily o r o r p urpose l ike c ounter o r s toring o ffset ad dress s ome p articular a ddressing mo des e tc. spec ial p urpose regis ters us ed a s segme nt r egisters, p ointers, i ndex r egisters or a s of fset sto rage r egisters partic ular addressing modes. Fig 1. 3 F ig 1.3 Register or ganization of 8086 A X R egister: Accum ulator r egister c onsists o f t wo 8-b it r egisters AL A H, w hich c an b e c ombined toge r use d a s a 16- b it register A X. A L i n t his c ase c ontains low-o rder byte o f w ord, A H c ontains high-or der b y te. A ccumulator c an be used for I/ O operations, rotate and string m anipulation. B X R egister: T his registe r i s mainly use d a s a b ase r egister. I t h olds star ting b ase l ocation o f a memory r egion in a data s egment. I t i s u sed a s offse t s torage forming physical address in case of certain addressing m ode. C X R egister: I t i s u sed a s d efault counter - c ount r egister i n c ase o f stri ng l oop instruct ions. D X R egister: D ata regi ster c an b e u sed as a p ort n umber i n I / O ope rations i mplicit o perand o r d estination i n c ase o f f ew i nstructions. I n i nteger 32-b it multiply d ivide i nstruction D X r egister contains high-orde r wor d o f th e initia l o r resulting number. Segm ent re g isters: 1 Mbyte memory i s divid ed i nto 16 l ogical s egments. c omplete 1Mby te memory segmenta tion i s as s hown i n fig 1.4. E ach s egment c ontains 64Kby te o f memory. re four segment registe rs. C ode s egment ( CS) i s a 16-b it r egister c ontaining a ddress o f 64 K B segme nt wit h p rocessor i nstructions. processor u ses C S s egment a ll a ccesses to instr uctions r eferenced by i nstruction p ointer ( IP) r egister. C S r egister cannot b e changed directl y. 4

9 C S r egister i s automatically upda ted during far j ump, f ar c all and far retur n instruc t ions. I t is u sed addre ssing a memory l ocation i n code s egment of memory, where executable program is store d. S tack segm ent ( SS) i s a 16-b it r egister containi ng addr ess o f 64K B se gment p rogram s tack. B y d efault, p rocessor assumes a ll referenc ed by s tack p ointer ( SP) b ase p ointer ( BP) r egisters i s l ocated i n s tack segment. S S registe r c an b e chang ed directly u sing P OP i nstruction. It i s u sed for a ddressing s tack segme nt o f m emory. stac k s egment i s tha t s egment of memor y, which i s used t o sto re stac k data. D ata segm ent ( DS) i s a 16-b it r egister c ontaining a ddress o f 64KB s egment p rogram. B y d efault, p rocessor assumes a ll referenced by genera l r egisters ( AX, B X, C X, D X) i ndex r egister (S I, D I) i s l ocated i n se g ment. D S r egister c an b e changed directly u sing P OP L DS i nstructions. It p oints to data segment memory where data is reside d. E xtra segm ent ( ES) i s a 16-b it r egister conta ining address o f 64K B segm e nt, usually p rogram. B y d efault, p rocessor assu mes D I r egister referenc es ES segment in s tring m anipulation i nstructions. ES r egister can be changed directly u sing P OP L ES i nstructions. I t a lso r efers t o s egment w hich e ssentially i s a nor data segment of memory. It also contains data. Fi g1. 4. Memory segme ntation Pointers and inde x registe rs. p ointers c ontain in p articular s egments. p ointers I P, B P, S P usually contain offsets within code, data and stack segments respectivel y Stac k Point er ( SP) is a 16-bit register pointing to program stack in stack segme n t. B ase P ointer ( BP) i s a 16-b it register p ointing to i n s tack s egment. B P r egister i s usually used for based, based indexed or register indirect addressing. S ource Inde x ( SI) i s a 16-b it r egister. SI i s u sed index e d, b ased indexe d r egister indirect addressing, as well as a source data addresses in string manipulation instruc t ions. 5

10 D estination I ndex ( DI) i s a 16-b it r egister. D I i s u sed for index e d, bas ed indexe d r egister i ndirect addressi n g, a s w ell a s a destinat ion a ddress i n strin g m anipulation instruc t ions. Flag Regist er : Fi g. 1.5 Fl ag Register F lags R egister determines current s tate of proc e ssor. y m odified automatically by C PU a fter mamatic al o perations, t his allow s t o d etermine type o f r esult, and t o d etermine conditions t o t ransfer c ontrol t o o r p arts o f p rogram f lag r egister a s shown in fig has 9 active flags and y divided into two categories: 1. Conditiona l Flags 2. Contr ol Flags Conditional Fl ags C arry Flag ( CY ): T his f lag indic ates an overf low conditio n unsig ned integ er arithmetic. It is also used in multiple- p recision arithmetic. A uxiliary Flag (AC): I f a n operation performed in A LU gene rates a carry/ b arrow l ower n ibble ( i.e. D0 D3) t o u pper n ibble ( i.e. D4 D7 ), th e A C f lag i s s et i.e. carry g iven by D3 b it t o D4 i s A C fla g. T his i s n ot a general-purpose fl a g, i t is us ed internally by Processor to perform Binary t o BCD conversion. P arity F lag ( PF) : T his f lag i s use d t o i ndicate parity o f r esult. I f l ower order 8-b its o f r esult c ontains e ven n umber o f 1 s, Parity F lag i s s et odd n umber o f 1 s, Parity flag i s reset. Z ero F lag ( ZF) : I t i s set; i f re sult o f a rithmetic o r log ical operatio n i s ze ro e lse it i s rese t. S ign F lag (S F ): I n s ign m agnitude mat sig n o f number i s i ndicated by MSB b it. If result of operation is negative, sign flag i s set. Contr ol Fl ags Control flags are set or reset deliberately to control operations of exe cu tion unit. Control flags ar e a s f o llows: T rap F lag ( TF) : It i s u sed for single s tep control. I t a llows u ser t o exe cute o ne i nstruction o f a prog ram a t a t ime debuggin g. W hen t rap f lag i s s et, progra m c an be run in single step mode. I nterrupt F lag ( IF) : I t i s a n i nterrupt enable/ dis able f lag. I f i t i s s et, maskab le i nterrupt o f 8086 i s enabl ed i f i t i s r eset, i nterrupt i s disabl e d. I t c an b e se t by executing instruction sit and can be cleared by executing CLI i nstruction. D irection F lag ( DF) : I t is u sed i n s tring operation. I f i t i s s et, s tring by tes acce ssed h igher memory a ddress t o l ower m emory a ddress. W hen i t i s r eset, s tring bytes are accessed from lower memory address to higher memory a ddress. 1.3 A ddressing Modes 8086 has 12 addressing modes can be c lassified into five groups. Addressing modes for accessing immediate and register data (regi ster and immediate m odes). Addressing modes for accessing data in memory ( memory m odes) 6

11 Addressing modes for accessing I / O ports ( I / O modes) Relative addressing m ode Implied addressing m ode Immediate addr essing m o de: In t his m ode, 8 o r 16 bit c an be specified a s p art of instruction - O P C ode I mmediate Operan d E xample 1: MOV CL, 03 H:Moves 8 bit data 03 H into CL Example 2: MOV DX, 0525 H: Moves 16 bit data 0525 H into DX I n a bove two ex a mples, s ource ope rand i s i n i mmediate m ode destination operand is in registe r mode. A constant such as VALUE ca n b e d efined by a ssembler E QUATE d irective s uch as VALU E E QU 35H Example: MOV B H, VALU E Used to loa d 35 H i nto BH Register addressing m o de: operand to be accessed is specified as residin g in an internal register of T able 1.1 b elow s hows i nternal r egisters, any one can b e u sed a s a s ource or d estination operand, however only datgisters can be accessed as eir a by t e or word. T able 1.1 I nternal registers of 8086 Example 1 : MOV DX (Destination Register), CX (Source Register) Which moves 16 bit content of CS into D X. Example 2 : M OV CL, DL Moves 8 bit contents of DL i nto CL MOV B X, CH is an illegal instruc t ion. * registe r sizes must be same. Direct addressing m o de: i nstruction O pcode i s f ollowed by a n affecti ve a ddress, t his effective a ddress i s d irectly u sed a s 16 bit o ffset o f storag e l ocation o f o perand from l ocation s pecified by c urrent v alue i n selecte d segmen t re g ister. d efault s egment i s alway s DS. 20 b it p hysical addre ss o f o perand i n me mory i s normally obtain ed a s P A = DS: EA 7

12 B ut b y u sing a segment o verride prefix ( SOP) i n segment registers can be reference d, i nstruction, any o f f our F ig 1.6 Physical address generati on of 8086 E xecution U nit ( EU) h as d irect a ccess t o a ll r egisters for reg ister i mmediate o perands. H owever E U c annot directly a ccess memory operands. It must use BIU, in order to access memory o perands. I n d irect addressing m ode, 16 b it e ffective a ddress ( EA) i s t aken directly fr om displacement field of instruc t ion. Example 1 : MOV CX, ST ART I f 16 b it v alue a ssigned to offset S TART b y prog rammer u sing a n a ssembler p seudo i nstruction s uch a s D W i s 0040 [DS] = n BIU generates 20 b it phy s ical address H. content of is moved to CL content of is moved to CH Example 2 : M OV CH, ST ART I f [DS] = 3050 and START = bit content of memory location is move d to CH. Example 3 : MOV START, BX W ith [ DS] = 3050, value of ST AR T is Phys ical address: MOV instruction moves (BL) and ( BH) to locations and respective l y. Register indirect addressing m o de: E A i s s pecified i n e ir p ointer ( BX) r egister o r a n index ( SI o r D I ) r egister. 20 bit physical address is computed using D S and EA. Example: MOV [DI], BX register indirect If [DS] = 5004, [DI] = 0020, [Bx] = 2456 PA= content of BX(2456) is moved to memory l ocations H and H. w hen memory i s accessed P A i s c omputed B X PA is computed from B P a n d SS. Example: MOV AL, ST A RT [BX] o r MOV AL, [STAR T + B X] based mode D S whe n tack 8 s i s accesse d

13 EA: [START] + [B X ] PA: [DS] + [ EA] 8 bit content of this memory location is moved to AL. String addressing mode: s tring i nstructions automatically a ssume SI t o p oint t o f irst by te or w ord o f s ource o perand and DI to p oint t o f irst byte or w ord of de stination op erand. c ontents o f S I D I automatically increme nted (by c learing D F t o 0 b y CL D instruction) to point to next by t e or word. Example: MOV S BYT E If [DF] = 0, [DS] = 2000 H, [ SI ] = 0500, [ ES] = 4000, [DI] = 0300 Source address: 20500, assume it contai ns 38 PA: [DS] + [SI] Destination address: [ES] + [DI] = 40300, assume it contai ns 45 I/ O mode (direct): Port number is an 8 bit immediate ope ran d. Example: OUT 05 H, AL Outputs [AL] to 8 bit port 05 H I/O mode (indirect): port number is take n D X. Example 1: IN AL, DX I f [DX] = bit content by port 5040 is moved into AL. E xample 2: IN AX, DX Inputs 8 bit content of ports 5040 and 5041 into AL and AH respectively. R elative addressing mode: E xample: JNC START 9

14 I f C Y=O, n P C i s l oaded c urrent P C START, orwise next instruction is execute d. Im plied addressing m o de: Instruction using this mode have no opera n ds. Example: CLC which clears carry flag t o zero. c ontents p lus 8 bi t si g ned alue v o f Fi g 1.7 Summary of 8086 addressing mo des 1.4 INSTRUCTION SET OF instructions are categorized into following main type s. 1. Data Copy / Transfer In structions 2. Arithmetic and Logical Instruct ions 3. Shift and Rotate In structions 4. L oop In structions 5. B ranch Instruction s 6. String Instru ctions 7. Flag Manipulation Instruct ions 8. Machine Control Instruct ions Data Copy / Transfer Instruc t ions: MOV: 10

15 This instruction copies a word or a byte of data from some source to a destina t ion. destination can be gister or a memory l ocation. source can be gister, a memory location, or an immediate numbe r. MOV A X, BX MOV AX, 5000H MOV AX, [SI] MOV AX, [2000H] MOV AX, 50H[B X ] MOV [734AH], BX MOV DS, CX MOV CL, [ 357AH] Direct loading of segment registers with immediate data is not pe r mitted. P USH: P ush to Stack T his i nstruction p ushes c ontents o f s pecified register/memory loc ation o n t o stack. stack pointer is decremented by 2, after each exec ution of i nstruction. E. g. PUSH AX PUSH DS PUSH [5000H] POP : Pop from S tack T his i nstruction w hen e xecuted, l oads specified register/memory locatio n c ontents o f memory l ocation o f w hich add ress i s med using stack segment and stack pointer. stack pointer is incremented by 2 Eg. P OP A X P OP D S POP [5000H] c urrent Fig 1.8 P ush into and Popping Register Content from Stack Memo ry XCHG: Exchange byte or word T his instruction exchange contents of specified source and destination operan ds Eg. XC HG [5000H], AX 11

16 XCHG BX, AX X L AT: Translate byte using look-u p table Eg. L EA BX, TABLE 1 MOV AL, 04H XLAT Input and output port transfer instruct ions: I N : Copy a by t e or word from specified port to accumulator. Eg. IN AL, 03H I N AX,DX OU T : Copy a by t e or word from accumulator specified port. Eg. O UT 03H, AL O UT DX, AX L EA: Load effective address of operand in specified registe r. [ reg ] offset portion of addres s in DS Eg. LEA reg, offset L DS: Load DS register and or specified register from memory. [ reg] [ me m ] [ DS] [mem + 2] Eg. LDS reg, mem L ES: Load ES register and or specified register from memory. [ reg] [ me m ] [ ES] [ me m + 2 ] Eg. LES reg, mem Flag transfer instruc ti ons: LAHF: Load (copy to) AH with low byte flag r egister. [ AH] [ Flags low by t e] Eg. LAHF SAHF: Store (copy) AH register to low byte of flag reg i ster. [ Flags low by t e] [AH] Eg. S AHF PUSHF: Copy flag reg i ster to top of stack. [ SP] [ S P] 2 [[SP]] [ Flag s ] Eg. PUSHF POPF: Copy word at top of stack to flag register. [ Flags] [[ SP ]] [ SP] [ SP ] Arithmetic Instructions: 12

17 8086 provides many a rithmetic operatio n s: a ddition, s ubtraction, n egation, multiplication and comparing two value s. AD D : add instruction adds contents of source operand to destination ope ra nd. Eg. AD D A X, 0100H A DD AX, BX ADD AX, [SI] AD D AX, [5000H] ADD [5000H], 0100H ADD 0100H A DC: Add with Carry T his i nstruction performs same o peration a s A DD i nstruction, but add s th e carry flag to re s ult. Eg. ADC 0100H AD C AX, BX ADC AX, [SI] ADC A X, [5000] A DC [5000], 0100H SUB: Subtract s ubtract instruc tion s ubtracts sourc e ope rand de stination o perand result is left in destination ope ran d. Eg. SUB A X, 0100H SUB AX, BX SUB AX, [5000H] SUB [ 5000H], 0100H SBB: Subtract with Borro w s ubtract borrow i nstruction s ubtracts th e s ource o perand th e borrow flag ( CF) w hich may reflect r esult o f p revious c alculations, d estination operan d Eg. SBB AX, 0100H SB B A X, BX SB B AX, [5000H] SB B [ 5000H], 0100H I NC: Incremen t Th is instruction increases contents of specified Register or memory location by 1. Immediate data cannot be operand of this instruc t ion. Eg. IN C AX IN C [ BX] IN C [5000H] DEC: Decremen t decrement instruction subtracts 1 from contents of specifie d registe r o r memory loca t ion. Eg. D EC AX DEC [5000H] NEG: Negate negate instruction forms 2 s complement of specified destination in instruct ion. destination can be gister or a memory locat ion. T his i nstruction can be implemented by inverting each bit and adding 1 to it. Eg. N EG AL AL = H Replace number in AL with its 2 s complemen t AL = = CBH 13

18 CMP: Comp are This instruction compares source operand, which may b e gister or an immediate data or a memory location, with a destination operand that may b e gister or a memory locat ion Eg. CMP BX, 0100H CMP AX, 0100H CMP [5000H], 0100H CMP BX, [ SI] CMP BX, CX MUL:Unsigned Multiplication Byte or W ord This instruction multiplies an unsigned byte or word by contents of AL. Eg. M UL BH; ( AX ) (AL) x (BH) MUL C X; (DX)(AX) (AX) x (CX) MUL WORD PTR [SI]; (DX)(AX) (AX) x ([ SI ]) IMUL:Signed Multiplicati on This instruction multiplies a signed byte in source operand by a signed byt e in AL or a signed word in source operand by a sig n ed word in AX. Eg. IMUL B H IMUL C X IMUL [ SI] CBW: Convert Signed Byte to Word This instruction copies sign of a byte in AL t o all bits in AH. A H is n said t o be sign extension of AL. Eg. CBW AX= Convert signed byte in AL sig n ed word in AX. Res ult in AX = CWD: Convert Signe d Word to Double Word This instruction copies sign of a byte in AL t o all bits in AH. A H is n said t o be sign extension of AL. Eg. CWD Convert signed word in AX to sign ed double word in DX: AX DX= Re s ult in AX = DIV: Unsigned division T his i nstruction i s u sed t o d ivide a n unsigne d wor d by a by te or t o divide a n unsigne d double word by a word. Eg. DIV CL; Word in AX / byte in CL; Quotient in AL, remainder in AH D IV CX; D ouble w ord in D X A X / w ord; i n C X, Q uotient i n A X; remain der in DX AAA: ASCII A djust Aft er Additi on A AA i nstruction i s exe cuted afte r a n A DD in struction a dds t wo ASCI I code d o perand t o g ive a byte o f r esult i n A L. A AA inst ruction c onverts r esulting contents of Al to a unpacked decimal dig i ts. Eg. A DD C L, D L ; [C L ] = 32H = ASCI I 2 ; [ DL] = 35H = ASCI I 5 ; R esult [ C L] = 67H MOV AL, CL; Move ASCII result into AL since; AAA adjust only [ AL] AAA; [AL] =07, unpacked B CD for 7 AAS: ASCII Adjust AL afte r Subtracti on T his i nstruction c orrects r esult i n A L r egister a fter subtracting t wo unpa cked ASCI I oper an ds. re sult i s i n unpacked decimal for m at. procedure i s s imilar to A AA instruction except for subtract ion of 06 from AL. AAM: ASCII Adjust aft er Multiplicati on 14

19 T his i nstruction, a fter e xecution, c onverts p roduct a vailable I n AL i nto u npacked BCD forma t. Eg. M OV AL, 04; AL = 04 MOV BL, 09; BL = 09 MUL BL; AX = AL* BL; AX=24H A AM; AH = 03, AL= 06 AAD: ASCII Adjust befor e D ivision T his i nstruction c onverts t wo u npacked B CD d igits i n A H A L t o e quivalent b inary n umber i n A L. T his a djustment m ust b e m ade befor e d ividing tw o u npacked B CD d igits i n A X b y a n u npacked B CD b y te. I n i nstruction sequenc e, t his instruction appears Before DIV instruc t ion. Eg. AX AAD result in AL 00 3A 58D = 3 A H in AL r esult o f A AD execu tion w ill g ive hexa decimal n umber 3A i n AL 00 i n AH where 3A is hexadecimal Equivalent of 58 ( de ci mal). DAA: Decimal Adjust Accumu lator T his i nstruction i s used t o c onvert r esult of th e additio n o f two packed B CD numbers to a va lid BCD number. result has to be only in AL. Eg. AL = 53 CL = 29 ADD AL, CL; AL ( AL) + ( CL) ; AL ; AL 7 C DAA; AL 7 C + 06 (as C> 9); AL 82 DAS: Decimal Adjust after Subtracti on T his i nstruction conver ts r esult o f subtracti on o f t wo packe d B CD n umbers to a va lid BCD number. subtraction has to be in AL only. Eg. A L = 75, B H = 46 SUB AL, BH; AL 2 F = ( AL ) - (B H ) ; AF = 1 DAS; AL 2 9 (as F>9, F - 6 = 9 ) Logical in structions A ND : Logica l AND T his i nstruction b it b y b it A NDs s ource o perand may b e a n immed iate r egister o r a m emory l ocation t o d estination ope rand m ay a r egister or a m emory locat ion. result is stored in destination oper an d. Eg. AN D A X, 0008H A ND AX, BX OR: Logica l OR T his instruction b it b y bit ORs source operand that may be a n i mmediate, r egister o r a memory l ocation t o destinat ion o perand m ay a r egister o r a memory loc a tion. result is stored in destination ope ran d. Eg. OR AX, 0008H OR AX, BX NOT: Logical Invert T his i nstruction c omplements c ontents o f a n o perand reg ister o r a me mory loc a tion, bit by b it. Eg. NOT AX N OT [5000H] OR: Logical Exclusive O R 15

20 T his i nstruction b it by bit X ORs s ource o perand may b e a n imm ed iate, reg ister o r a m emory l ocation t o d estination o perand m ay a r egister or a memory locat ion. result is stored in destination oper an d. Eg. XOR AX, 0098H XO R AX, BX TEST: Logical Compare Instructi on TEST instruction p erforms a b it by b it logical A ND o peration o n t wo o perands. r esult o f t his ANDi ng ope ration is n ot ava ilable for fur r u se, b ut flag s affecte d. Eg. TE ST AX, BX T EST [0500], 06H Shift and Rotate Instructi ons SAL/SH L: SAL / SH L destination, count. S AL S HL two m nemonics s ame i nstruction. T his i nstruction s hifts each b it i n s pecified destin ation t o l eft 0 is stor ed a t LSB p osition. M SB is s hifted i nto carry fl a g. d estination can b e a by te or a w ord. I t c an b e i n a register or in a memory locat ion. number of shifts is indicated b y count. Eg. SAL CX, 1 SAL A X, CL S HR: SHR destination, co unt T his i nstruction s hifts e ach b it i n s pecified d estination t o r ight 0 i s s tored a t M SB p osition. LSB i s s hifted i nto carry fl a g. d estination c an b e a by te o r a w ord. It can be gister or in a memory l ocation. number of shifts is indic a ted by count. Eg. SHR CX, 1 MOV CL, 05H S HR AX, CL SAR: SAR destinat ion, co unt T his i nstruction s hifts e ach b it i n s pecified d estination s ome n umber o f b it p ositions t o r ight. A s a b it i s shifted o ut o f M SB p osition, a copy o f th e o ld M SB i s pu t i n MSB p osition. LSB will be shifted into CF. Eg. SAR BL, 1 MOV CL, 04H S AR DX, CL R OL Instruction: ROL destination, count This instruction rotates all bits in a specified by te or word to l eft some number of bit positions. MSB is placed as a new LSB and a new CF. Eg. ROL CX, 1 MOV CL, 03H ROL B L, CL ROR Instruction: ROR destination, co unt T his i nstruction r otates a ll b its i n a s pecified by te o r w ord t o r ight s ome n umber o f b it p ositions. LSB is placed as a new MSB a new CF. Eg. R OR CX, 1 MOV CL, 03H ROR BL, CL RCL Instruction: RCL destinat ion, co unt T his i nstruction r otates a ll b its i n a s pecified by te o r w ord s ome n umber o f b it p ositions t o l eft a long carry f lag. M SB i s p laced a s a n ew carry p revious carry i s place as new LSB. Eg. RCL C X, 1 MOV CL, 04H 16

21 RCL A L, CL R CR Instruction: RCR destination, count T his i nstruction r otates a ll b its i n a s pecified by te o r wor d s ome n umber o f b it p ositions t o r ight a long c arry flag. L SB i s p laced a s a ne w carry previo us carry is plac e as new MSB. Eg. R CR CX, 1 MOV CL, 04H RCR AL, CL ROR Instruction: ROR destination, co unt T his i nstruction r otates a ll b its i n a specif ied byte o r wor d t o rig ht som e n umber of b it p ositions. LSB is placed as a new MSB a new CF. Eg. ROR C X, 1 MOV CL, 03H ROR BL, CL RCL Instruction: RCL destinat ion, co unt T his i nstruction r otates a ll b its i n a s pecified by te o r w ord s ome numbe r o f b it p ositions t o l eft a long carry f lag. M SB i s p laced a s a n ew carry p revious carry i s place as ne w LSB. Eg. RCL C X, 1 MOV CL, 04H RCL A L, CL R CR Instruction: RCR destination, count T his i nstruction r otates a ll b its i n a s pecified by te o r w ord s ome n umber o f b it p ositions t o r ight a long c arry flag. L SB i s p laced a s a ne w carry p revious carry is plac e as new MSB. Eg. R CR CX, 1 MOV CL, 04H RCR AL, CL L oop Instructions: Unconditional LOOP Instructi ons LOOP: LOOP Unconditi onally T his i nstruction e xecutes p art o f p rogram L abel o r addr ess s pecified i n i nstruction u pto L OOP i nstruction CX num ber of t imes. At e ach i teration, C X i s decremented automatically and JUMP IF NOT ZERO structure. Example: MO V C X, 0004H C onditional LOOP Instruct ions LOOPZ / LOOPE Label Loop through a sequence of instructions from label while ZF= 1 and CX= 0. LOOPNZ / LOOPE NE Label Loop through a sequence of instructions from label while ZF= 1 an d CX= Branch Instructi on s: B ranch I nstructions t ransfers flow o f execution o f prog ram t o a new a ddress spe cified i n instruction directly or indirectly. When this ty pe of instruction is e xecuted, CS I P r egisters g et l oaded n ew v alues o f C S I P corresponding t o l ocation t o b e transferr ed. B ranch Instructions are classified into two types 1. Unconditional Branch Instruc t ions. 2. Conditional B ranch Instruc t ions Unconditional B ranch Instructions: 17

22 I n U nconditional c ontrol t ransfer i nstructions, exe cution c ontrol i s t ransferred t o s pecified l ocation i ndependent o f any status o r c ondition. C S an d I P unconditionally modified to new CS and I P. CALL: Unconditi onal Ca ll T his i nstruction i s u sed t o c all a S ubroutine ( Procedure) a m ain progr a m. A ddress o f p rocedure may b e s pecified directly or indirectl y. re t wo ty pes o f p rocedure depending upon wher it is available in same segment or in anor seg m ent. i. N ear CALL i.e., ± 32K displaceme n t. ii. For CALL i.e., anywhere outside seg m ent. O n exe cution t his i nstruction s tores i ncremented I P & C S o nto s tack l oads CS & IP registers with segment and offset addresses of procedure to be calle d. RET: Return from Procedur e. At end of procedure, RET instruction must be executed. W hen it is ex e cuted, previously stored con tent o f I P and C S a long wi th F lags are retrieved i nto CS, I P F lag r egisters s tack execu tion o f m ain p rogram c ontinues fur r. INT N: Interrupt Type N. I n i nterrupt struc ture o f 8086, 256 i nterrupts d efined corresponding t o type s from 00H to FF H. When INT N instruction is executed, t ype by te N is m ultiplied by 4 c ontents o f I P C S o f interrup t s ervice r outine w ill be t aken memory block in 0000 seg m ent. INTO: Interrupt on Overf low T his i nstruction i s ex e cuted, w hen over flow f lag OF i s s et. T his i s e quivalent t o a Ty pe 4 I n terrupt instruction. JMP: Unconditional Jump T his i nstruction unconditionally t ransfers co ntrol o f exe cution t o s pecified address using an 8-bit or 16-bit displacem ent. No Flags are affected b y this instruction. IRET: Return from I SR W hen i t i s e xecuted, v alues o f I P, C S F lags r etrieved from s tack t o continue execution of main progr am. MOV BX, 7526H Label 1 MOV AX, CODE O R BX, AX L OOP Label Conditional B ranch Instructions W hen t his i nstruction i s ex e cuted, exe cution c ontrol i s t ransferred to addre ss s pecified relatively in i nstruction, provide d th e c ondition i mplicit i n th e Opcode i s satisfi ed. Orwise execution continues sequentially. JZ/ JE Label Tr ansfer execution control to address Label, if ZF= 1. JNZ/ JNE Label T ransfer execution control to address Label, if Z F= 0 JS Label Transfer execution control to address Label, if SF= 1. JNS Label Transfer execution control to address Label, if SF= 0. JO Label Transfer execution control to address Label, if OF = JNO Label T ransfer execution control to address Label, if OF = 0. JNP Label 18

23 Transfer execution control to address Label, if PF= 0. JP Label Transfer execution control to address Label, if P F= 1. JB Label T ransfer execution control to address Label, if C F = 1. JNB Label Transfer execution control to address Label, if C F = 0. JC XZ Label Transfer execution control to address Label, if C X= String Manipulation Instructi ons A s eries o f byte or w ord a vailable i n mem ory a t c onsecutive l ocations, t o b e r eferred a s Byte S tring o r W ord S tring. A S tring o f chara cters may b e l ocated i n c onsecutive memory l ocations, w here each c haracter may b e represente d by i ts ASCI I equivale n t s upports a s et of m ore powerfu l instructions string manipulations for referring to a string, two parameter s are requir ed. I. Starting and End Address of String. II. Length of String. leng th o f string i s usually s tored a s c ount i n C X registe r. incrementing or d ecrementing o f p o inter, i n s tring i nstructions, d epends u pon D irection F lag ( DF) S tatus. I f i t i s a By te s tring o peration, index r egisters updated by o ne. On or hand, if it is a word string operation, index registers are updated by t wo. REP : Repeat Instruction Pref ix T his i nstruction i s u sed a s a prefix t o o r i nstructions, in struction to w hich R EP p refix i s p rovided, i s exe cuted repeatedly un til C X r egister becom es z ero ( at each iteration CX is automatically decremented by o ne). i. REPE / RE PZ - repeat operation while equal / ze ro. i i. REPNE / REPNZ - repeat opera tion while not equal / not ze ro. se are used for CMPS, SCAS instructions only, as instruction prefixe s. MOVSB / MOVSW: Move String Byte or String Word S uppose a s tring o f b ytes s tored i n a s et o f c onsecutive memory l ocations i s t o b e m oved t o a nor s et of d estination l ocations. s tarting by te o f sou rce string i s l ocated i n m emory l ocation w hose a ddress m ay b e c omputed using SI ( Source I ndex) and D S ( Data S egment) c ontents. s tarting a ddress of d estination l ocations w here t his strin g ha s t o be relocated is give n by D I ( Destination Index) ES (Extra Segme nt) conte n ts. CMPS: Compare String Byte or String Word C MPS i nstruction c an b e us ed t o c ompare t wo s trings o f by te o r word s. l ength o f s tring m ust b e s tored i n regis ter C X. I f b oth b yte or w ord s trings equal, ze ro Flag is se t. R EP i nstruction P refix i s u sed t o r epeat o peration t ill C X ( counter) b ecomes z ero or condition specified by REP Pre fix is F al se. SCAN: Scan String Byt e or String Word T his i nstruction s cans a s tring of byte s o r w ords a n ope rand by te or wo rd specifie d i n re gister A L o r A X. S tring i s p ointed to by E S: DI r egister p air. leng th of s tring s stored i n C X. DF c ontrols th e m ode scanning o f strin g. W henever a m atch t o specifie d oper i s fou nd i n s tring, executio n s tops ze ro Flag i s set. If no match is found, zero flag is rese t. LODS: L oad String Byte or String Word L ODS i nstruction l oads AL / A X register by c ontent o f a string p ointed t o b y D S: SI r egister p air. SI i s m odified automatically depending upon D F, I f i t i s a 19

24 ROCONT ROLLER b yte transfer ( LODSB), th e SI i s m odified by o ne i f i t i s a w ord t ransfer ( LODSW ), SI is modified by t wo. No or Flags are affected by this instruc t ion. STOS: Store String Byte or Stri ng Word S TOS i nstruction S tores AL / AX registe r conte nts t o a loc ation i n th e string p ointer b y E S: D I r egister p air. D I i s m odified accordingl y, N o F lags affe cted by this instruc t ion. d irection F lag c ontrols S tring instruction ex e cution, source index SI D estination I ndex D I ar e m odified a fter e ach i teration automaticall y. I f D F =1, n e xecution f ollows a uto decreme nt m ode, SI and DI decremented automatically a fter e ach i teration. I f D F=0, th en exe cution f ollows a uto i ncrement m ode. I n t his m o de, SI and DI are incremented automatically a fter each iteration F lag Manipulation and a P rocessor Control Instructi ons se i nstructions c ontrol func tioning of ava ilable hardware i nside th e processor ch ip. se instructions are categorized into two ty p es: 1. Flag Manipulation instruc t ions. 2. Machine Control instruc t ions. F lag Manipulation instru ctions Flag manipulation instructions directly modify some of Flag s of i. CL C Clear Carry Flag. ii. C MC Complement Carry F l ag. i ii. S TC Set Carry F la g. iv. CL D Clear Direction Flag. v. S TD Set Direction Flag. vi. CLI Clear I nterrupt Flag. v ii. S TI Set I nterrupt Flag Machine Control instruct ions Machine control instructions control bus usage execu tion i. WAI T W ait for Test input pin to go low. ii. HL T Halt proce s s. i ii. N O P N o o peration. iv. E SC Escape to external devic e like NDP v. LO C K Bus lock instruction pre fi x. Assembler directive s : A ssembler d irectives h elp a ssembler t o correctly u nderstand assembly lang uage p rograms t o pr epare c odes. A nor ty pe o f h int w hich he lps ass embler t o assign a p articular c onstant with a labe l o r i nitialize p articular memory l ocations o r l abels c onstants i s c alled a n operator. R ar, ope rators p erform a rithmetic l ogical t asks u nlike d irectives j ust d irect a ssembler to correctly i nterpret p rogram t o c ode i t appropriately. f ollowing d irectives commonly u sed i n assembly lang uage programming practice using Microsoft Macro Assembler ( MASM) or Tur bo Assemble r ( TASM). DB: Define Byt e DB directive is used to reserve byte or byt es of memory locations i n a vailable m emory. W hile p reparing E XE f ile, t his d irective d irects a ssembler t o a llocate s pecified n umber o f memory byte s to s aid type that m ay b e a c onstant, v ariable, s tring, e tc. A nor o ption o f t his dire ctive a lso i nitializes rese rved memory by tes with ASCII codes of characters specified as a string. following exa mples show how DB directive is used for different purpose s. Example: LIS T DB 0lH, 02H, 03H, 04H T his s tatement d irects a ssembler t o r eserve f our memory l ocations a l ist n amed L IST and initialize m with above specifie d four value s. M ESSAGE DB ' GOOD MORNI N G' 20

25 T his m akes asse mbler reserve n umber of by tes of memory equa l t o number o f c haracters i n s tring n amed M ESSAGE and i nitialize t hose l ocations by ASCI I equivalent of se characters. D W: D efine Word. D W d irective s erves s ame purpose s a s D B directi v e, b ut i t n ow m akes asse mbler rese rve numbe r o f memory w ords ( 16- b it) i nstead o f b y tes. Some examples are given to expla in this dire ct ive. Examples WORDS DW 1234H, 4567H, 78ABH, 045CH T his m akes assemble r rese rve f our w ords in memory ( 8 byt e s), and initializ e w ords s pecified values i n statement s. During i nitialisation, l ower byte s store d a t lower memory addr e sses, w hile u pper byte s s tored a t highe r addr e sses. A nor option of DW directive is explained with DUP operator. WDATA DW 5 DUP (6666H) T his s tatement reserves f ive w ords, i.e. 10-bytes o f memory a w ord labe l W DATA initializes all word loc ations with 6666H. D Q: D efine Q uad wo rd T his d irective i s u sed t o d irect a ssembler t o r eserve 4words (8 bytes) of memory specified variable and may initialize it with specified value s. D T: D efine T en B ytes. D T d irective d irects a ssembler t o de fine s pecified v ariable r equiring la-by tes i ts s torage i nitialize 10bytes s pecified v alues. d irective may b e u sed i n c ase o f variable s facing heavy numeric al c alculations, generally processed by numerical processor s. ASSUME: A ssume L ogical S egment N ame A SSUME d irective i s u sed t o i nform a ssembler, names o f log ical s egments t o b e assumed differen t segme nts u sed i n p rogram. I n a ssembly l anguage p rogram, e ach s egment i s g iven a n ame. F or e xample, c ode s egment may b e g iven na me C ODE, s egment may b e giv en name DATA etc. statement A SSUME CS: C ODE d irects a ssembler m achine c odes are a vailable i n a s egment n amed C ODE, henc e C S reg ister i s t o b e l oaded addres s ( segment) a llotted b y ope rating sy stem l abel C ODE, w hile l oading. S imilarly, A SSUME D S: D ATA i ndicates t o th e a ssembler i tems r elated t o program, are available in a logical segment named DATA, and DS registe r i s t o b e in itialized b y s egment a ddress v alue de cided by opera ting sy stem for data s egment, w hile loading. I t n c onsiders s egment D ATA a s a d efault s egment e ach memor y operation, r elated t o s egment C ODE a s a sou rce segment m achine c odes of p r ogram. A SSUME s tatement i s a m ust a t th e starting o f eac h assembly languag e program, E ND: E ND of Program E ND d irective ma rks e nd o f a n assembly languag e program. W hen a ssembler c omes a cross this E ND d irecti ve, i t ignor es source line s a vailable l ater o n. Hen c e, i t s hould b e e nsured E ND stateme nt s hould b e l ast s tatement i n f ile s hould n ot a ppear i n bet w een. N o u seful prog ram sta tement s hould l ie in file, after END statemen t E NDP: E ND o f P rocedure. I n assembly language prog ramming, sub routines c alled p rocedures. Thus, p rocedures may b e in dependent prog ram mo dules w hich r eturn p articular r esults o r value s t o c alling program s. E NDP d irective is u sed t o i ndicate e nd o f a procedu r e. A procedure i s usually a ssigned a n a me, i. e. label. T o m ark e nd of a p articular p rocedure, n ame o f procedur e, i.e. l abel m ay appe ar a s a prefix d irective E NDP. s tatements, a ppearing i n s ame m odule b ut after ENDP di r ective, are neglected from that procedure. structure given below explains use of ENDP. PROC EDURE STAR... 21

26 S TAR E NDP E NDS: E ND of Segment T his d irective marks e nd o f a logic al segm e nt. l ogical s egments assig ned name s u sing A SSUME directiv e. n ames appe ar E NDS directive a s prefixe s t o mark end of t hose particular segm e nts. Whateve r c ontents o f segm e nts, y s hould a ppear i n program b efore E NDS. Any s tatement appearing afte r E NDS w ill b e neglecte d s e gment. s tructure show n below explains fact more clearly. DAT A SEGMENT... DATA ENDS ASSUME CS: CO DE, DS :DATA CODE SEGMEN T.... CODE ENDS E ND a bove s tructure r epresents a s imple p rogram c ontaining t wo segments n amed D ATA CODE. related t o p rogram m ust l ie b etween DATA S EGMENT D ATA E NDS s tatements. Similarl y, a ll executab le i nstructions m ust l ie b etween CO DE SEGMENT and CODE ENDS stateme n ts. E VEN: A lign o n E ven M emory A ddress a ssembler, w hile s tarting a ssembling p rocedure o f any p rogram, i nitializes a l ocation c ounter goe s o n u pdating i t, a s a ssembly p roc eeds. I t g oes o n a ssigning a vailable a ddresses, i. e. c ontents o f l ocation c ounter, sequentially t o progra m v ariables, constants mo dules a s pe r ir r equirements, in sequ ence in w hich y app ear in pro g ram. Th e EVEN direc tive u pdates l ocation coun ter t o next e ven add ress i f c urrent locati on c ounter contents n ot e ven, assigns following r outine o r variable o r c onstant to addr e ss. structure given below explains directive. E VEN P ROCEDURE R OOT... ROOT ENDP above s tructure show s a proc edure R OOT th at i s t o b e aligned a t an e ven a ddress. a ssembler w ill s tart asse mbling ma in prog ram c alling R OOT. W hen a ssembler c omes a cross d irective E VEN, i t c hecks c ontents o f l ocation c ounter. I f i t i s o dd, i t i s u pdated t o next even v alue n ROO T p rocedure i s assigned t o add r ess, i.e. u pdated c ontents o f l ocation c ounter. I f th e c ontent of loc ation c ounter i s already e ven, n ROOT procedure will be assigned with same addre s s. E QU: Equa te d irective E QU i s u sed t o a ssign a l abel a v alue o r a s y mbol. u se o f t his dire ctive i s j ust t o r educe recurr ence of th e numeric al va lues or c onstants i n a p rogram c ode. r ecurring v alue i s assigne d a l abel, labe l i s u sed i n plac e of n umerical v alue, t hroughout pro g ram. W hile a ssembling, w henever asse mbler c omes a cross l abel, i t s ubstitutes n umerical v alue labe l f inds o ut th e e quivalent c ode. Usin g th e E QU d irective, eve n an i nstruction m nemonic c an b e assigne d a l abel, l abel can n be u sed i n prog ram i n plac e of t h at m nemonic. S uppose, a n umerical c onstant a ppears ' in a prog ram t en t imes. I f th at consta nt i s t o b e chang ed a t a late r t ime, one will h ave t o ma ke a ll se te n correctio ns. This m ay le ad t o huma n e rrors, because i t 22

27 i s p ossible a h uman p rogrammer may m iss o ne o f t hose corr e ctions. T his w ill r esult i n g eneration of wrong cod e s. If E QU directive i s u sed t o assign val ue a l abel th at can be used in place of each recurrence of that constant, only one change i n E QU s tatement w ill g ive c orrect m odified c ode. e xamples g iven b elow sh ow sy n tax. Exam ple LABEL E QU 0500H ADDITION EQU A DD first s tatement a ssigns consta nt 500H la bel LABEL, while sec ond statement assigns anor label ADDITI ON with mnemonic A DD. EXTRN: External and PUBLIC: Public directive EXTRN informs th e a ssembler n ames, procedur es l abels decld afte r t his d irective have already be en d efined i n s ome o r assembly langua ge m odules. W hile i n o r m odule, where nam e s, p rocedures l abels actually a ppear, y m ust b e d eclared p ublic, u sing P UBLIC directive. I f o ne w ants t o c all a p rocedure FACTORI AL a ppearing in MODUL E 1 M ODULE 2 ; i n M ODULE1, i t m ust b e decld PUB LIC u sing s tatement P UBLIC F ACTORIAL i n m odule 2, i t m ust b e d eclared ext ernal using d eclaration E XTRN FACTORIAL. statem ent o f d eclaration EXTR N m ust b e accompanied by S EGMENT E NDS d irectives of MODUL E 1, befo re i t i s c alled i n MOBUL E 2. T hus MODULE 1 and MODULE 2 must have following declara t ions. MODULEl SEGM ENT PUBLIC FACTORIAL F AR MODULEl ENDS MODULE2 SEGM ENT EXTRN FACTORIAL F AR MODUL E2 END S G ROUP: G roup Re lated segm ent d irective i s u sed t o for m logica l g roups o f s egments s imilar pur pose or t y pe. This directi ve i s u sed t o i nform a ssembler t o m a l ogical g roup o f fo llowing s egment nam e s. a ssembler pa sses information t o l inker/loader t o m c ode s uch grou p d eclared s egments or o perands m ust l ie in a 64Kbyte m emory s egment. T hus a ll s uch s egments l abels ca n b e a ddressed using same segment base. PROGRAM GROUP CODE, DATA, STACK a bove stateme nt d irects l oader/linker t o p repare a n EXE file such CO DE, D ATA and STACK segment must lie within a 64kbyte memory seg m ent that is named as PROGRAM. N ow, ASSUME s tatement, o ne c an use l abel P ROGRAM r ar t han C O DE, DATA and STAC K a s shown. A SSUME CS: P ROGRAM, DS: PROGRAM, SS: PROGRA M. L ABEL: Labe l L abel d irective i s u sed t o a ssign a n ame t o c urrent c ontent o f l ocation c ounter. A t s tart of assembly p rocess, a ssembler i nitializes a l ocation c ounter t o k eep t rack o f m emory l ocations assigne d t o p rogram. A s p rogram assembly p roceeds, c ontents o f l ocation c ounter u pdated. D uring a ssembly p rocess, w henever a ssembler c omes a cross L ABEL d irective, i t a ssigns declare d l abel c urrent conte nts o f l ocation count e r. type o f labe l must b e speci f ied, i. e. w her i t i s a N EAR o r a F AR l abel, B YTE o r W ORD l abel, e tc. A L ABEL d irective may b e u sed t o m ake a F AR jum p a s s hown b elow. A F AR j ump c annot b e m ade a t a normal labe l a c olon. labe l CONTI NUE c an be used a F AR j ump, i f p rogram contain s th e following stateme n t. CONTI NUE LABEL FA R L ABEL directive c an b e u sed t o ref er t o seg ment along typ e, by te or w ord a s shown. DATA SEGMENT 23

28 DATAS D B 50H D UP (?) DATA-L AST LABEL B YTE FAR DATA ENDS A fter r eserving 50H loc ations for D ATAS, next l ocation w ill be assig ned a labe l DATALAST and its type will be by t e and far. L ENGTH: B yte Length of a L abel T his d irective i s n ot a vailable i n MAS M. T his i s used to refer to length of a data array or a string. MOV CX, LE NGTH ARRAY T his statement, w hen ass e mbled, w ill s ubstitute leng th o f array ARR AY i n byt e s, i n instruc t ion. L OCAL l abels, v ariables, c onstants o r proce dures decld LOCAL i n a m odule are to be used onl y by tha t m odule. At a l ater t ime, s ome o r m odule m ay d eclare a particular t ype L OCAL, w hich i s previously decld L OCAL by a nor modu le o r m odules. T hus s ame l abel m ay s erve differe nt p urposes d ifferent m odules o f a p rogram. W ith a s ingle declaration statement, a number of variables can be declared loca l, a s shown. LOCAL a, b, DATA, ARRAY, ROUTIN E N AME: L ogical N ame of a Module N AME d irective i s u sed t o a ssign a n ame t o a n assembly l anguage p rogram m odule. m odule m ay n ow b e r eferred t o by i ts declare d name. n ames, i f sele cted t o b e s uggestive, m ay p oint o ut f unctions o f d ifferent modules and hence may help in documenta t ion. O FFSET: O ffset of a Labe l W hen a ssembler c omes a cross OF FSET o perator a long a l abel, i t f irst computes 16-b it d isplacement ( also calle d a s of fset interchangeabl y ) o f p articular l abel, r eplaces string ' OFFSET LABE L ' by comp uted d isplacement. T his o perator i s used array s, strin g s, labe ls procedur es t o decide ir offsets in ir default segmen ts. s egment may a lso b e d ecided by a nor operator o f s imilar typ e, viz., S EG. I ts m ost c ommon u se i s i n c ase of th e i ndirect, index e d, based indexe d o r o r addres sing technique s o f s imilar t y pes, u sed t o r efer to memory indirectly. e xamples o f t his o perator are a s follow s : Example: CODE SEGMENT MOV SI, OFFSET LIS T CODE ENDS DATA SEGMENT LIST DB 10H DATA ENDS O RG: O rigin O RG d irective d irects asse mbler t o s tart m emory a llotment for pa rticular segment, block or code from declared address in OR G statement w hile s tarting assembly p rocess a m odule, a ssembler initialize s a location c ounter t o k eep t rack o f a llotted a ddresses m odule. I f O RG s tatement i s n ot w ritten i n p rogram, l ocation counte r i s initialize d t o I f a n ORG 200H s tatement i s p resent a t th e s tarting o f c ode seg ment o f m odule, th en c ode w ill s tart 200H a ddress in c ode s egment) I n o r w ords, l ocation count er w ill g et i nitialized t o a ddress 0200H i nstead o f 0000H. T hus, c ode differe nt m odules seg ments ca n b e locate d i n a vailable memory a s requ ired by pro g rammer. O RG d irective can e ven b e u sed data segments similarly. P ROC: P rocedure P ROC d irective m arks s tart o f a n amed proc edure i n stateme n t. A lso, ty pes N EAR o r F AR s pecify ty pe o f procedure, i. e w her i t is t o be called by main program located within 64K of phy sical m emory or not. For example, s tatement RESULT P ROC N EAR marks s tart o f a r outine RESUL T, w hich i s t o be ca lled by a program located in 24

29 S ame s egment of memory. F AR d irective is u sed procedures to be called by programs located in different segments of memory. example statements are as follows: Exam ple RESULT PROC NEAR ROUTI NE PROC FAR P TR: P ointer pointe r o perator i s u sed t o d eclare type o f a la bel, v ariable o r m emory o perand. operator P TR i s prefixe d by e ir BYTE or WOR D. I f prefix i s B YTE, n particula r lab e l, v ariable or m emory op erand i s treated a s a n 8-b it quantit y, w hile i f WO RD i s prefix, n i t i s t reated as a 16- bi t quantity. In oth er w ords, PT R o perator i s u sed t o s pecify da ta ty pe -by te or w ord. exa mples o f th e P TR opera tor as follow s : Example: M OV A L, B YTE P TR [SI]; M oves content o f memory l ocation addresse d by SI (8- b it) t o AL INC BYTE PTR [BX]; Increments byt e contents of memory location addressed by B X M OV B X, W ORD P TR [ 2000H]; M oves 16-b it c ontent o f memory loca tion 2000H t o B X, i. e. [ 2000H] to BL [2001 H] t o BH I NC W ORD P TR [ 3000H] - I ncrements word c ontents o f memory locatio n 3000H c onsidering c ontents o f 3000H ( lower byt e ) an d 3001 H ( hig her byt e ) a s a 16-b it n umber I n c ase o f JM P i nstructions, P TR o perator i s u sed t o s pecify ty pe of j ump, i.e. near o r far, as explained in example s given below. JMP WORD PTR [BX] -N EAR Jump JMP WORD PTR [BX] -F AR Jump P UBLIC As already dis c ussed, PUBLIC d irective i s use d along E XTRN directive. This i nforms a ssembler l abels, vari a bles, c onstants, o r procedure s d eclared P UBLIC may b e a ccessed by o r assembly m odules t o m ir c odes, b ut wh ile u sing PUBL IC decld l abels, va r iables, con stants o r procedur es u ser m ust decla re m ext ernals u sing E XTRN d irective. O n o r h and, ty pes d eclared E XTRN i n a m odule o f p rogram, may b e decld P UBLIC i n a t l east anyone o f o r modules of same progra m. S EG: Segm ent of a Labe l S EG opera tor is u sed t o decide segmen t address o f l abel, v a riable, or procedure s ubstitutes th e s egment ba se address i n place o f SE G label. example given below explain use of SEG operator. Exam ple M OV AX, SEG ARRAY; This statement moves seg ment addres s M OV DS, AX; of ARRAY in which it is appearing, to register AX and n to DS. S EGMENT: L ogical Segm ent S EGMENT d irective m arks s tarting o f a l ogical s egment. s tarted s egment i s a lso assigned a n ame, i.e. l abel, by t his s tatement. S EGMENT E NDS d irective m ust b racket e ach log ical segme nt o f a pro g ram. I n s ome c ases, segme nt may b e assigned a type l ike P UBLIC ( i.e. c an b e u sed by o r modules o f p rogram w hile l inking) o r G LOBAL ( can b e a ccessed by any or m odules). p rogram structure given below explains use of SEGMENT directive. E XE. CODE SEGMENT GLOBAL; Start of segment named EXE.CODE, that can be accessed by any o r module. E XE. CODE ENDS; END of EXE.CODE logical segme n t. SHOR T S HORT o perator i ndicates t o a ssembler only o ne byte i s r equired t o c ode displacement a j ump ( i.e. d isplacement i s in -128 t o by tes address of by t e next to jump opcode). This method of specifying jump address saves memory. O rwise, a ssembler may reserve t wo bytes for displacem e nt. sy ntax of statement is as given below. JM P SHORT LA BEL 25

30 TYP E TYPE o perator d irects ass embler to d ecide da ta ty pe of s pecified l abel replaces 'TY PE label' by de cided typ e. F or wor d type va riable, th e data type is 2, d ouble w ord typ e, i t i s 4, by te t y pe, i t i s 1. S uppose, STRI NG is a word array. instruction MOV AX, TYPE STRING moves value 0002H in A X. G LOBAL l abels, v ariables, c onstants o r procedures declared GLOBAL may b e u sed by or modules o f pro g ram. O nce a v ariable i s declare d GLOBA L, i t c an b e u sed by a ny m odule i n progr a m. f ollowing s tatement d eclares proc edure ROUTI NE a s a global labe l. ROUTINE PROC GLO BAL 1. 5 ASSEMBLY LANGUAG E PROGR AMMING ALP for addition of two 8-bit numb ers ALP for Subtraction of two 8-b it DATA SEGMENT numbers V AR1 DB 85H DATA SEGMENT V AR2 DB 32H VAR1 DB 53H RES DB? VAR2 DB 2 AH DATA ENDS RES DB? A SSUME CS:CODE, D S: DAT A D ATA E NDS CODE SEGMENT ASSUME CS:CODE, DS: DATA START: MOV AX, DATA CODE SEGM ENT MOV DS, AX START: MO V AX, DAT A MOV AL, VAR1 MOV D S, AX MOV BL, VAR 2 MOV AL, VAR 1 ADD AL, BL MOV BL, VAR 2 M OV RES, AL SUB AL, BL MOV AH, 4CH M OV R ES,AL IN T 21H MOV AH, 4CH CODE ENDS IN T 21H E ND S TART CODE ENDS END STAR T 26

31 ALP for Multiplication of two 8-b it numb ers DATA SEGMENT VAR1 DB 0 EDH VAR2 DB 99H R ES D W? D ATA E NDS ASSUME CS: CODE, DS: DAT A CODE S EGMENT START: MO V AX, DA TA M OV D S, A X MOV AL, VAR1 MOV BL, VAR 2 MUL B L MOV RES, AX MOV AH, 4CH IN T 21H CODE ENDS END STAR T ALP for division of 16-bit number with 8-bit numb er DATA SEGMENT VAR 1 DW 6827H VAR2 DB 0FE H QU O DB? R EM D B? D ATA E NDS ASSUME CS:CODE, DS: DATA CODE SEGMENT START: MO V AX, DA TA M OV D S, A X MOV A X, VAR 1 DIV VA R2 MOV QUO, AL M OV R EM, A H MOV AH, 4CH IN T 21H CODE ENDS END STAR T ALP for Subtraction of two 16-bit numb ers DATA SEGMENT VAR 1 DW 8560H VAR 2 DW 3297H RES DW? D ATA E NDS A SSUME CS: CODE, DS: DAT A CODE SEGMENT START: MO V AX, DA TA M OV D S, A X MOV A X, VAR 1 CLC SUB A X, VAR2 MOV RES, AX 27

32 MOV AH, 4CH IN T 21H CODE ENDS END STAR T 1.6 Modular programmi ng ALP for Multiplication of two 32-b it numb ers DATA SEGMENT MULD DW 0FFFFH, 0FFFFH MULR DW 0FFFFH, 0FFFFH R ES DW 6 DUP (0) D ATA E NDS ASSUME CS: CODE, DS : DATA CODE SEGMENT START: MO V AX, DA TA M OV D S, A X MOV AX, MULD MUL MULR MOV RES, AX M OV R ES+2, D X MOV AX, MULD+2 MUL MULR AD D R ES+ 2, AX ADC RES+ 4, DX MOV AX, MULD MUL MULR + 2 AD D R ES+ 2, AX ADC RES+ 4, DX J NC K INC RES+6 K: MOV AX, MULD+2 MUL MULR + 2 AD D R ES+ 4, AX ADC RES+ 6, DX MOV AH, 4CH IN T 21H CODE ENDS END STAR T ALP to Sort a set of unsigned integer numb ers in a n ding/ d e nding o rder using Bubble sor t algorithm. DATA SEGMENT A DW 0005H, 0ABCDH, 5678H, 1234H, 0EFCDH, 45EFH D ATA E NDS ASSUME CS: CODE, DS : DATA CODE SEGMENT START: MO V AX, DA TA M OV D S, A X MOV SI, 0000H MOV BX, A[SI] DEC BX X2: MOV CX, BX MOV SI, 02H 28

33 X1: MOV AX, A[SI] IN C SI IN C SI CMP AX, A[SI] XCHG AX, A[SI] MOV A[SI-2 ], AX X3: LO OP X1 DEC BX JNZ X2 MOV AH, 4CH IN T 21H CODE ENDS END STAR T 1.7 Linking And Relocati on DOS linking program links different object modules of a source program and function library routines to generate an integrated executable code of source program. main input to linker is.obj file that contains object m odules of sourc e program s. Or supporting information may be o btained from files generated by MAS M. linker program is invoked using following o ptions. C> LIN K o r C> LINK MS. OBJ. OBJ ext ension i s a m ust a f ile t o be a ccepted by LINK as a va lid o bject file. first object may generate a display asking for object file, list file and libraries as i nputs a n exp ected n ame o f.ex E f ile t o b e genera t ed. ou tput o f th e l ink program is an executable file with entered filename and. EX E exten sion. T his exe cutable f ilename can furr be entered at DOS pr ompt to execute file. I n a dvanced v ersion o f M ASM, c omplete procedure o f assemb ling l inking i s c ombined u nder a sing le m enu invoka ble c ompile fun c tion. r ecent v ersions o f M ASM h ave m uch m ore s ophisticated user-friendly f acilities o ptions. A l inker l inks m achine codes o r required a ssembled c odes. L inking i s necessary because of number of codes to be linked for final binary file. l inked f ile i n b inary r un o n a c omputer i s commonly k nown a s exe cutable f ile o r s imply. ex e. f ile. A fter l inking, re ha s t o b e re-a llocation o f s equences o f placing codes before actually placement of codes in memory. l oader prog ram pe rforms task o f r eallocating co des a fter fin ding th e p hysical R AM a ddresses a vailable a t a g iven i nstant. D OS l inking p rogram l inks d ifferent o bject m odules o f a s ource p rogram and f unction l ibrary routine s t o g enerate a n i ntegrated e xecutable c ode o f s ource pro g ram. mai n i nput t o l inker i s. OBJ f ile c ontains o bject m odules of source progr a ms. O r suppor ting informatio n may be obtained from files generated by MASM. linked file in binary for r un o n a c omputer i s commonly k nown a s executab le f ile o r simply.ex e. f ile. A fter l inking, re h as t o b e re-a llocation of sequences o f plac ing c odes befor e actually p lacement of codes in memory. l oader prog ram pe rforms task o f r eallocating c odes a fter fin ding th e physic al R AM addresses a vailable a t a g iven i nstant. l oader i s a p art o f o perating s ystem p laces code s i nto th e m emory a fter r eading.ex e f ile. This s tep i s necessary b ecause a vailable m emory a ddresses may n ot s tart 0 x0000, b inary code s h ave t o b e l oaded a t d ifferent addresse s during r un. l oader f inds appropriate sta rt addre s s. I n a c omputer, th e loader i s u sed i t l oads i nto a sec tion o f RA M progra m 29

34 that is ready to r un. A progra m c alled l ocator reall ocates l inked f ile and crea tes a f ile for permanent location of c odes in a standard forma t Segment comb ination I n a ddition t o l inker c ommands, a ssembler p rovides a m eans o f regulating way segmen ts in different object modules are organized by linke r. S egments s ame nam e j oined tog er by using m odifiers a ttached t o SEGMENT direct ives. SEGMENT directive may h ave form Segment name SEGMENT Combination-typ e w here combine-ty pe i ndicates h ow s egment i s t o b e l ocated in l oad m odule. S egments h ave d ifferent n ames c annot b e com bined s egments wit h s ame n ame but no combine-type will cause a linker error. possible combine-type s : P UBLIC I f s egments i n d ifferent m odules h ave same n ame and combine- ty pe P UBLIC, n y concatena ted i nto a s ingle eleme nt i n l oad m odule. Th e ordering in concatenation is specified by linker comma n d. C OMMON I f segment s i n d ifferent object m odules h ave s ame n ame combine-ty pe i s C OMMON, n y ov erlaid s o y hav e s ame starting addres s. length of common segment is that of longest segment being o verlaid. S TACK I f s egments i n di fferent o bject modu les h ave s ame n ame combine typ e S TACK, n y becom e o ne s egment whose l ength i s s um o f leng ths o f th e individually specified segments. In effect, y are combined to form one large stack A T AT combine-t ype is followed by a n expression that e valuates t o a c onstant w hich i s t o b e s egment a ddress. I t a llows u ser t o specify exa ct l ocation o f segment in memory. M EMORY T his combine-t ype c auses s egment t o b e p laced a t l ast o f l oad module. I f m ore than one s egment MEM ORY combine-ty pe i s b eing l inked, only f irst o ne w ill b e t reated a s h aving MEM ORY c ombine t y pe; o rs w ill b e overlaid as if y had COMMON combine-ty p e. 30

35 Fi g. 1.9 Segment combinations resulting from PU BLIC and Common Comb ination types Fig Formation of a stack from two segments Access to External Identifiers If a n i dentifier i s define d i n a n o bject m odule, n i t is s aid t o b e a l ocal ( o r i nternal) i dentifier re lative t o m odule. I f i t i s n ot d efined i n module b ut i s d efined i n o ne o f o r m odules b eing l inked, n it i s r eferred t o a s a n ex ternal ( or g lobal) i dentifier r elative t o m odule. I n o rder t o pe rmit o r o bject m odules t o refer ence s ome o f identifiers i n a give n m odule, g iven mod ule m ust i nclude a l ist o f i dentifiers t o 31

36 ROC ONTROLLER w hich i t w ill a llow a ccess. refo r e, e ach m odule i n multi-m odule p rograms m ay c ontain t wo l ists, o ne containing ext ernal ide ntifiers th at can b e referr ed t o by o r m odules. Two lists are implemented by EXTRN and PUBLIC directives, whi ch have forms: w here identifier s are var iables labe ls being declare d o r a s bein g available to o r module s. a ssembler m ust kno w ty pe o f a ll ext ernal i dentifiers be fore i t c an genera te p roper m achine c ode, a type s pecifier m ust b e a ssociated e ach i dentifier i n a n E XTRN statemen t. For a variable type may be BYTE, WORD, or DWORD and for a label it may be NEAR or FA R. O ne o f primary tasks o f l inker i s t o verify every identifier appearing i n a n EXTRN statement is m atched by o ne i n a P UBLIC s tatement. I f t his i s n ot c ase, n re w ill b e a n u ndefined r eference a l inker e rror w ill o ccur. offsets lo cal i dentifier will be inserted by assembler, but offsets for external identifiers and a ll s egment addr esses m ust b e i nserted b y l inking p rocess. o ffsets a ssociated a ll e xternal r eferences c an b e a ssigned o nce a ll o f o bject m odules h ave b een f ound ir e xternal s ymbol t ables h ave b een ex a mined. a ssignment o f s egment addr esses i s c alled r elocation i s d one a fter l inking pr ocess h as dete rmined exactly where e ach segment is to be put in memory. 1.8 Stack s stack is a block of memory that may be used for temporarily storing contents o f r egisters i nside C PU. I t i s a top-d own s tructure w hose eleme nts a ccessed u sing stack pointer (S P ) which gets decremente d by two a s we s tore a data word into s tack g ets increme nted b y t wo a s w e r etrieve a w ord s tack b ack t o CPU registe r. p rocess o f s toring i n s tack i s c alled pushing i nto s tack reverse proc ess of transferring back from stack t o C PU register i s known a s popping off stack. stack is essentiall y Last-In-First- Out ( LI FO) data segment. T his m eans w hich i s p ushed i nto s tack l ast w ill b e o n t op o f s tack w ill b e popped off stac k fir s t. s tack p ointer i s a 16-b it r egister contains o ffset a ddress o f m emory l ocation i n s tack s egment. s tack s egment, l ike any o r s egment, m ay h ave a memory b lock of a maxi mum o f 64 Kbyte s locati o ns, t hus may o verlap any o r segmen ts. S tack Segment register ( SS) contains base addr ess of s tack seg ment i n memory. S tack S egment re gister ( SS) S tack p ointer r egister ( SP) t oger a ddress stack- top as explained below: I f s tack t op p oints t o a me mory l ocation 52050H, i t m eans l ocation 52050H i s already o ccupied previously pushed d a ta. next 16 b it push o peration w ill d ecrement s tack p ointer by t wo, s o i t w ill p oint t o n ew stack-t op 5204EH decremented contents o f S P will b e 204EH. T his l ocation w ill n ow be occupie d by th e recently pushed data. T hus a s elected v alue o f S S, m aximum v alue o f S P=FFFFH s egment c an h ave maxi mum o f 64K l ocations. I f S P s tarts a n i nitial v alue o f F FFFH, i t w ill b e d ecremented by t wo whenever a 16-b it is p ushed o nto s tack. A fter s uccessive p ush o perations, w hen s tack p ointer c ontains 0000H, any a ttempt t o f urr p ush data to stack will result in stack overf l ow. 32

37 A fter a proc edure i s c alled u sing CAL L instr u ction, I P i s incremen ted t o n ext i nstruction. n c ontents o f I P, C S and f lag r egister p ushed automatically t o s tack. c ontrol is n transf erred to th e sp ecified addre ss i n C ALL instruc tion i. e. starting address of procedur e. n procedure is execute d. Fig Stack top addres s calculation 1.9 Procedures A p rocedure i s a s et o f c ode c an b e branched t o r eturned i n s uch a w ay c ode i s a s i f i t w ere i nserted a t p oint from w hich i t i s b ranched t o. branc h t o p rocedure i s r eferred t o a s call, c orresponding b ranch back i s k nown a s th e ret urn. r eturn i s al ways made t o i nstruction immediately fol lowing ca ll regardless of where call is locate d Calls, Returns, and Pr ocedure Definitions CALL instruction not only branches to indicated address, but also pushes r eturn a ddress o nto s tack. R ET i nstruction s imply p ops return addr ess sta ck. r egisters u sed b y p rocedure n eed t o b e s tored b efore ir c ontents c hanged, n r estored j ust b efore ir cont ents chan g ed, th en r estored j ust before procedure is excite d. A CALL may b e d irect or indirect i ntrasegment o r intersegm e nt. I f C ALL i s i ntersegment, r eturn m ust b e i ntersegment. I ntersegment c all m ust pu sh b oth ( I P) ( CS) o nto s tack. r eturn m ust correspondingly p op two w ords from s tack. I n c ase o f i ntrasegment c all, only c ontents o f I P w ill b e s aved retrieve d w hen c all return instruc tions are use d. P rocedures u sed i n s ource c ode by placin g a s tatement o f m a t beginning of proced ure Procedure name PROC Attrib ute and by terminating procedure with a statemen t Procedur e name E NDP a ttribute c an be u sed w ill b e e ir NEA R o r F AR. I f attribu te i s N EAR, R ET i nstruction w ill o nly po p a word i nto I P re g ister, but i f i t is FAR, i t w ill a lso pop a word into CS registe r. A procedure may b e in: 1. same code segment as statement that ca l ls it. 2. A code segment that is different from one containing statement that calls it, but in same source module as calling stateme n t. 3. A different source module and segment from calling stateme n t. I n f irst cas e, attrib ute c ould b e N EAR pro vided a ll c alls are in same c ode s egment a s p rocedure. F or l atter t wo c ases a ttribute m ust b e F AR. I f 33

38 p rocedure i s g iven a F AR attrib u te, n a ll c alls t o i t m ust b e intersegment c alls e ven i f c all is from s ame code segment. For t hird c ase, procedur e n ame m ust b e d eclared in EXTRN and PUBLIC stateme n ts Saving and Restoring Registers W hen b oth c alling pr ogram procedur e s hare same s et o f r egisters, i t i s necessary t o s ave r egisters w hen entering a procedur e, r estore m before returning t o calling progr am. M SK PROC NEAR PUSH AX PUSH BX P USH C X P OP CX POP BX P OP A X R ET MSK ENDP Procedure Communica tion re t wo g eneral ty pes o f p rocedures, t hose o perate o n s ame s et o f t hose m ay p rocess a d ifferent s et o f eac h t ime y c alled. If a p rocedure i s i n s ame sour ce m odule a s c alling pro g ram, th en procedur e c an refe r t o varia bles directly. W hen procedure i s in a separa te s ource m odule i t can s till refe r to th e source module directly provided that calling program contains direct ive PUBLIC ARY, COUNT, SUM E XTRN ARY: WORD, COUNT: WORD, SUM: W ORD Recursive Procedures W hen a p rocedure i s c alled in a nor procedu re i t c alled recur sive p rocedure. T o m ake s ure proc edure d oes n ot modify i tself, ea ch ca ll m ust s tore i ts s et o f param e ters, r egisters, and all temporary results in a different place in memory Eg. Recursive procedure to compute fact orial 1.10 Macr os Disadvantages of Procedure 1. L inkage associated with m. 2. I t s ometimes r equires more c ode t o p rogram l inkage t han i s needed t o p erform ta s k. I f t his i s c ase, a p rocedure m ay n ot s ave m emory e xecution t ime i s considerably i ncreased. 3. M acros i s neede d for p roviding progra mming ease o f a procedure w hile a voiding linkage. Ma cro i s a seg ment o f c ode needs t o b e w ritten only once b ut whos e b asic s tructure c an b e cause d t o b e repe ated se veral t imes in a s ource mod ule by placing a single statement at point of each referenc e. A m acro i s u nlike a proc edure i n that machin e i nstructions are repeat ed eac h t ime m acro i s r eferenced. refore, n o memory i s s aved, b ut prog ramming t ime is conserved (no linkage is required) and some degree of modularity is achieve d. code i s t o b e r epeated i s c alled prototy pe c ode. p rototype c ode along s tatements for referencing and terminating is called macro de fi nition. O nce a macro i s d efined, i t can b e inserted a t vario us p oints i n progra m by u sing m acro c alls. Wh en a m acro ca ll i s encountered by a ssembler, a ssembler repla ces call with ma cro code. I nsertion o f m acro c ode by asse mbler fo r a m acro c all i s r eferred t o a s a macro ex p ansion. I n orde r to a llow prototype code t o be used i n a variety o f s ituations, m acro def inition prototy pe cod e c an u se dummy p arameters w hich can be replaced by actual parameters 34

39 w hen macro is expanded. During a macro ex p ansion, f irst a ctual pa rameter repla ces f irst dummy p arameter i n prototype code, s econd a ctual para meter r eplaces second dummy parameter, a n d so on. A macro call has fo rm % Macro n ame ( Actua l p arameter l ist) a ctual para meters be ing separated by comma s. % MULTI P LY (CX, VAR, XYZ[B X ] Local Label s C onsider a macr o c alled ABSOL which m akes use o f lab e ls. T his macro i s u sed t o replac e operand by its absolute value. %*DEFI N E (ABSOL(OPER)) ( CMP % O PER, 0 JG E NE XT N EG % OPER % NEXT : N O P) W hen m acro ABSOL i s c alled th e f irst t ime, l abel N EXT wi ll a ppear i n p rogram, refore it b ecomes d efined. Any s ubsequent c all w ill cau se N EXT t o b e redefine d. T his w ill r esult i n a n e rror during assembly p rocess because N EXT has be en a ssociated m ore t han o ne l ocatio n. O ne s olution t o t his p roblem w ould b e t o h ave N EXT r eplaced by a dummy para meter for l abel. T his w ould r equire progr ammer t o keep track of dummy parameters use d. O ne s olution t o t his p roblem i s u se o f L ocal L abels. L ocal l abels s pecial l abels w ill h ave suffixe s g et i ncremented e ach t ime m acros c a lled. s e suffixe s t wo d igit n umbers that g ets increment ed by o ne starting z ero. L abels c an b e d eclared a s l ocal l abel b y a ttaching a p refix Loc a l. L ocal L ist o f Local labe ls a t e nd of first statement in ma c ro definition Interrupts And Interrupt Routines Interrupt and its Need: microproc essors a llow n ormal prog ram execut ion t o b e i nterrupted i n o rder t o carry o ut a specific task/work. processor can be interrupted in following ways i ) b y an external signal generated by a peripheral, i i) by an internal signal generated b y a special instruction in program, i ii) by a n i nternal signa l generate d d ue t o a n exc eptional c ondition w hich occurs w hile e xecuting a n i nstruction. ( For e xample, i n 8086 p rocessor, d ivide by z ero i s a n exc eptional c ondition wh ich initiat es type 0 i nterrupt suc h a n interru pt i s a lso called execu tion). p rocess o f interrupti ng n ormal program e xecution t o carry o ut a s pecific t ask/work i s referre d t o a s i nterrupt. i nterrupt i s i nitiated b y a signa l gene rated by a n external device or by a signal generated internal to processor. W hen a m icroprocessor re ceives a n i nterrupt sig nal i t s tops exe cuting c urrent n ormal p rogram, save status (or content) of va rious r egisters ( I P, C S f lag re gisters i n c ase o f 8086) i n s tack n processor exe cutes a s ubroutine/procedure in o rder t o per form s pecific t ask/work r equested by i nterrupt. subrout ine/procedure i s exe cuted i n r esponse t o a n interrup t i s a lso c alled Interrupt S ervice S ubroutine (IS R ). A t e nd o f I SR, s tored s tatus o f r egisters i n s tack i s r estored t o r espective r egisters, p rocessor r esumes n ormal p rogram execu tion p oint { instruction) w here i t w as interrupte d. external interrupts are used to implement interrupt driven data transfer scheme. i nterrupts g enerated by spe cial i nstructions c alled s oftware i nterrupts y u sed t o i mplement syste m s ervices/calls ( or mo nitor s ervices/calls). syste m/monitor s ervices p rocedures d eveloped by sy stem desig ner v arious o perations s tored i n 35

40 memory. u ser can c all se service s t hrough s oftware interrupt s. i nterrupts generated by exceptional conditions are used to implement error conditions in sy s tem Interrupt Driven Data Transfer Scheme interrupts are usef ul efficient transfe r b etween proc essor p e ripheral. W hen a p eripheral i s ready t ransfer, i t i nterrupts p rocessor by sending a n a ppropriate s ignal. Upon r eceiving a n i nterrupt s i gnal, p rocessor suspe nds th e cur rent p rogram ex e cution, s ave s tatus i n s tack exe cutes a n IS R to perform da ta transfer between peripheral and processor. A t e nd of I SR pro cessor s tatus i s restored s tack processo r r esume i ts n ormal p rogram exec u tion. T his t ype o f t ransfer sc heme i s called i nterrupt d riven data transfer scheme. t ransfer betwe en proce ssor perip heral devic es c an b e i mplemented e ir b y p olling t echnique o r by i nterrupt m ethod. I n p olling t echnique, processor h as t o periodically p oll o r che ck s tatus/readiness o f d evice c an p erform t ransfer o nly w hen de vice ' is read y. I n p olling techniq ue processor t ime i s w asted, beca use p rocessor h as t o s uspend i ts w ork c heck s tatus of d evice i n predefine d interva l s. If de vice i nterrupts th e proce ssor t o ini tiate a t ransfer whenever i t i s ready n p rocessor t ime i s effectively utilize d b ecause proce ssor nee d n ot s uspend i ts work and check status of device in predefined interva l s. F or a n e xample, c onsider t ransfer from a keyboar d t o p r ocessor. Normally a key board has to be checked by proc essor o nce i n every 10 m illiseconds a k ey p ress. refore o nce i n every 10 millisecond s proces sor h as t o s uspend i ts w ork n c heck key board a v alid key c ode. A ltern atively, key board c an i nterrupt p rocessor, whe never a key i s pressed a v alid k ey code i s generated. I n t his way processor need not waste its time to check keyboard once in every 10 milliseconds Classification of Interrupts In general interrupts can be classified in following three way s : 1. Hardware and software interru pts 2. Vectored and Non Vectored inte rru pt: 3. Maskable and Non Maskable inte rru pts. i nterrupts i nitiated b y e xternal h ardware by se nding a n appropriate sig nal t o i nterrupt p in o f p rocessor i s c alled h ardware i nterrupt p rocessor h as t wo i nterrupt p ins I NTR NM I. i nterrupts i nitiated by apply ing appr opriate s ignal t o se pins are called hardware interrupts of s oftware i nterrupts p rogram i nstructions. se i nstructions i nserted a t d esired l ocations i n a progr a m. W hile r unning a p r ogram, i f softw interru pt i nstruction i s e ncountered n p rocessor i nitiates an interrupt proc essor h as 256 types o f s oftware i nterrupts. s oftware i nterrupt i nstruction i s I NT n, w here n i s type n umber in range 0 to 255. W hen a n interrupt signa l i s accepted by processor, i f prog ram c ontrol a utomatically br anches t o a s pecific a ddress ( c alled v ector a d dress) n i nterrupt i s c alled v ectored i nterrupt. a utomatic b ranching t o v ector a ddress i s p redefined by m anufacturer o f process o rs. ( In se v ector addre sses i nterrupt serv ice s ubroutines ( ISR) s tored). I n non-v ectored i nterrupts th e i nterrupting d evice s hould supply a ddress o f I SR t o b e exe cuted in response to th e inter r upt. A ll 8086 i nterrupts v ectored i nterrupts. v ector addre ss a n 8086 i nterrupt i s o btained a v ector t able implemented in first 1kb memory s pace ( 00000h to 03FFFh). processor h as facility a ccepting o r rejecting hardwar e i nterrupts. P rogramming process or t o r eject a n i nterrupt i s referred t o a s masking o r d isabling p rogramming p rocessor t o accept a n interr upt i s referre d t o a s u nmasking or ena bling. In 36

41 8086 interrupt flag (IF) can be set to one to unm ask or enable a ll hardware inter rupts IF is cleared to zero to mask or disable a hardware interrupts except NMI. i nterrupts w hose r equest c an b e e ir accepte d o r r ejected by proc essor c alled maskable i nterrupts. i nterrupts w hose r equest has t o b e definitely acce pted (or c annot b e r ejected) b y p rocessor are c alled non-m askable i nterru pts. W henever a r equest i s m ade by non-maskable i nterrupt, processor h as t o definitely accept r equest s ervice i nterrupt by s uspending i ts c urrent p rogram exe cuting a n I SR. I n 8086 p rocessor a ll h ardware i nterrupts i nitiated throug h I NTR p in m askable b y clearing i nterrupt f lag ( IF). in terrupt i nitiated throug h NMI p in a ll s oftware i nterrupts non-maskable Sources of Interrupts in 8086 An interrupt in 8086 can come from one of following three source s. 1. On e s ource i s a n ext ernal s ignal a pplied to NMI or I NTR i nput p in o f proc e ssor. i nterrupts i nitiated b y apply ing a ppropriate s ignals t o se i nput p ins c alled hardwar e interr u pts. 2. A s econd sour ce of an inte rrupt i s exe cution o f inter rupt i nstruction " INT n ", where n i s t ype n umber. i nterrupts i nitiated b y " INT n " i nstructions c alled software inter r upts. 3. t hird sour ce o f a n i nterrupt i s some c ondition produc ed in th e 8086 by e xecution o f a n i nstruction. A n ex ample o f t his type o f i nterrupt i s d ivide by z ero i nterrupt. P rogram e xecution w ill b e automatically interrupt ed i f y ou a ttempt t o d ivide a n o perand by zero. S uch conditional interrupts are also known as exceptions Interrupts of microprocessor has 256 types o f interru p ts. I NTEL h as a ssigned a ty pe numbe r t o e ach i nterrupt. ty pe n umbers i n range o f 0 t o p rocessor ha s d ual f acility o f i nitiating se 256 i nterrupts. interrupts c an be i nitiated e ir by executing " INT n " i nstruction where n i s type n umber or interr upt can b e initi ated by sending an appropriate signa l to INTR input pin of proc es sor. F or i nterrupts i nitiated by s oftware instru c tion" INT n ", type n umber i s s pecified by instructio n i tself. Wh en i nterrupt i s i nitiated t hrough I NTR pi n, n p rocessor r uns a n i nterrupt a cknowledge cy cle t o g et ty pe n umber. ( i.e., i nterrupting d evice s hould s upply type n umber throug h D0- D7 l ines when pr ocessor reques ts for same through interrupt acknowledge cy c le). 37

42 Fi g Organization of Interrupt vector table in 8086 O nly first f ive types h ave exp licit d efinitions; o r ty pes may b e used by i nterrupt i nstructions o r e xternal i nterrupts. F rom f igure i t i s s een t ype a ssociated a division error interru pt i s 0. refore, i f a d ivision by 0 i s a ttempted, processor will p ush c urrent conte nts o f P SW, C S I P into s tack, f ill I P C S reg isters addre sses to 00003, and continue executing at address indicated by new contents of I P and CS. A d ivision e rror interrup t occurs any t ime a D IV o r IDI V i nstruction is exe cuted with quotient exceeding range, reg ardless of I F ( Interrupt flag ) and TF (Trap flag) status. type 1 i nterrupt i s single-s tep interrupt ( Trap i nterrupt) i s only i nterrupt c ontrolled by T F f l ag. I f T F f lag i s e nabled, n a n i nterrupt wi ll o ccur a t e nd o f n ext i nstruction w ill c ause a b ranch t o l ocation i ndicated by c ontents o f 00004H t o 00007H. sing le step i nterrupt i s used primarily for debugging w hich gives programmer a snapshot of his progr am after each instruction is executed 38

43 IRET is used to return from an interrupt service routine. It is similar to RET instruction except that it pops orig inal contents of PSW from stack as well as return addres s. IN T instruction has one of forms INT or INT Typ e I NT i nstruction i s al so o ften u sed a s a debugging aid i n case s where single stepping provides more detail than is wante d. By inse rting I NT i nstructions a t k ey p oints, c alled break p oints. W ithin a p rogram a p rogrammer c an u se a n i nterrupt r outine t o p rovide m essages o r i nformation a t se points. H ence 1 byte INT instructi on (Type 3 i nterrupt) i s a lso referred t o a s b reakpoint inter rupt. 39

44 I NTO i nstruction h as t ype 4 c auses a n int errupt i f only i f th e O F f lag i s s et t o 1. I t i s o ften placed j ust a fter a n a rithmetic i nstruction s o s pecial processing w ill b e d one if instruc tion causes a n overflo w. U nlike a divide-by-zer o f ault, a n over flow c ondition d oes n ot caus e an i nterrupt automaticall y ; i nterrupt mus t b e explicitly s pecified by I NTO in st ruction. r emaining i nterrupt types correspo nd t o i nterrupts instructions imbedded in interrupt program or to external interr u pts Strings and String Handlin g Instructions 8086 microprocessor i s equipped s pecial i nstructions to handle str ing operat io ns. By s tring w e m ean a se ries o f w ords o r b ytes r eside i n c onsecutive memory loca t ions. s tring i nstructions o f 8086 p ermit a p rogrammer t o i mplement o perations s uch a s t o m ove o ne b lock o f m emory t o a b lock el sewhere i n memor y. A s econd ty pe o f o peration i s easily p erformed i s t o s can a string e lements s tored in m emory l ooking a spe cific valu e. O r e xamples t o c ompare elements t wo strings toger in order to determine wher y are same or differe n t. Move St ri ng: MOV S B, M OV SW: A n e lement o f s tring specifie d b y s ource index ( SI) r egister r espect t o c urrent segme nt (D S ) r egister i s m oved t o l ocation specifie d by destinati on i ndex ( DI) r egister r espect t o curre nt ext ra s egment ( ES) r egister. m ove c an b e performed o n a by te (MO V S B) o r a wor d ( MOV S W) o f. A fter m ove i s c omplete, c ontents o f b oth SI & D I automatically incremented o r decrement ed by 1 a by te m ove by 2 a w ord m ove. Addre ss p ointers SI DI increme nt o r d ecrement depends on how direction flag DF is se t. Example: Block move program using move string instruct ion MOV AX, DATA SEG ADDR MOV D S, AX M OV E S, A X MOV SI, BLK 1 ADDR MOV DI, BLK 2 ADDR M OV C K, N CDF; DF=0 NEXT: MO V S B LOO P NE XT HLT L oad and s tore strings: (L OD SB/ L O D SW and STO SB/STO SW) L OD S B: L oads a by te a string in memory in to AL. a ddress i n SI is u sed r elative to DS to determine address of memory location of string eleme n t. ( AL ) [(DS) + (SI)] ( SI) ( SI) + 1 LOD SW: word string element at phy sical address derived from DS and SI i s to be loade d into A X. S I is automatically incremented b y 2. ( AX) [(DS) + ( SI)] ( SI) ( SI) + 2 STO SB: Stores a byte from AL i nto a string location in memory. This time conten ts of ES and DI are used to form address of storage location in memor y. [(ES) + (DI)] ( AL) ( DI) ( DI) + 1 S TO SW: [(ES) + ( DI) ] ( AX) ( DI) ( DI)

45 ROCONTROL LER Repeat String: RE P b asic s tring o perations m ust b e r epeated to p rocess array s o f data. T his i s d one by i nserting pe at prefix b efore i nstruction i s t o b e r epeated. Prefix R EP c auses b asic string ope ration to b e repeated u ntil cont ents o f reg ister CX become equal t o z e ro. E ach t ime instruction i s ex e cuted, i t causes C X t o be t ested ze ro, i f C X i s found t o b e nonzero it is decremented by 1 and basic string o peration is repeated. Example: Clearing a block of memory by repeating S TOSB MOV AX, 0 M OV E S, A X MOV DI, A0 00 M OV C X, O F CDF REP STOS B N EXT: prefixe s R EPE R EPZ s tand same fu n ction. y m eant u se C MPS S CAS i nstructions. W ith R EPE/REPZ th e ba sic comp o r s can ope ration c an be repeated as long as both contents of CX are not equal to zero and zero flag i s 1. R EPNE R EPNZ w orks similarly t o R EPE/REPZ exc ept n ow o peration is repeated as long a s CX¹0 and ZF= 0. Comparison or scanning i s to be performed as long a s string elements are unequal (ZF=0) and end of string is not y e t found (CX¹0). A uto Indexing for String Instructions: S I & DI addr esses are eith er automatically increme nted o r de cremented ba sed o n se tting of direction flag DF. When CLD (Clear Direction Flag) is executed DF=0 permits auto increment by 1. When STD (Set Direction Flag ) is executed DF=1 permits auto decrement by 1. UNIT-II 8086 SYSTEM BU S STRUCTURE 8086 Microprocessor i s a 16-b it C PU a vailable i n 3 c lock r ates, i.e. 5, 8 10MHz, p ackaged i n a 40 p in CERDI P o r p lastic pack a ge Microproc essor o perates in s ingle p rocessor o r m ultiprocessor c onfigurations t o a chieve h igh perf o rmance. p in c onfiguration i s a s s hown i n fi g 1. S ome o f p ins s erve a particula r function i n minimu m m ode (single processor m ode) o rs func tion i n maxi mum m ode ( multiprocessor m ode) configur at ion s ignals c an b e c ategorized i n t hree g roups. f irst s ignals having c ommon f unctions i n min imum a s w ell as maxi mum m ode, sec ond are sig nals w hich h ave s pecial f unctions i n m inimum m ode t hird signa ls h aving s pecial f unctions for max imum mode signals following signal description is common for both minimum and maximum modes 41

46 Fi g.2.1 Bus signals 8086 sig nals c an b e categ orized i n three g roups. f irst are th e signa ls having c ommon f unctions i n min imum a s w ell as maxi mum m ode, sec ond are th e sig nals w hich h ave s pecial f unctions i n mini mum m ode t hird signa ls h aving s pecial f unctions maximum mode. following signal description common for both minimum and maximum modes. AD15-AD0: se th e t ime multiplexe d memory I / O addr ess da ta l ines. Addres s r emains o n l ines d uring T 1 s tate, w hile i s a vailable o n b us d uring T 2, T 3, T W T 4. H ere T1, T 2, T 3, T 4 T W c lock s tates o f a m achine cyc le. T W is a w ait s tate. se l ines a ctive hig h float t o a t ristate dur ing i nterrupt acknowledg e and local bus hold acknowledge cycle s. A19/S6, A18/S5, A17/S4, A16/S3: se are time multiplexe d addre ss and sta t us lines. D uring T 1, se m ost s ignificant a ddress l ines o r m emory o pera tions. D uring I / O o perations, se l ines are l ow. During memory o r I / O op e rations, statu s i nformation i s a vailable on t hose lines T 2, T 3, T W T4. s tatus of i nterrupt enable flag b it(displayed o n S 5) i s u pdated a t b eginning o f e ach clock cycle. S 4 S 3 c ombinedly indic ate w hich s egment r egister i s presently being use d for me mory accesse s a s s hown i n T able 2.1. se l ines f loat t o tri-s tate o ff ( tristated) d uring l ocal b us h old a cknowledge. s tatus l ine S 6 i s a lways l ow (lo gi cal). a ddress b its s eparated sta tus bits usin g latches controlled by AL E signal. 42

47 Table 2.1 Bus High Enable / statu s BHE/S7-B us H igh Enable/Statu s: b us h igh enabl e s ignal i s u sed t o i ndicate t ransfer o f da ta over higher order ( D15- D 8) da ta b us a s show n i n Table 2.1. I t g oes l ow t ransfers o ver D15-D 8 i s u sed t o d erive c hip s elects o f odd a ddress memory b ank o r p eripherals. B HE i s l ow during T1 r ead, w rite i nterrupt acknowle dge cycl e s, when- e ver a byte i s t o b e t ransferred o n h igher byte o f data b us. s tatus i nformation i s a vailable d uring T 2, T 3 T 4. s ignal i s a ctive low i s t ristated during ' h old'. It is low during T1 for first pulse of interrupt acknowledge cy c le. T able 2.2 Bus high enable statu s RD-Rea d: R ead s ignal, w hen l ow, i ndicates periphera ls proce ssor i s performing a memory or I / O r ead o peration. RD i s a ctive l ow shows s tate for T 2, T 3, TW o f any read cycle. signal remains tristated during ' hold acknowledge'. READY: T his i s a cknowledgement s low d evices o r memory y ha ve c ompleted transf e r. sig nal made availa ble by devices i s sy nchronized by 8284A clock g enerator t o p rovide ready i nput t o sig nal i s a ctive hi g h. INTR- l nterrupt R equest: T his i s a l evel triggere d i nput. T his i s s ampled d uring l ast c lock c ycle of each i nstruction t o d etermine availability o f r e quest. I f any i nterrupt r equest i s p ending, processor e nters i nterrupt a cknowledge c y cle. T his c an b e internally m asked b y rese tting i nterrupt e nable f lag. T his s ignal i s a ctive h igh internally sy n chronized. TEST: T his i nput i s exa mined b y a ' WAIT' i n struction. I f T EST i nput g oes l ow, e xecution w ill c ontinue, e lse, p rocessor r emains i n a n i dle s tate. i nput i s synchronized internally during each clock cycle on leading edg e of clock. NMI-Non-m askable I nterrupt: T his i s a n edge-trig gered i nput w hich c auses a Ty pe2 inter r upt. N MI i s n ot m askable internally by softwar e. A transitio n l ow t o hig h i nitiates interrupt resp onse a t e nd of current i nstruction. T his i nput i s internally sy n chronized. R ESET: Th is i nput c auses p rocessor t o t erminate c urrent activity s tart exe cution F FFF0H. s ignal i s active h igh m ust b e a ctive a t l east fou r c lock cycl e s. It r estarts e xecution w hen R ESET r eturns l ow. R ESET i s a lso internally sy nchro nized. CLK-C lock I nput: clock input provides basic timing for processor operation and b us control activity. Its an asymmetric square wave with 33% duty cyc le. range of frequency for different 8086 versions is from 5MHz to 10MH z. 43

48 V CC: + 5V p ower supply o peration o f i nternal c ircuit. G ND g round interna l circ u it. M N/M X : logic level at this pin decides wher processor is to operate in eir minimum (single processor) or ma x imum ( multiproces sor ) mode. following pin functions are for minimum mode operation of M /IO -M emory/io: T his i s a s tatus l ine logically e quivalent to S2 i n maxi mum m ode. W hen i t i s l ow, i t i ndicates C PU i s h aving a n I/O o peratio n, w hen i t i s h igh, i t i ndicates C PU i s h aving a memory op e ration. T his l ine becom es a ctive i n p revious T 4 r emains a ctive t ill f inal T 4 o f c urrent cycl e. I t i s t ristated d uring l ocal b us " hold acknowledge". I NTA -I nterrupt Acknowl e dge: T his s ignal i s u sed a s a r ead s trobe i nterrupt a cknowledge c ycles. I n o r w ords, w hen i t g oes l ow, i t m eans p rocessor h as a ccepted i nterrupt. It i s a ctive l ow during T 2, T 3 TW of e ach interr upt acknowledg e cycle. ALE-A ddress lat ch Enable: T his o utput s ignal i ndicates availability of va lid a ddress on a ddress/data l ines, i s connec ted t o latc h ena ble inpu t o f latch e s. Th is signal is active high and is neve r tristate d. D T / R -D ata Transmit/Receive: T his o utput i s used t o decide direct ion o f f low t hrough transreceive rs ( bidirectional buffers ). W hen processor s ends o ut dat a, this s ignal i s h igh w hen p rocessor i s receiving, t his s ignal i s l ow. Logicall y, t his i s e quivalent t o S 1 i n maxi mum m o de. I ts t iming i s s ame a s M /I/O. This i s t ristated d uring ' hold acknowledge'. DEN-D ata Enabl e T his s ignal i ndicates availability o f v alid o ver a ddress/data line s. I t i s u sed t o e nable t ransreceivers ( bidire ctional b uffers) t o separa te m ultiplexed a ddress/data si g nal. I t i s a ctive fro m m iddle o ft2 u ntil m iddle o f T 4 DEN is tristated during ' hold acknowledge' cy c le. H OLD, HLDA-H old/hold Acknowled g e: W hen HOL D l ine goes h i gh, i t indica tes t o p rocessor that anor m aster i s reque sting b us a ccess. process o r, a fter receiving H OLD r equest, i ssues h old acknowledg e s ignal o n HLDA p in, i n middle o f n ext c lock c ycle a fter c ompleting c urrent b us ( instruction) c ycle. A t s ame t ime, processor floats loc al bus control lines. When proces sor d etects H OLD l ine lo w, i t l owers HLDA signal. HOL D i s a n asynchr onous i nput it should be externally sy n chronized. I f D MA r equest i s m ade w hile C PU i s p erforming a memory or I / O cycl e, i t w ill release local bus during T 4 provide d : 1. request occurs on or before T 2 state of current cycle. 2. c urrent cy cle i s no t operating o ver low er by te of a w ord (or operating o n a n o dd addres s). 3. current cycle is not first acknowledge of an interrupt acknowledge sequence. 4. A Lock instruction is not being execute d. S o far we have presented pin descriptions of 8086 in minimum mode. following pin functions are applicable for maximum mode operat ion o f S 2, S 1, S 0 -Status L ines: se status l ines w hich refle ct ty pe of oper a tion, b eing c arried o ut by p rocessor. se b ecome a ctive during T 4 o f p revious cy cle r emain a ctive d uring T 1 T 2 o f c urrent b us cycl e. stat us l ines r eturn t o passiv e s tate d uring T 3 o f c urrent b us cy cle s o y may ag ain b ecome a ctive next b us c ycle d uring T 4. A ny c hange i n se l ines d uring T3 i ndicates s tarting o f a ne w c ycle, return t o pass ive s tate i ndicates end o f b us cy cle. se s tatus l ines are encoded in table

49 T able 2.3. Status lines L OCK: T his o utput p in i ndicates o r syst em b us m asters w ill b e prevent ed gainin g syste m b us, w hile L OCK sig nal is l ow. LOCK signa l i s a ctivated by ' LOCK' prefix i nstruction r emains a ctive unt il c ompletion o f next instruct io n. T his f loats t o tri-s tate off d uring " hold acknowled g e". When C PU i s executing a c ritical i nstruction w hich r equires s ystem b us, L OCK p refix i nstruction e nsures o r processors connec ted in sy stem w ill n ot gain c ontrol o f b us. 8086, w hile e xecuting p refixed i nstruction, a sserts bus l ock s ignal o utput, w hich m ay be connected to an externa l bus controlle r. QS1, QS0-Queue Status : se lines give information about status of code prefetch queue. se ac tive d uring CL K cy cle afte r which que ue operat ion i s perform e d. se are encode d as shown in Table 1.4. T able 2.4. Queue Sta tus This modificat ion in a simple fet ch execute architecture o f a conventional m icroprocessor offe rs an a dded a dvantage o f p ipelined p rocessing of i nstructions a rchitecture h as a 6-b yte instruc tion prefetc h q ueue. T hus e ven l argest (6- b y tes) i nstruction c an b e p refetched memory and s tored i n p refetch q u eue. T his r esults i n a faster exe cution o f th e inst r uctions. I n 8085, a n i nstruction ( opcode oper ) i s f etc hed, d ecoded e xecuted only afte r exe cution o f t his i nstruction, next o ne i s f etched. By prefetching i nstruction, re i s a c onsiderable speeding u p i n instructio n e xecution i n T his s cheme i s k nown a s i nstruction pipelining. A t th e s tarting C S: I P i s l oaded r equired a ddress w hich exe cution i s t o b e s tarted. I nitially, q ueue w ill b e empty and microproc essor starts a fetc h o peration t o brin g one by te ( f irst b yte) o f i nstruction c ode, i f C S: I P address i s o dd o r t wo by tes a t a t ime, i f C S:IP a ddress i s e ven. fir st by te i s a c omplete opc ode i n c ase of s ome instr uctions ( one byte o pcode i nstruction) and i t i s a p art o f opcod e, in c ase of o r instruction s ( two byte l ong 45

50 o pcode instructions), remaining pa rt o f opc ode m ay l ie i n s econd byte. But invariably f irst by te o f a n instruc tion i s a n opcod e. se opcodes along data f etched a rranged i n queue. W hen fi rst byte queue g oes decoding i nterpretation, o ne by te in q ueue b ecomes e mpty subsequently q ueue i s u pdated. m icroprocessor d oes n ot p erform n ext f etch o peration t ill a t l east t wo by tes o f i nstruction q ueue are e mpti ed. i nstruction e xecution cycle i s n ever b roken f etch opera t ion. A fter decoding f irst byt e, decod ing c ircuit d ecides wheth er i nstruction i s o f s ingle o pcode b yte o r d ouble o pcode b y te. I f i t i s s ingle o pcode b yte, n ext b ytes tre ated a s byte s d epending u pon decode d i nstruction l ength, o r w ise, next b yte i n q ueue i s treate d a s s econd byte o f i nstruction o pcode. s econd byte i s n decode d i n c ontinuation f irst by te t o decide instr uction length and n umber o f subse quent byte s t o be trea ted a s instructio n. queue i s u pdated af ter every by te i s r ead q ueue b ut f etch cy cle i s i nitiated b y BI U only if a t l east, t wo b ytes o f q ueue empty E U ma y b e concurrently exe cuting fetc hed instructions. next byte after instruction is completed is again first opcode byt e of n ext i nstruction. A s imilar p rocedure i s repe ated t ill c omplete exe cution o f progr am. m ain p oint t o b e n oted h ere i s, f etch o peration o f next i nstruction i s o verlapped exe cution o f c urrent instruct io n. A s s hown i n architectu r e, re t wo separate u nits, namel y, exe cution u nit b us i nterface unit. W hile th e exe cution u nit i s busy in exe cuting a n instructi o n, a fter i t i s completely d ecoded, b us i nterface u nit may b e f etching byte s o ( next i nstruction m emory, depending upon queue stat us. Figure 1.6 explains queue oper at ion. R Q/GT0, RQ/GT1-Re Q uest/grant: se pins u sed by o r loc al b us m asters, i n m aximum m ode, t o ce p rocessor t o release l ocal b us a t e nd o f processor' s c urrent b us c ycle. E ach o f p ins i s b idirectional R Q/GT0 h aving higher priority t han R Q/ G T1, R Q/GT p ins h ave inter nal pull-u p r esistors may b e l eft u nconnected. Th e request! grant sequence is a s f o llows: 1. A pulse one clock wide from anor bus master requests bus acce s s to During T4 (current) or T1 (next) clock cycle, a pulse one clock wide from 8086 to requesting m aster, i ndicates 8086 h as a llowed l ocal b us t o f loat i t w ill e nter " hold ackno w ledge" s tate at next c lock cycle. C PU' s bus interface u nit i s likely to be disconnected from local bus of sy s tem. 3. A o ne c lock wide puls e a nor ma ster indicate s t o 8086 ' hold' request i s a bout t o e nd 8086 m ay re gain c ontrol o f th e l ocal b us a t next c lock c y cle. Th us e ach m aster t o m aster exchang e o f l ocal b us i s a sequence o f 3 p ulses. re m ust b e a t l east o ne d ead c lock cycl e a fter ea ch b us ex c hange. r equest grant p ulses a ctive l ow. F or b us r equests t hose r eceived w hile 8086 i s p erforming memory o r I / O cycl e, granting o f b us is gove rned by rule s a s discu ssed in c ase o f H OLD, HLDA i n minimum mode. 2.2 Basic configurations : Read Write Timi ng Diagram General Bus Operati on 8086 ha s a c ombined addr ess da ta bus commonly referred a s a t ime multiplexe d a ddress data b us. m ain re ason be hind mu ltiplexing addre ss and da ta over sa me p ins i s m aximum utiliza tion o f p rocessor p ins i t fa cilitates u se of 40 p in standar d D IP p ackage. b us c an b e demultiplexe d u sing a f ew l atches t ransreceivers, whene ver require d. Basically, all processor bus cycle s consist of a t least four clo ck c y cles. se are referred t o a s T 1, T 2, T 3, T 4. a ddress i s t ransmitted b y processor d uring T 1, I t i s p resent o n b us o nly one c y cle. ne gative edg e o f t his A LE p ulse i s use d t o separ ate address and data or status informa t ion. 46

51 ROCO NTROLLER I n maxi mum m ode, s tatus l ines S 0, S 1 S 2 u sed t o i ndicate type o f op e ration. S tatus b its S 3 t o S 7 multiplexe d h igher o rder addre ss b its and th e BHE sign a l. Address is valid during T1 while status bits S3 to S7 are valid during T2 throug h T4. F ig.2.2. General Bus operat ion cycl e 2.3 System Bus timings: Minimum mode 8086 system and timi ngs I n a m inimum m ode 8086 s y stem, microproc essor 8086 i s o perated i n m inimum m ode b y s trapping i ts M N/MX* p in t o l ogi c1. I n t his m ode, a ll c ontrol s ignals g iven out by microprocessor chip itself. re is a single microproc essor in minimum mode system. remaining components in system latches, t ransreceivers, clock g enerator, memory and I/ O devi ces. o pcode fetc h r ead cy cles s imilar. H ence t iming d iagram c an b e c ategorized i n t wo p arts, f irst i s t iming d iagram for r ead cycle and s econd i s t iming diagram for write cycle. F ig 1. 2 s hows r ead cycle t iming dia g ram. rea d cycle be gins i n T1 a ssertion o f address l atch ena ble ( AL E) sig nal a lso M/ I O* si g nal. D uring n egative going edg e o f th is s ignal, v alid a ddress i s latche d o n local b us. B HE* A 0 signals addre ss l o w, high o r both byt e s. F rom T l t o T 4, M/ I O* s ignal i ndicates a m emory o r I / O operation. A t T 2 a ddress i s r emoved local b us i s sent to th e output. b us i s n t ristated. r ead ( RD* ) c ontrol s ignal i s a lso a ctivated i n T 2. r ead ( RD) s ignal cause s a ddressed de vice t o e nable i ts b us drivers. A fter R D* g oes l ow, v alid i s a vailable o n b us. Th e addresse d d evice w ill d rive RE ADY l ine h igh, when p rocessor r eturns r ead s ignal t o h igh l evel, addr essed devic e wil l again tristate its bus drive rs. 47

52 Fi g M inimum Mode 8086 System A w rite cy cle a lso begins asse rtion of ALE e mission of addr e ss. M/IO* sig nal is again asserted t o i ndicate a m emory or I /O operation. I n T2 after sending a ddress i n T l processo r s ends t o b e w ritten t o a ddressed locat io n. Th e r emains o n b us u ntil middle o f T 4 stat e. W R* becomes a ctive a t b eginning o ft2 ( unlike R D* i s s omewhat d elayed i n T 2 t o p rovide t ime f loating). B HE* A 0 s ignals u sed t o sele ct p roper by te or byte s o f memory o r I/O w ord t o b e read o r written. M/ I O*, RD* W R* s ignals i ndicate type s o f trans fer a s spec ified i n T able T able 2. 5 Read wr ite cycle 48

53 Fi g Read cycle timin g diagram for minimum mode F ig 2.5 Bus request and busgrant t imings in minimum mode system 2.3 System Design using 8086: Maximum mode 8086 system and timi ngs In maximum mode, 8086 is operated by strapping MN/MX* pin to g r ound. I n t his m ode, proc essor deriv es s tatus sig nals S2 *, S 1 * S 0 *. A nor c hip c alled b us c ontroller d erives con trol s ignals using t his st atus informat io n. I n maximu m m ode, re may be more than one microprocessor in sy s tem configuration. basic functions of bus controller chip IC 8288, is to derive control sign als like R D* W R* ( for me mory I/O devices ), D EN*, D T/R*, ALE, e tc. u sing i nformation m ade ava ilable by p rocessor o n th e s tatus l ines. b us c ontroller c hip ha s 49

54 in put l ines S 2*, S 1* and S 0 * CL K. se i nputs t o 8288 are dr iven by CP U. It d erives o utputs A LE, D EN*, D T/R*, MW T C*, AMW C *, I ORC*, IOW C* AI O WC*. A EN*, I OB C EN p ins especially usef ul for multip rocessor s y stems. AEN* and IOB are generally g rounded. CEN pin is usually tie d to +5V. Fi g. 2.6 Maximum mode configuiration significanc e o f M CE/PDEN* o utput depe nds u pon s tatus of th e IOB p in. I f I OB i s g rounded, i t a cts a s m aster c ascade ena ble t o cont rol cascade d 8259A; e lse i t a cts a s peripheral data enable used in multiple bus configura t ions. I NTA* p in i s u sed t o i ssue t wo i nterrupt a cknowledge p ulses t o i nterrupt controller or to an interrupting device. IORC*, IO WC* are I/O read command and I/O write command signals respectively. se sig nals e nable an I O interface t o read o r wr ite da ta or t o th e addressed p ort. M RDC*, M WTC* memory read comm and memory wr ite c ommand signa ls respectively may b e u sed a s memory r ead and w rite s ignals. A ll se comm signa ls instruct memory to accept or send data from or to b us. For both of se write command signals, advanced signals namely AIOWC* an d AMWTC* are available. y also serve same purpose, b ut are activated o ne c lock cycle e arlier t han I OWC* M WTC* s ignals, respectivel y. maxi mum m ode sy stem is shown in fig m aximum mode syste m t iming d iagrams a lso d ivided i n t wo p ortions a s r ead ( input) w rite ( output) t iming d iagrams. address/ and a ddress/status t imings are s imilar t o th e m inimum m ode. A LE i s a sserted in T 1, just l ike minimu m m ode. only diff erence l ies i n s tatus s ignals u sed a vailable c ontrol a dvanced comm and s ignals. fig. 1.2 shows maximum mode timings for read o peration while fig. 1.3 shows same for write o peration. 50

55 F ig.2.7 M emory read cycle Fig.2.8 Memo ry write cycle 2.5 IO programmi ng Fig 2.9 RG*/GT* Tim ings in maximum mo de O n 8086, a ll prog rammed c ommunications I / O por ts i s OUT instructions de fined in Fig d one by I N IN and OUT instruct ions 51

56 ROCONTR OLLER Name Mnemonic Format Descr iption In put Long form, byt e IN AL, PORT ( AL ) < - ( PO R T) Long form, word I N AX, PORT ( AX) < - ( POR T+ 1: PO R T) Short form, byt e IN AL, DX ( AL) < - ((DX)) Short for m, word I N A X, DX ( AX) < - ((DX) + 1: ( DX )) O utput L o ng form, byt e OUT P ORT, AL ( PORT) < - ( AL) Long form, word OUT POR T, AX ( PORT+1: PORT) < - ( AX) Short form, byt e O UT DX, AL ((DX)) < - ( AL) Short for m, word OUT DX, AX ((DX)+1: (DX)) < - ( A X) Note: PORT is a constant ranging fro m 0 to 255 Flags: No flag s are affected Addressing modes: Operands are limite d as indicate d above. I f s econd o perand i s D X, n re i s only on e by te i n i nstruction c ontents o f D X use d a s p ort address. U nlike m emory addressin g, content s o f D X n ot m odified b y any segment r egister. T his a llows v ariable access t o I / O ports i n rang e 0 t o 64K. machine language code for I N instruction is: A lthough A L o r A X i s i mplied a s f irst o perand i n a n I N i nstruction, e ir AL or A X m ust be specified so that assembler can determine W- b it. S imilar c omments apply t o O UT instruc tion exc ept i t po rt addre ss i s d estination i s refore indicate d by fir st oper, and second oper i s eith er AL or AX. Its machine code i s : N ote i f l ong m o f I N o r O UT i nstruction i s u sed p ort a ddress m ust b e i n r ange 0000 t o 00FF, b ut s hort m i t c an b e any addre ss i n rang e 0000 t o FFF F ( i. e. any address in I / O address space). Neir IN nor OUT affects flag s. I N i nstruction m ay b e u sed t o i nput a b uffer re gister o r s tatus a status regi ster. instruct ions I N A X, 28H MOV DATA_WORD, AX w ould m ove w ord in p orts w hose addre ss t o location DATA_ WORD. memory 52

57 2.6 Introduction to Multiprogrammi ng I n order t o a dapt t o a s many s ituations a s p ossible b oth h ave be en give n t wo modes of oper a tion, minimum mo de and th e maxi mum m ode. mini mum mo de i s u sed a s mall sy stem a s ingle p r ocessor, a syste m i n which 8086/ 8088 g enerates a ll n ecessary b us c ontrol s ignals directly ( reby m inimizing r equired b us c ontrol l ogic). m aximum m ode i s medium-s ize t o l arge systems, w hich o ften include two or more processor s. 2.7 S ystem Bus structure F ig.2.10 T ypical system Bus architecture T able 2.6 P ins for read/ write operation 2.8 M ultiprocessor Systems Multiprocessor Syste ms r efer t o u se of m ultiple proces sors tha t execute instructio ns simultaneously and communicate using m ailboxes and semaphores Maximum mode of 8086 is designed t o implemen t 3 basic multiproces sor configur at ions: 1. Coproc es sor (8087) 2. C losely coupled (dedicated I / O processor: 8089) 53

58 3. L o osely coupled (Multi bus) C oprocessors closely couple d external processor share: configurati ons s imilar - b oth C PU Mem ory I/ O system B u s & bus control logi c Clock generat or 2.9 Coprocessor configura tions Coprocessor Config u ration: WAIT instruction allows processor to sy n chronize itself with external hardware, eg., waiting for 8087 math co-processor. W hen CPU executes W AIT waiting state. TEST input is asserted (low), waiting state is completed and execution w ill resume. ESC instruc t ion: E SC opcode, operand, opcode: i mmediate value recognizable to a coprocessor as an instruction opco de Operand: name of gister or a memory address (in any m ode) W hen CPU executes ESC instruction, processor accesses memory operand by p lacing address on address bus. If a coprocessor is configured to share sys tem bus, it will recognize ESC i nstruction and refore will get opc ode and operan d Fi g Synchronisation b etween 8086 and its coprocesssor 54

59 F ig 2.12 M achine code formats for ESC instruction F ig.2.13 Coprocessor co nfiguration 55

60 F ig.2.14 c losely coupled configuration Coprocessor cannot take control of bus, it does everything th rough CPU Closely Coupled processor may take control of bus independently shares CPU s clock bus control log i c. communication with host CPU is by w ay of shared memory h ost sets up a message (command) in memory independent processor inte rrupts host on complet ion Two 8086 s cannot be closely coupled 2.10 Closely Coupled Configurati on Fig.2.15 Interprocessor comm unication through shared memory 56

61 Fig.2.16 Bus allocation schemes Loosely Coupled Confi g urations: A loosely coupled configuration provides following advantag e s: 1. High system throughput can be achieved by h aving more than one CPU. 2. syst em c an b e exp anded i n a m odular for m. E ach b us m aster mod ule i s a n i ndependent u nit normally r esides on a sepa rate PC b oard. refo r e, a b us m aster m odule can b e add ed or remove d out affectin g oth er module s i n syste m. 3. A failure in one module normally does not cause a b reakdown o f entir e sy stem and faulty module can be easily d etected and replaced. 57

62 4. E ach b us m aster may h ave a l ocal b us t o access dedicated memory o r I/O de vices s o a g reater d egree o f p arallel processing c an b e a chieved. M ore t han o ne b us master module may have access to shared sys tem bus Extra bus control log ic must be provided to resolve bus arbitrat ion problem. extra logic is called bus a ccess logic it is i ts responsibility to make sure that only one bus master at a time ha s control of b us. Simultaneous bus requests are resolve d on a priority basis : re are thre e scheme s fo r establishing priority: 1. Daisy chaining. 2. Polling. 3. In dependent requesting 2.11 Introduction to Advanced processors: Microproces sor Salient Fe atures of i s f irst m ember o f family o f advanc ed micropr ocessors with memory m anagement and protection abilities C PU, with its 24-bit address b us is a ble t o a ddress 16 M bytes o f physic al memor y. V arious v ersions o f ava ilable th at r uns o n MHz, 10 M Hz 8 M Hz c lock frequen c ies i s upwardly c ompatible with 8086 in terms of instruction se t h as t wo o perating m odes namely real addres s m ode v irtual a ddress m ode. I n r eal a ddress m ode, c an addre ss upto 1 Mb o f phy sical memo ry a ddress l ike I n v irtual addr ess m ode, i t c an address u p t o 16 M b o f physic al memory address space and 1 GB of virtual memory address spac e. i nstruction s et o f i ncludes i nstructions o f h as s ome e xtra instructio ns t o s upport operating syst em memory m anagement. In r eal a ddress m ode, i s o bject c ode c ompatible with I n p rotected v irtual addre ss m ode, i t i s s ource c ode compatible pe rformance of is five times faster than standa rd Need for Memory Managemen t p art o f m ain m emory i n w hich o perating syste m o r syste m p rograms s tored i s n ot a ccessible t o users. I t i s r equired t o e nsure s mooth exe cution o f r unning proce ss also t o ensure ir protect io n. memory manag ement w hich i s a n i mportant t ask o f o perating s ystem i s s upported by a hardware u nit c alled m emory manageme n t unit. Swa pping in o f Pr ogram F etching o f a pplication p rogram secondary memory placing i t i n physical memory for execution by CPU. Swapping out of executable Progra m S aving a p ortion o f p rogram o r i mportant r esults r equired f urr exe cution b ack t o secondary memory to m ake prog ram mem ory free f urr executi on o f a nor required portion of progra m Concept of Vir tual Memory L arge a pplication p rograms r equiring memory m uch m ore t han physically ava ilable 16 M bytes o f memory, may b e exe cuted by diving it i nto s maller se gments. T hus use r, re e xists a very l arge l ogical memory s pace w hich i s n ot actually av a ilable. T hus re e xists a v irtual m emory w hich d oes n ot exi st physically i n a s y stem. T his c omplete p rocess of virtual memory management is take n care o f by CPU and supporting operating sy s tem Internal Architectur e o f Register Organiza tion of CPU contains almost same set of registe rs, as in 8086, namel y 1. Eight 16- bit general purpose registers 2. Four 16-bit segmen t registers 58

63 3. Status and control registers 4. In struction Pointer F ig.2.17 R egister set of F ig 2.18 Flag registers D2, D4, D6, D7 D11 c alled a s s tatus flag bit s. bits D8 ( TF) D9 ( I F) are u sed c ontrolling m achine o peration t hus y c alled c ontrol fla g s. a dditional f ields available in flag register s are: 1. IO PL - I/ O Privileg e Field (bits D12 and D13) 2. NT - Nested Task flag ( b it D 14) 3. PE - Protection Ena b le ( b it D16) 4. MP - M onitor Processor Extension ( bit D 17) 5. EM - Processor Exte nsion Emulator ( b it D18) 6. T S Task Switc h (bit D 19) P rotection E nable f lag pla ces in p rotected m ode, if set. T his c an only b e c leared b y r esetting C PU. I f M onitor P rocessor Ext ension f lag i s s et, a llows W AIT instruction to g enerate a processor extension not p resent exc ep tion. P rocessor E xtension E mulator f lag i f s et, cause s a p rocessor ext ension a bsent exc eption per mits emulation of processor extension by CPU. T ask S witch f lag i f s et, i ndicates next i nstruction u sing ext ension w ill generate e xception 7, p ermitting C PU t o t est whe r curr ent processor ext ension i s for current ta s k. Machine Stat u s Word ( M SW) m achine sta tus w ord c onsists o f f our fla gs P E, M O, E M T S o f f our low er o rder b its D 19 t o D 16 o f uppe r word o f flag re g ister. LMSW SMSW i nstructions ava ilable i n i nstruction s et o f t o w rite r ead MS W i n r eal address mode. 59

64 Internal Block Diagram o f Fi g I nternal Block diagram of CPU contain four functional block s 1. Addre s s Unit ( A U) 2. B us I n it (B U ) 3. I nstruction Unit ( I U ) 4. Execution U n it ( E U) a ddress u nit i s respon sible calc ulating phy sical addres s of instru ctions C PU w ants t o a ccess. A lso a ddress l ines d erived by t his u nit may be u sed t o a ddress d ifferent p er ipherals. p hysical a ddress c omputed by addres s u nit i s h anded o ver t o b us u nit ( BU) o f C PU. M ajor func tion o f b us u nit i s t o fetc h instr uction b ytes memor y. I nstructions fetched i n advanc e stored i n a queue t o ena ble fa ster e xecution o f i nstructions. b us u nit a lso c ontains a b us c ontrol m odule c ontrols p refetcher modul e. se prefetche d i nstructions a rranged i n a 6-by te i nstructions q ueue. 6-by te pr efetch q ueue for wards i nstructions arranged i n i t t o i nstruction uni t (I U ). i nstruction u nit a ccepts i nstructions p refetch queue an instruction decoder decodes m o ne b y o ne. de coded i nstructions ar e la tched o nto a decoded i nstruction q ueue. o utput o f decodi ng cir cuit d rives a c ontrol circuit i n executio n uni t, w hich i s r esponsible e xecuting i nstructions receive d d ecoded i nstruction q ueue. Th e d ecoded i nstruction queue s ends p art o f i nstruction o ver b us. E U contains re gister bank used for s toring data a s s cratch p a d, o r u sed a s s pecial p urpose registe rs. A LU, h eart o f E U, c arries o ut a ll a rithmetic l ogical operatio ns and sends results over data bus or back to registe r ba n k Interru pts of Interrupts of may be divided into three categorie s, 1. External or hardware interru pts 2. INT instruction or software interr upts 3. Interrupts generated internally by e xceptions W hile exe cuting a n i nstruction, C PU m ay sometim es b e confr onted a s pecial s ituation b ecause o f whic h fur r exe cution i s no t perm itte d. W hile trying to exe cute a 60

65 d ivide by ze ro instru c tion, C PU dete cts a majo r err or s tops fur r ex e cution. In t his c ase, w e say an exc eption h as b een gen e rated. I n o r wo r ds, an i nstruction e xception i s a n u nusual s ituation e ncountered d uring exe cution o f a n instruct ion s tops f urr e xecution. r eturn addr ess from a n ex c eption, i n m ost o f c ases, points to instruction that caused exc ep tion. A s i n c ase o f 8086, i nterrupt v ector t able o f r equires 1Kbyte s of spac e for s toring 256, four-by te po inters t o p oint t o corresponding 256 interrupt s ervice r outines ( l SR). Each p ointer c ontains a 16-b it off set followe d by a 16-b it segme nt selecto r t o p oint t o a p articular I SR. c alculation o f vector p ointer a ddress i n i nterrupt v ector ta ble (8-bit) INT type is exactly s imilar to L ike 8086, su pports s oftware i nterrupts o f ty pe 0 ( I NT 00) t o type F FH ( INT FFH). M askable I nterrupt INTR: T his i s a m askable i nterrupt i nput p in o f w hich I NT ty pe i s t o b e p rovided by a n ext ernal c ircuit l ike a n i nterrupt c ontroller. o r f unctional detai ls of this interrupt pin are exactly similar to I N TR input of Non- Maskable Interrupt NMI: It has higher priority than I N TR interrupt. W henever t his i nterrupt i s r eceived, a v ector valu e o f 02 i s s upplied internally t o c alculate p ointer to i nterrupt v ector t able. O nce C PU r esponds t o a N MI r equest, i t d oes n ot s erve any o r i nterrupt r equest ( including NM I ). Fur r i t does n ot s erve p rocessor e xtension ( coprocessor) s egment overrun i nterrupt, t ill e ir i t exe cutes I RET o r it is reset. To start with, this clears IF flag which is set again with exe cution of I RET, i. e. return from inte r rupt. Single Step Interru pt A s i n 8086, t his i s a n in ternal interr upt comes into a ction, i f t rap f lag ( TF) o f i s se t. CPU s tops exe cution a fter each i nstruction cycle s o r egister c ontents ( including f lag r egister), p rogram s tatus w ord memor y, e tc. may be exa mined a t e nd o f each i nstruction ex e cution. T his i nterrupt i s u seful troubleshooti ng softwar e. An interrupt vector type 01 is reserved for this inte rru pt. Interrupt Prioritie s : I f m ore t han o ne interrup t s ignals occur simultaneousl y, y ar e pr ocessed according to ir priorities as shown be l ow: 61

66 Signal Description of C LK: T his i s system c lock i nput p in. c lock frequency a pplied a t t his p in i s d ivided b y t wo internally i s u sed deriving f undamental t imings bas ic o perations o f circu it. clock is generated using 8284 clock generator. D15-D0: se sixteen bidirectional data bus line s. A23-A0: se physical a ddress o utput line s u sed to a ddress memor y o r I / O devi c es. address lines A23 - A 16 are zero during I/ O transfers BHE: T his o utput signal, a s i n 8086, i ndicates re i s a transf er o n th e highe r by te o f data b us ( D 15 D 8 ). S1, S0: se active-l ow s tatus o utput s ignals w hich indicate i nitiation o f a b us c ycle and with M/IO and COD/INTA, y define type of bus cy c le. M / IO: T his o utput line differentiate s memory ope rations I/ O o perations. I f t his sig nal i s i t 0 i ndicates that a n I / O cy cle o r I NTA cycle i s i n proc ess if it is 1 it indicates that a memory or a HALT cy c le is in progress. C OD/ INTA: T his o utput s ignal, i n c ombination M / I O signa l S 1, S0 distinguishes different memory, I / O and INTA cy c les. L OCK: T his active-l ow o utput p in i s u sed t o p revent o r m asters from gaining con trol o f b us c urrent f ollowing b us cycl e s. T his p in i s a ctivated by a " LOCK" i nstruction p refix, o r automatically by hardw during X CHG, i nterrupt acknowledge or descriptor table acces s R EADY T his active-low i nput p in i s u sed t o insert w ait stat es i n a b us cycl e, interfacing low speed peripheral s. This signal is neglected during HLDA cy c le. HOL D and HL DA T his p air o f p ins i s u sed by ext ernal b us ma sters to r equest for c ontrol o f sy stem bus ( HO L D) t o c heck wh er mai n processor h as grante d control (HLDA) or not, in same way a s it was in I NTR: Through t his acti ve high i nput, a n ext ernal d evice re quests t o s uspend current instruction execution and serve interrupt request. Its function is exactly simil ar to that of I N TR pin of N MI: Non-M askable Inte rrupt r equest i s a n active-hi g h, edge-trig gered i nput i s equivalent to an INTR signal of typ e 2. N o acknowledge cycles are needed to be carried o ut. PE REG and PE ACK ( Processor Extension Request and Acknowledgemen t) P rocessor ext ension r efers t o coproc essor ( i n c ase of C PU). T his p air o f p ins e xtends m emory ma nagement protectio n c apabilities o f t o p rocessor e xtension PE REQ i nput reque sts t o perform a data oper transfer 62

67 a processor ex t ension. P EACK active-l ow o utput i ndicates t o pr ocessor extension that requested operand is being transferre d. B USY ERRO R : Proce ssor e xtension B USY E RROR active-lo w i nput s ignals i ndicate o perating con ditions o f a processor ext ension to B USY g oes l ow, i ndicating t o suspe nd exe cution wa it u ntil B USY becom e i nactive. I n t his d uration, processo r ext ension i s busy i ts a llotted j ob. O nce j ob i s c ompleted p rocessor e xtension d rives B USY i nput h igh i ndicating t o co ntinue with p rogram e xecution. A n a ctive E RROR sig nal c auses t o perfor m proc essor e xtension inte rrupt w hile exe cuting WAI T E SC i nstructions. a ctive ERRO R s ignal i ndicates t o proce ssor ext ension h as c ommitted a m istake and henc e it is reactivating processor extension inte rru pt. C AP: A μ f, 12V capac itor m ust b e connec ted betwee n t his i nput p in g round t o f ilter o utput o f i nternal s ubstrate b ias gen e rator. F or c orrect o peration o f c apacitor m ust b e c harged t o i ts o perating v oltage. T ill t his c apacitor c harges t o i ts f ull capacity, may be kept stuck to reset to avoid any spurious activity. Vss: This pin is a sy stem ground pin of V c c: This pin is used to apply + 5V power supply v oltage to internal circuit of RESET active-high RESET input clears internal logic of 80286, and reinitializes it RESET active-high r eset i nput p ulse width s hould b e at l east 16 c lock cy cles r equires a t l east 38 c lock c ycles afte r t railing edg e o f RES ET i nput s ignal, before it makes first opcode fetch cycle Real Addre ss Mo de A ct a s a f ast 8086 Instruction set is upwardly c ompatible It address only 1 M byte of physical memory using A0-A19. I n r eal a ddressing m ode o f o peration o f 80286, i t ju st a cts a s a fast instruction set is upwa rd compatible with that of addresses only 1Mbytes of ph ysical memory using A0- A1 9. lines A20-A2 3 n ot u sed by interna l c ircuit o f i n t his m ode. I n r eal a ddress m ode, w hile addressing phy sical memory, use s BHE along with A0- A b it physical address is again formed in same way a s that in c ontents of segment r egisters use d a s segme nt b ase a ddresses. o r r egisters, d epending u pon a ddressing m ode, c ontain o ffset a ddresses. B ecause o f e xtra p ipelining o r c ircuit l evel i mprovements, i n r eal a ddress m ode a lso, o perates a t a m uch f aster r ate t han 8086, a lthough functionally y wor k i n a n i dentical fashion. A s i n 8086, p hysical memory i s organize d i n t erms o f s egments o f 64Kby te m aximum s ize. A n exc eption i s generate d, i f s egment s ize limi t i s exceeded by instr uction o r. o verlapping o f physic al memory s egments i s a llowed t o m inimize m emory r equirements a t ask r eserves t wo f ixed ar eas o f physica l m emory for sy stem i nitialization i nterrupt v ector t able. I n r eal m ode f irst 1 Kbyte o f m emory starting a ddress 0000H t o 003FFH i s r eserved i nterrupt v ector t able. A lso a ddresses from FFFF0H to FFFFFH are reserved for sy s tem initialization. program execution starts from FFFFH after reset and initialization. interru pt v ector t able of i s o rganized i n s ame w ay a s o f Some o f interr upt ty pes r eserved e xceptions, single-s tepping p rocessor ext ension s egment o verrun, et c W hen i s rese t, i t alway s s tarts execu tion i n r eal addr ess mo d e. I n r eal a ddress m ode, i t performs f ollowing fun c tions: i t initialize s I P o r reg isters of 80286, it prepares for entering protected vir tual address mode. 63

68 F ig 2.20 R eal Address calculation P rotected Virtual Address Mode (PVAM) i s f irst process or t o s upport c oncepts o f v irtual memory and memory manageme n t. virtua l memory d oes n ot exi st physically i t s till a ppears t o b e a vailable in s ystem. c oncept o f V M i s i mplemented u sing Phy sical memory C PU c an directly a ccess secondary memory i s u sed a s a sto rage p rogram, which are stored in secondary memory initially. S egment o f prog ram o r r equired for a ctual exe cution a t i nstant i s f etched secondary memory i nto p hysical m emory. A fter exe cution o f t his f etched s egme nt, n ext s egment r equired f urr exe cution i s again f etched secondary memor y, whil e r esults o f exe cuted segme nt store d b ack i nto secondary memory f urr r eferences. T his c ontinues t ill c omplete p rogram i s executed D uring e xecution p artial r esults of previously exe cuted portio ns ag ain f etched i nto physic al m emory, i f required f urr ex e cution. p rocedure o f f etching c hosen progra m s egments or da ta secondary stora ge i nto physi cal memory is called swapping. procedure of storing back partial results or data back o n secondary storag e is called unswapping. virtual memory i s allotted per task i s able t o add ress 1 G byte (230 b y tes) o f v irtual memory pe r t a sk. c omplete v irtual m emory i s mappe d o n t o 16Mby te phy sical memory. I f a p rogram l arger t han 16Mbyte i s s tored o n h ard d isk i s t o b e ex e cuted, i f i t i s f etched i n t erms o f o r prog ram s egments o f l ess t han 16Mby te i n size i nto progra m memory by swapping sequentially a s per sequence of execution. W henever p ortion of a progra m i s required for executio n by CP U, i t i s f etched secondary memory p laced i n physic al memory is c alled s wapping in o f p rogram. A port ion o f p rogram o r i mportant p artial r esults r equired fur r e xecution, m ay b e s aved b ack o n secondary s torage t o m ake P M f ree for furr e xecution o f a nor r equired p ortion o f p rogram i s c alled swapping o ut o f executable progra m u ses 16-b it c ontent o f a segme nt r egister a s a s elector to a ddress a d escriptor s tored i n p hysical memor y. de scriptor i s a b lock o f c ontiguous memory l ocations containing infor mation o f a segm e nt, l ike segment b ase addres s, s egment lim it, s egment t ype, p rivilege l e vel, segment availability i n phy sical memor y, de scriptor type seg m ent use anor task. 64

69 UN I T III I/O INTERFACIN G Memory Devices and Interfaci ng A ny application o f a m icroprocessor base d syste m require s transfer o f data b etween e xternal circuit ry t o microprocess or m icroprocessor t o ext ernal circuitry. M ost o f p eripheral d evices desig ned i nterfaced a C PU e ir t o e nable i t t o comm unicate u ser or a n ext ernal p rocess to e ase circ uit operations so that microprocessor works more efficiently. u se o f p eripheral i ntegrated d evices s implifies b oth h ardware circ uits softwar e considerable. following are devices used in interfacing of Memory General I/O devices 74LS138 (Decoder / Demultiplex er). 74LS373 / 74LS374 3-STATE Octal D-Ty pe Transparent L a tches. 74LS 245 Octal Bus Tran iver: 3-State. 74LS138 (Decoder / Demultiplexe r ) L S138 i s a hig h s peed 1-of-8 D ecoder/ Demultiplexe r f abricated l ow p ower S chottky b arrier d iode p rocess. d ecoder a ccepts t hree binary w eighted i nputs ( A0, A 1, A 2) w hen e nabled provide s eig ht mutually exc lusive active L OW O utputs ( O0 O 7). L S138 c an b e used a s an 8-o utput demultiplexe r by u sing o ne of a ctive L OW Ena ble i nputs a s th e i nput and o r Ena ble i nputs a s st ro bes. E nable i nputs w hich n ot use d m ust b e permanently t ied t o ir appropriate a ctive HI GH o r active LOW state. Fi g. 3.1 Pin diagram of LS373 / 74LS374 3-S TATE O ctal D-T ype T ransparent L atches Edge-Trig gered Flip-Fl ops se 8-b it registers f eature totem-p ole 3-STATE o utputs designe d specifically i mplementing b uffer r egisters, I/ O p orts, b idirectional b us d rivers, w orking r egisters. eig ht latche s o f 74L S373 transpare nt D type l atches meanin g w hile enable (G) is HIGH Q outputs will follow data (D) i nputs. 65

70 W hen ena ble i s taken L OW o utput w ill b e l atched a t leve l of data tha t was s et u p. e ight flip-f lops o f 74LS374 edge-trig gered D-type f lip f lops. O n p ositive t ransition o f c lock, Q o utputs w ill b e s et t o l ogic state s w ere se t u p at D inputs. Main Features Choice of 8 latches or 8 D-type flip-f lops in a single package 3-STATE bus-driving o utputs Full parallel-access for load ing Buffered contro l inputs P-N-P inputs reduce D-C loading on data l ines Fi g. 3.2 Connection diagram o f 74LS373 F ig 3.3 Pin of 74LS245 74LS245 Octal Bus Tran iver: 3-State 74LS245 i s a high-s peed Si-g ate C MOS d evice. 74LS245 i s an o ctal t ran ive r f eaturing non- inverting 3-s tate b us compatib le ou tputs i n b oth s end receive direct io ns. 74LS245 f eatures a n O utput E nable ( O E) i nput easy c ascading a s end/receive ( DIR) i nput for direction c ontrol. O E c ontrols o utputs s o buses effectively isolated. A ll inputs have a Schmitt-trigg er a ct ion. se o ctal b us t ran i vers desig ned async hronous two-way c ommunication between data buses. 74LS245 is a high-speed Si-g ate CMOS device. 74LS245 is a n o ctal t ran i ver f eaturing non-inverting 3-s tate b us c ompatible out puts i n b oth s end and receive direc t ions. 74LS245 featur es a n O utput E nable ( OE) i nput easy cascadin g and a s end/receive (DIR) i nput d irection c ontrol. O E c ontrols o utputs s o that b uses are effectively i solated. A ll i nputs h ave a Schmitt-trig ger a c tion. se octal b us t ran i vers are designed for asynchronous two-way c ommunication between data buses. Memory Devices And Interfaci ng m emory i nterfacing c ircuit i s u sed t o a ccess m emory q uit frequently to r ead i nstruction c odes s tored i n m emory. r ead / w rite o perations moni tored by c ontrol signa l s. S emiconductor m emories o f t wo typ e s. Viz. R AM ( Random A ccess Memor y ) and ROM (Read Only Memory) Semiconductor RAM s are broadly two types- static Ram and dynamic RAM Memory structure and its requirements r ead / w rite m emories c onsist of a n array o f r egisters i n w hich e ach register h as u nique addres s. size of memory is N * M as shown in figure. 66

71 W here N i s n umber o f r egister M i s w ord l ength, i n n umber o f b its. A s s hown i n f igure(a) memory chip ha s 12 address l ines Ao A1 1, o ne c hip sele ct ( CS ), and t wo c ontrol l ines, Read (RD) to enable output buffer and Write ( WR) to enable input buffe r. i nternal d ecoder i s u sed t o d ecoder addre ss l ines. F igure(b) s hows l ogic d iagram of a typical EPROM (Erasable Programmable Read-Only Memory ) 4096 ( 4K) r egister. It h as 12 addr ess lines Ao A 11, o ne chip select ( C S), o ne read contr ol sign a l. Since E PROM does not require ( W R) signa l. E PROM ( or E PROMs) i s u sed a s a p rogram m emory R AM ( or R AMs) a s a memory. W hen b oth, EP ROM R AM u s ed, total addre ss space 1 Mbytes i s shared by m. Address Decoding Techniques Absolute dec oding Li near decoding Block deco ding Absolute Dec o ding: I n a bsolute d ecoding t echnique memory c hip i s s elected only fo r th e s pecified log ic l evel o n a ddress l ines: n o o r l ogic l evels c an s elect c hip. B elow f igure m emory i nterface a bsolute decodin g. T wo 8 K E PROMs ( 2764) u sed t o p rovide e ven and o dd memory b a nks. C ontrol signa ls B HE Ao use to ena ble o utput o f o dd e ven memory b anks respectivel y. A s e ach m emory c hip h as 8 K m emory lo c ations, thir teen a ddress l ines required t o addre ss ea ch l ocations, independently. A ll remaining a ddress l ines use d to g enerate an u nique chi p select si gn al. T his a ddress technique i s normally used in large memory sy s tems. Fig 3.4 Linear deco ding 67

72 Linear De co ding: I n s mall sy stem h ardware d ecoding l ogic c an b e e liminated b y u sing only re quired n umber o f a ddressing lin es ( not a ll). O r l ines s imple igno r ed. Th is t echnique i s refer red a s l inear decodin g or p artial d ecoding. C ontrol s ignals BHE and Ao use d to e nable o dd e ven m emory b anks, respectivel y. F igure s hows a ddressing o f 16K R AM ( 6264) l inear decodin g. a ddress li ne A1 9 i s u sed t o select R AM chi p s. Whe n A19 i s l ow, c hip i s s elected, o rwise it is d isabled. s tatus o f A1 4 t o A1 8 does n ot a ffect c hip s election l ogic. T his g ives y ou m ultiple a ddresses ( shadow a ddresses). T his t echnique reduces c ost o f decoding c ircuit, b ut i t g as dra wback o f m ultiple addresses F ig 3.5 B lock decoding B lock Decoding: I n a m icrocomputer syste m memory array i s o ften c onsists of seve ral b locks o f memory ch ips. Each block of me mory re quires decoding circuit. To avoid separa te decoding e ach memory block special decoder IC is used to generate chip select sig n al for each block. Fi g. 3.6 Static Memory interfacing 68

73 Static Memory Interfaci ng general procedure of static memory interfacing 8086 a s follow s : 1. Arrange available m emory c hips so as to obtain 16-b it b us w idth. u pper 8-b it b ank i s c alled odd a ddress m emory b ank l ower 8-b it b ank i s c alled even a ddress memory b ank. 2. Connect available memory addre ss lines of memory chips wi th those o f m icroprocessor a lso c onnect memory RD WR i nputs t o corresponding p rocessor c ontrol s ignals. C onnect 16-b it b us o f memory bank o f microprocessor r emaining address l ines o f micropro c essor, BH E Ao u sed dec oding r equired c hip se lect si gnals fo r o dd and eve n memory b a nks. C S o f memory i s derived from output of decoding cir cu it. 4. A s a g ood efficie nt inter facing p ractice, a ddress ma p o f sy stem s hould b e continuous a s f ar as possible Dynami c RAM Interfacing b asic Dyna mic R AM c ell use s a capacitor to s tore cha rge as p resentation o f. T his capa citor is m anufactured a s a diode i s reverse-b iased so s torage c apacitance c omes into p icture. T his storag e capa citance i s utilize d storing c harge represe ntation o f b ut reverse-biase d d iode h as a l eakage c urrent t ends t o discharge capacitor giving r ise to possibility of data l oss. T o a void t his p ossible l oss, s tored i n a dyna mic R AM c ell m ust b e r efreshed a fter a f ixed t ime i nterval regularl y. p rocess o f refreshing da ta i n th e R AM i s k nown a s r efresh c ycle. T his a ctivity i s similar t o r eading e ach c ell o f memor y, i ndependent o f r equirement o f m icroprocessor, regularly. D uring t his r efresh p eriod a ll o r o perations ( accesses) r elated t o memory subsy stem are suspende d. a dvantages o f dyna mic R AM. L ike lo w p ower c onsumption, higher packaging d ensity l ow c ost, m ost o f a dvanced comp uter sy stems designe d u sing dy namic RA M s. A lso r efresh m echanism a dditional h ardware requ ired m akes i nterfacing h ardware, i n c ase o f d ynamic R AM, m ore c omplicated, a s c ompared t o s tatic RAM interfacing circ u it. Interfac ing I/O Ports I /O p orts o r i nput/output p orts d evices t hrough w hich m icroprocessor c ommunicates with or devices or external data s ources/destinations. I nput activity, as one m ay e xpect, i s activity ena bles microproce ssor t o r ead da ta ext ernal d evices, e xample k eyboard, jo y sticks, m ouser e tc. d evices are k nown a s i nput devices as y feed data into a microprocessor sy s tem. O utput a ctivity t ransfers microproc essor t op ext ernal devic e s, e xample C RT d isplay, 7-s egment displa y s, p rinter, e tc, d evices a ccept a microprocessor system are called output devic es. S teps in Interfacing an I/ O Device following steps are performed to interface a general I / O device with a CPU: 1. C onnect da ta b us o f microprocessor sy stem bus of I / O por t. 2. D erive a d evice a ddress p ulse by decoding require d addr ess of d evice use it as chip select of devic e. 3. U se a s uitable contro l signal, i.e. I ORD / or I OWR t o carry ou t d evice o perations, i. e. c onnect I ORD t o RD i nput o f th e device if i t i s an input devi s e, o rwise conne ct IOWR t o W R i nput o f d evice. I n s ome c ases R D o r WR co ntrol signa ls combi ned devic e add ress p ulse t o g enerate th e device select pulse. Input Port 69

74 i nput d evice i s conne cted t o microprocess or t hrough bu f fer. si mplest m o f a inp ut p ort i s a b uffer a s sh own i n fi g ure. T his b uffer i s a tri-s tate buffer its o utput is a vailable o nly w hen ena ble s ignal i s a ctive. W hen m icroprocessor w ants t o r ead i nput d evice ( keybo a rd), c ontrol sig nals microprocesso r a ctivates buffe r b y a sserting e nable i nput o f b uffer. O nce b uffer i s e nabled, de vice i s available on data b us. Microprocessor reads this data by initiating read comma n d. Out put Port I t i s u sed t o s end data t o o utput device suc h a s display fr om microproc e ssor. simplest form of output por t is a latc h. F ig.3.7 I /O interfacing o utput d evice i s conn ected t o micropr ocessor t hrough latc h a s show n i n figu r e. W hen m icroprocessor w ants t o se nd t o o utput d evice i t p uts o n b us a ctivates c lock si gnal o f l atch, latching da ta fr om b us at outp ut of latc h. It is n available at output of latch for output devic e. I/O Interfacing Techniques Input/output devices can be interfaced with microprocessor systems in two way s : 1. I / O mapped I/ O 2. Memory mapped I/ O 1. I/O m a pped I/O: 8086 h as s pecial instructi ons I N and OUT t o trans fer da ta through inpu t/output p orts i n I/O mapped I/ O system. IN instruction copies data from a port to Accumulator. I f an 8-b it p ort i s r ead da ta wil l g o t o A L if 16-bit p ort i s r ead wi ll g o t o A X. Th e O UT i nstruction c opies a by te AL o r a word A X t o specifie d port. M/ I O sign al i s alway s l ow w hen 8086 i s exe cuting se i nstructions. I n t his a ddress o f I / O devic e is 8-bit or 16- b it. It is 8-bit for Direct addressing and 16- bit for Indirect addressing. 2. Memory mapped I/ O I n t his ty pe o f I / O i nterfacing, 8086 use s 20 addre ss l ines t o identify an I / O d e vice. I /O d evice i s c onnected a s i f i t i s a memory devi c e u ses s ame con trol s ignals i nstructions t o a ccess I/O a s those o f memory, h ere R D and W R signa ls ac tivated indicating memory bus cy c le. 3.2 Parall el C ommunication I nterface: 8255 Program mable P eripheral Interfa ce Interfacing 8255 i s a widely u sed, prog rammable para llel I/O d evice. I t c an b e progra mmed t o t ransfer unde r da ta u nder va rious conditio n s, s imple I / O t o in terrupt I /O. I t i s f lexible, v ersatile e conomical ( when m ultiple I/O p orts ar e required ). I t i s a n i mportant g eneral purpose I/ O device that can be used with almost any m icroprocessor has 24 I / O pins that can be grouped primarily i nto two 8 bit parallel port s: A B, remain ing 8 bits a s Po rt C. 8 b its o f p ort C c an be u sed a s i ndividual b its o r b e groupe d i nto tw o 4 b it ports: C Upper ( CU) CLower (C L ). f unctions o f se ports are defined by writing a control word in contr ol registe r. 70

75 8255 c an b e u sed i n t wo m odes: B it s et/reset ( BSR) m ode I / O m ode. B SR m ode i s u sed t o s et o r r eset th e b its i n p ort C. I / O m ode i s f urr divide d i nto 3 m odes: mode 0, mode 1 and mode 2. In mode 0, all ports function as simple I / O ports. M ode 1 i s a h andshake m ode whereby P ort A and /or P ort B u se b its P ort C a s h andshake s ignals. I n handsha ke m ode, t wo ty pes o f I / O t ransfer c an b e i mplemented: s tatus c heck inter r upt. I n m ode 2, P ort A c an be s et up bidirec tional transfer using handsh ake signa ls P ort C, P ort B c an be s et u p e ir i n m ode 0 or mode 1. Fi g Pins of 8255 F ig.3. 9 B lock diagram o f 8255 R D: ( Re a d) : Th is signal enables Rea d ope rat ion. When signal microprocessor reads data from a selected I / O port of W R: ( Write ): This control signal enables write oper at ion. R ESET ( Rese t) : It clears control reg isters and sets all ports in input m o de. CS, A 0, A 1: se are device select signal s. is connected to a decoded addre ss an d A0, A1 are connected to A0, A1 of microprocessor. i s l ow, Fig 3.10 Control wordforma t of

76 B SR Mode of 8255: Fi g B SR mode of 8255 I/O Modes of 8255 Mode 0: Simple Input or Outp ut I n t his m ode, P ort A P ort B u sed a s t wo s imple 8-b it I / O p orts and P ort C a s two4- b it I / O p orts. E ach p ort ( or half- p ort, i n c ase o f P ort C ) c an b e p rogrammed t o f unction a s s imply a n i nput p ort o r a n o utput p ort. i nput/output f eatures i n m ode 0 are: O utputs latched, Inputs are not latched. P orts do not have handshake or interrupt capabilit y. Mode 1: Input or Output with handsh ake I n m ode 1, hshake s ignals exc hanged betw een micropr ocessor periphe rals p rior t o t ransfer. p orts ( A B ) f unction a s 8-b it I / O po r ts. y c an b e c onfigured e ir a s input o r o utput port s. E ach p ort ( Port A P ort B ) u ses 3 l ines p ort C a s handshak e s ignals. rema ining t wo l ines o f p ort C c an be use d simple I / O functions. I nput and output data are latched and Interrupt logic is supporte d. Mode 1: Input contro l signals F ig.3.12 m ode 1 input control signals 72

77 S TB S trobe Inp ut) : T his s ignal (ac tive l ow) i s generate d by a p eripheral d evice i t h as transmitted a byte of dat a. 8255, in response to, generates IBF and INTR. I BF ( I nput b uffer full): T his sig nal i s a n a cknowledgement by 8255 t o i ndicate input latch has received data byt e. This is reset when microprocessor reads data. I NTR ( Interrupt Re quest): T his i s a n o utput s ignal may be used t o i nterrupt microprocessor. T his signal is generated if, I BF and INTE are all at log i c 1. I NTE ( Interrupt E nable): T his i s a n i nternal flip-f lop t o a p ort n eeds t o b e s et t o g enerate I NTR si g nal. t wo flip-f lops I NTEA INTEB set / reset u sing B SR m ode. I NTEA i s e nabled o r d isabled t hrough P C4, INTEB i s e nabled o r disabled throug h PC2. ( a) input operati on ( b) output opera tion Fig.3.13 Timing waveform for mo de1 operation ( Output B uffer F ull): T his i s a n o utput signa l g oes l ow w hen microproc essor w rites i nto o utput l atch o f T his s ignal i ndicates t o an o utput p eripheral new data is ready t o b e r ead. I t g oes high again after 8255 r eceives a signa l periphera l. ( Acknow l edge) : T his i s a n i nput s ignal a periphera l m ust o utput a l ow w hen peripheral receives data from 8255 ports. I NTR ( Interrupt Re quest): T his i s a n o utput s ignal, i t i s s et by ri sing edg e of th e signa l. T his sig nal c an be u sed t o i nterrupt mi croprocessor t o reque st next data byte for o utput. INTR is set and INTE are all one and reset by rising e dge of.. I NTE ( Interrupt E nable): T his i s a n i nternal flip-f lop t o a p ort n eeds t o b e s et t o g enerate I NTR si g nal. t wo flip-f lops I NTEA INTEB set / reset u sing B SR m ode. I NTEA s ignal c an b e enabled o r d isabled throug h P C6, INTEB i s enabled or disabled throug h PC2. Mode 2: Bidirectional Data Transfer OB F T his m ode i s used primarily i n applications s uch a s data transfe r b etween t wo c omputers o r floppy d isk c ontroller i nterface. Port A c an b e configur ed a s b idirectional p ort P ort B e ir in m ode 0 o r m ode 1. P ort A u ses f ive signals P ort C a s h andshake s ignals da ta t ransfer. remaini ng t hree l ines Port C c an b e u sed eir as simple I/ O or as handshake sig nals for Port B. 73

78 Fi g M ode 2 Control Signals 3.3 Serial Commu nication: Using i s a U niversal Synchr onous and Asy nchronous Receive r T ransmitter c ompatible I ntel s p rocessors. T his c hip c onverts p arallel i nto a s erial stream o f b its s uitable for serial transm is sion. It i s a lso a ble t o re ceive a seria l st ream o f bits c onvert it into parallel data bytes to be read by a microproc e ssor Basic Modes of data transmi ssion a) Simplex b) Duplex c) Half Duplex a) Sim plex mo de Data is transmitted only in one direction over a singl e communication channel. F or e xample, processor may transmit data for a CRT display u nit in this mode. b) Duple x Mo de I n d uplex m ode, m ay be transferre d betw een t wo transreceivers i n b oth d irections simultaneously. c ) Half Duplex mo de I n t his m ode, transm ission m ay t ake p lace i n e ir d irection, b ut a t a t ime may b e t ransmitted o nly i n o ne d irection. A c omputer m ay c ommunicate a t erminal i n t his mode. I t i s n ot p ossible t o t ransmit compute r t o t erminal t erminal t o computer simultaneously. 74

79 Fi g Serial commun ication interface 8251 b uffer i nterfaces interna l b us o f circ uit th e system b us. read / w rite c ontrol logic c ontrols o peration o f per ipheral depending upo n op erations i nitiated by C PU dec ides whe r address o n internal b us is c ontrol a ddress / a ddress. m odem c ontrol u nit h andles m odem h andshake sig nals t o coordinate communication between mode m an d USA RT. t ransmit c ontrol unit t ransmits da ta by te re ceived by data buffer C PU s erial c ommunication. t ransmission r ate i s contr olled by i nput frequenc y. T ransmit c ontrol u nit al so d erives two transmit ter s tatus signa ls namely TXRDY TXEMPTY which may be used by CPU for handshaking. t ransmit b uffer i s a p arallel t o s erial converte r rece ives a parallel byte c onversion i nto a seria l s ignal for f urr transmis s ion. r eceive control u nit d ecides r eceiver frequency a s c ontrolled b y R XC i nput frequenc y. r eceive control u nit generate s a r eceiver r eady ( RXRDY) sig nal m ay be used by C PU handshakin g. T his u nit a lso d etects a b reak i n string wh ile 8251 i s i n asy nchronous m ode. I n synchronous mode, 8251 detects SYNC characters using S YNDET/BD pin Signal Description o f 8251 D0 D 7 : T his i s a n 8-b it b us u sed t o r ead o r w rite s tatus, c ommand w ord o r or to 8251A. C / D : ( Control W ord/data) : T his i nput pi n, tog er R D W R i nputs, i nforms th e 8251A w ord on b us i s eir a data or c ontrol w ord/ status i nformation. If this pin is 1, control / status is on bus, orwise data is on b us. R D: T his active-l ow i nput t o 8251A i s use d t o i nform i t C PU i s reading e ir da ta o r s tatus i nformation i ts i nternal r egisters. T his active-l ow i nput t o 8251A i s u sed t o i nform it that CPU is writing data or control word to 8251A. W R: T his i s a n active-l ow c hip s elect i nput o f 825lA. I f i t i s h igh, n o r ead o r w rite operation can be carried out on data bus is tristated if t his pin is hig h. 75

80 C LK: T his i nput i s u sed t o g enerate i nternal devi ce t imings i s normally c onnected t o c lock g enerator o utput. T his i nput frequency sho uld b e a t l east 30 t imes gre ater tha n receiver or transmitter data bit transf er rate. RESE T: A high o n t his i nput force s 8251A i nto a n i dle s tate. de vice w ill r emain i dle t ill t his in put s ignal a gain goe s l ow a new s et o f c ontrol w ord i s w ritten i nto i t. minimum required reset pulse width is 6 clock states, for prope r reset ope rat ion. TXC (Transm itter Clock Input) : This transmitter clock input controls rate at which c haracter i s t o be transm i tted. s erial data i s shif ted o ut o n successiv e neg ative edg e of T XC. T XD ( Transmitted D ata Out put): T his o utput p in c arries seria l s tream o f t ransmitted bits along with or information like start bit, stop bits and parity b it, etc. R XC ( Receiver C lock I nput) : T his r eceiver cloc k i nput p in c ontrols r ate a t w hich characte r is to be re c eived. R XD ( Receive D ata I nput) : T his i nput p in o f 8251A r eceives a compos ite s tream o f data to be received by 8251 A. R XRDY (Re ceiver Re ady O utput): T his o utput i ndicates 8251A contain s a character to be read by CPU. T XRDY - Transm itter Read y: T his o utput s ignal i ndicates t o C PU i nternal circuit of transmitter is ready t o accept a new cha racter for transmission from CPU. D SR - Dat a Set Read y : T his i s n ormally use d t o check i f da ta set i s ready whe n communicating with a mode m. D TR - D ata Terminal Ready: T his i s u sed t o i ndicate d evice is ready t o ac cept data when 8251 is communicating a mode m. RTS - Request to Send Dat a: This sig n al is used to communicate with a modem. TXE- T ransmitter Empty: T XE s ignal can b e use d t o indica te e nd of a transmission mode Operating Modes of Asyn chronous mode 2. Synchro nous mode Asynchronous Mode ( Transm i ssion) W hen a character i s s ent t o 8251A by C P U, i t a dds start b its prior to th e serial b its, f ollowed by o ptional p arity b it s top b its u sing async hronous m ode i nstruction c ontrol w ord form a t. T his s equence i s n transm itted u sing T XD o utput p in o n falling edge of TX C. Asynchr onous Mode ( Re cei ve) A f alling edg e o n R XD i nput l ine m arks a s tart b it. r eceiver r equires only one s top b it t o m ark e nd o f b it s tring, r egardless o f s top b it p rogrammed a t transmitting en d. 8- b it character is n loaded into into parallel I/O buffer of R XRDY p in i s r aised h igh t o i ndicate t o C PU a c haracter i s ready i t. If p revious cha racter ha s n ot b een re ad by C PU, n ew chara cter r eplaces i t, th e overrun flag is set indicating that pre vious characte r is lost. 76

81 Fig.3.16 Mode instruction format-async. Fi g communication forma t Fi g Synchronous mode Instruction forma t 77

82 Synchronous Mode (Transm i ssion) T XD o utput i s h igh u ntil C PU s ends a characte r t o 8251 w hich usually i s a SY NC characte r. W hen C TS l ine g oes l ow, f irst c haracter i s serially t ransmitted o ut. Characters s hifted o ut o n f alling edg e o f T XC. Data i s s hifted o ut a t s ame r ate a s T XC, over T XD o utput l ine. I f C PU buffer b ecomes empt y, S YNC character o r character s ar e inserted in data stream ove r T XD output. Synchronous Mode (Receive r ) I n t his m ode, c haracter sy nchronization c an b e achie ved internally or externall y. Th e on RXD p in is s ampled o n r ising e dge o f R X C. c ontent of receiver buffe r i s c ompared f irst S YNC characte r a t every edg e u ntil i t m atches. I f 8251 i s p rogrammed t wo S YNC c haracters, subseq uent receive d c haracter i s a lso c hecked. W hen characte rs m a tch, hunting s tops. SYNDET p in s et h igh and i s rese t a utomatically by a s tatus r ead o peration. I n e xternal S YNC m ode, synchr onization i s a chieved by applying a hi gh leve l o n SYNDET i nput p in ces 8251 o ut o f H UNT mode. hig h l evel c an b e re moved a fter one R XC cycl e. parity o verrun error both are checked in same way as in asy n chronous mode. F ig.3.19 D ata Formats of Synchronous Mode Command Instruction Definiti on c ommand i nstruction c ontrols a ctual o perations o f se lected mat l ike e nable t ransmit/receive, e rror re set and m odem cont r ol. A r eset ope ration retur ns 8251 bac k t o mode instruction forma t. 78

83 Status Read Definiti on T his d efinition i s u sed b y C PU t o rea d sta tus o f acti ve 8251 to c onfirm i f any e rror c ondition o r o r c onditions l ike requ irement o f proce ssor service has be en detected during ope r ation. Fi g Status information 3.4 D/A A nd A/ D Interfac e : f unction o f a n A / D c onverter i s t o p roduce a d igital w ord whic h repre sents magnitude of some analog voltag e or curr en t. specifications for an A/D converter are very similar to those for D/A converte r: resolutio n of a n A/D c onverter r efers t o n umber of b its i n output binary word. An 8- bit converter for example has solution of 1 pa r t in 256. Accuracy linearity sp ecifications ha ve s ame meaning for a n A / D c onverter as y do for a D/A converte r. A nor important specifi cation a n A DC i s i ts c onversion t ime. - t ime i t t akes c onverter t o produc e a v alid o utput binary c ode a n a pplied input v oltage. When we refer to a converter as hig h speed, it has a short conversion time. 79

84 analog to digital converter is treat ed as an inp ut device by microprocessor tha t sends an initialising signal to ADC to start analog to digital data conversation proc es s. s tart of conve rsion signal i s a pulse of a specifi c duration. proc ess o f analog t o d igital c onversion i s a s low p rocess, microprocessor h as t o w ait d igital data till conversion is ove r. A fter conver sion i s o ver, A DC s ends e nd o f conversi on ( EOC) s ignal t o i nform microprocesso r c onversion i s o ver r esult i s ready a t outp ut buffe r of AD C. se t asks of i ssuing a n S OC p ulse t o A DC, reading EO C signa l fro m ADC r eading dig ital output o f ADC are carrie d o ut by C PU using 8255 I/O port s. Th e time taken by ADC from active edge of SOC pulse ( edge at which conversion process actually starts) till active edge of E OC s ignal i s c alled a s th e conver sion delay o f ADC- t ime t aken by c onverter t o c alculate e quivalent d igital o utput from i nstant o f th e s tart o f c onversion i s c alled c onversion delay. I t may r ange any where a f ew m icroseconds i n c ase o f f ast ADCs to even a few hundred millisec onds in case of slow A D Cs. A n umber o f A DCs are a vailable i n mark e t, s election o f A DC a particul ar a pplication i s d one, k eeping i n m ind require d s peed, r esolution rang e of o peration, p ower supply r equirements, s ample h old d evice requir ements and c ost fac tors considere d. a vailable AD Cs i n m arket u se d ifferent c onversion techni ques conversion of analog signals to digital signa l s. Parallel converter or flash converter, Successive approximatio n an d dual slope integrat ion A general algorithm for ADC interfacing contains following ste p s. 1. Ensure stability of analog input, applied to A D C. 2. Is sue start of conversion (SOC) pulse to A D C. 3. Read end of conversion (EOC) signal to mark end of conversion proc es s. 4. Read digi tal data output of ADC a s equivalent digita l output. I t may b e n oted tha t a nalog i nput v oltage m ust be c onstant a t i nput o f ADC rig ht s tart o f conver sion t ill e nd o f c onversion t o g et correc t res u lts. T his m ay b e ensured by a sample an d hold circuit which samples analog signal and holds it constant for a specified time dur at ion. microproc essor may i ssue a h old sig nal t o th e s ample and H old cir cu it. I f a pplied i nput chang es b efore c omplete conve rsion p rocess i s ov e r, d igital equivale nt o f analog i nput calcul ated by A DC may no t b e correct. I f applie d i nput chang es b efore complete conv ersion p rocess i s ove r, d igital e quivalent of analog i nput calculated by ADC may n ot be correct. ADC 0808/ 0809 ana log t o dig ital c onverter c hips are 8-bi t CMOS, succes sive a pproximation c onverters. S uccessive approxi mation t echnique i s one of f ast techniq ues a nalog t o d igital c onversion. c onversion d elay i s 100 μ s a t a c lock frequency of 640 khz, which is quite low as compared to or converte rs. se c onverters d o n ot n eed any e xternal ze ro or f ull s cale a djustments a s y a lready t aken c are o f b y interna l c ircuits. se converte rs internally h ave a 3 : 8 analog multiplexe r so a t a tim e eig ht differ ent ana log i nputs c an b e connecte d t o c hips. Out o f se eig ht i nputs only o ne can b e selected c onversion by using a ddress l ines A DD A, A DD B A DD C, a s s hown. U sing se a ddress i nputs, m ultichannel acquisitio n systems can be designed using a single AD C. 80

85 C PU m ay d rive se l ines usi ng o utput p ort l ines i n c ase o f m ultichannel applic at ions. I n c ase o f s ingle i nput applications, se may b e h ard wir ed t o s elect p roper i nput. Fi g P ins of ADC0808/09 Fig.3.22 Block Diagram o f ADC 0808/0809 only p ositive a nalog i nput v oltages t o ir digita l e quivalents. se chip s d o n ot conta in a ny interna l s ample and h old c ircuit. I f o ne n eeds a s ample h old c ircuit c onversion of fast, signals into equivalent digital q uantities, it h as to b e externally c onnected at each of analog i nputs. Fig.3.23 Timing Diagram of A DC 0808/0809 Fig Pins of DAC 0800 INTERFACING DIGITAL TO ANALOG O NVERTERS: d igital t o analog c onverters conve rt b inary n umbers i nto ir a nalog equiva lent voltages or curren ts. S everal techniques are employed for digital to a nalog conversion. i. Weig hted resistor net work i i. R-2R ladde r netwo rk iii. Curre nt output D/A converter 81

86 Applications in areas like digitally c ontrolled gai n s, m otor s peed c ontrol, p rogrammable g ain a mplifiers, digital voltmeters, panel mete rs, etc. I n a c ompact d isk a udio p layer exa mple a 14-or16-b it D / A c onverter is u sed t o convert binary datad off disk by a laser to an analog audio signal. Most speech syn sizer integrated circuits contain a D/A converter to convert stored binary data words into analog audio signa l s. Characteristic s : 1. R esolution: I t i s a c hange i n a nalog o utput o ne L SB c hange i n digit al i nput. I t is given by ( 1/2n )*Vref. I f n=8 ( i.e. 8- b it DAC) 1 /256* 5V= 39.06mV 2. S ettling t ime: I t i s t ime r equired for DA C t o s ettle for a f ull scale c ode change. DAC bit Digital to Analog converte r Featur es : i. DAC0800 is a monolithic 8-bit DAC manufactured by National semiconduc t or. i i. It has settling time aro und 100ms iii. I t c an operate o n a r ange o f p ower supply v oltage i.e. 4.5V t o + 18V. Us ually supply V + is 5 V o r + 12V. V- pi n c an be ke pt a t a minimum o f - 12V. i v. Resolution of D AC is 39.06mV 3.5 Programmable timer device 8253 Int el s programmable c ounter/timer d evice ( 8253) f acilitates g eneration o f a ccurate t ime dela y s. W hen 8253 i s u sed a s t iming delay g eneration p eripheral, microprocessor becomes f ree fro m t asks r elated t o counti ng p rocess exe cute p rograms i n memor y, w hile t imer d evice may p erform c ounting t asks. T his m inimizes softwar e o verhead o n microprocessor. Architecture and Signal Descri ptions prog rammable timer device 8253 c ontains thre e indepe ndent 16-b it co u nters, e ach a m aximum c ount r ate o f 2. 6 M Hz t o gener ate t hree totally indepe ndent delays o r m aintain t hree i ndependent c ounters simultaneousl y. A ll t hree c ounters may b e independently controlled by programming three internal command word registers. 8- b it, bidirect ional data buffe r interface s internal circu it of 8253 t o m icroprocessor systems b us. D ata i s t ransmitted o r r eceived by b uffer u pon th e e xecution o f I N o r OUT instructi o n. r ead/write l ogic c ontrols d irection o f b uffer depending u pon w her i t i s a r ead o r a w rite oper a tion. I t may b e n oted I N i nstruction reads data while OUT instruction writes data to a periphe ral.. 82

87 Fig 3.25 I nternal blocks of 8253 pin diagram t hree c ounters a ll 16-b it p resettable, d own c ounters, a ble t o operate e ir i n B CD o r i n hexa decimal m ode. m ode c ontrol w ord r egister c ontains i nformation c an b e u sed w riting or reading c ount v alue into o r r espective cou nt r egister u sing OU T IN i n structions. s pecialty o f 8253 counter s is y c an be easily r ead o n l ine withou t d isturbing c lock inp ut to th e count e r. This facility is c alled a s " on fly" reading of counters, and is invoked using a mode control word. A 0, A l p ins a ddress i nput p ins r equired internally for addr essing m ode c ontrol w ord regist ers thre e c ounter r egisters. A l ow o n C S l ine e nables th e N o operation will be performed by 8253 till it is enable d. Table 3.1 selected operations for various Contro l A c ontrol w ord register acce pts 8-b it control w ord w ritten by mic roprocessor s tores i t c ontrolling c omplete o peration o f s pecific c ounter. I t m ay b e n oted, c ontrol wor d reg ister c an only b e w ritten and c annot b e r ead as i t i s obv ious T able. C L K, GA TE and O UT p ins a vailable e ach of three t imer ch a nnels. ir functions will be clear when we study different operating modes of Control Word Registe r 8253 c an o perate i n anyone of six differen t m odes. A c ontrol w ord m ust b e w ritten i n r espective c ontrol w ord r egister b y microprocessor t o i nitialize e ach o f c ounters o f 8253 t o decid e i ts operating m ode. A ll c ounters c an operate i n any one of modes or y may b e even in different modes of operation, at a time. c ontrol w ord mat i s p resented, a long d efinition o f e ach b it, w hile w riting a c ount in c ounter, i t s hould b e n oted, coun t i s w ritten i n count er only after th e 83

88 i s p ut o n data b us a falling edg e appears a t clock pin o f peripher al reafte r. Any r eading o peration o f c ounter, b efore falli ng edg e ap pears may r esult in garbag e data. Fi g C ontrol word format and bit definition M ODE 0 T his m ode o f o peration i s c alled a s in terrupt o n termin al cou n t. I n t his m ode, o utput i s initially l ow a fter m ode i s s et. o utput r emains l ow e ven after c ount v alue i s l oaded i n c ounter. c ounter s tarts decrementing c ount v alue a fter f alling edg e o f c lock, i f G ATE input i s h igh. p rocess o f decreme nting c ounter c ontinues a t e ach f alling edg e o f c lock t ill t erminal c ount i s reach e d, i.e. c ount b ecomes z ero. Whe n t erminal c ount i s reach e d, o utput goe s h igh r emains h igh t ill s elected c ontrol w ord r egister o r corresponding c ount register i s reloaded with a new mode of operation or a new count, respectively. T his h igh o utput m ay b e u sed t o i nterrupt p rocessor whene ver r equired, by s etting s uitable t erminal c ount. W riting a c ount r egister w hile previou s c ounting i s i n process, generates following sequence of response. f irst byte o f new c ount w hen loa ded i n c ount r egister, s tops p revious count. second byte w hen w ritten, s tarts n ew c ount, terminating th e previous c ount 84

89 ROCONTR OLLER n re. G ATE s ignal i s a ctive high s hould b e h igh n ormal c ounting. W hen G ATE g oes l ow c ounting i s te rminated c urrent c ount i s l atched t ill G ATE again goes hig h. Fig Waveforms WR, OUT and GATE in Mode 0 M ODE 1 T his m ode o f o peration o f 8253 i s c alled a s progra mmable one-s hot m ode can b e use d a s a m onostable multivibrat or. dur ation o f qu asistable sta te o f monstable multivibrator is decided by count loaded in count register. g ate i nput i s u sed a s t rigger i nput i n t his m ode o f o peration. N ormally o utput r emains hig h t ill s uitable count i s l oaded i n c ount register a trigger i s applie d. A fter a pplication o f a trig ger ( on p ositive edge), outp ut g oes low r emains l ow t ill c ount b ecomes z ero. I f anor c ount i s l oaded w hen o utput i s already l ow, i t does n ot distur b previous coun t t ill a n ew trigger puls e i s applied a t G ATE i nput. new counting starts after new trigger pulse. Fig W R, GATE and OUT Waveforms in Mode 1 85

90 M ODE 2 T his m ode i s c alled e ir ra te generato r o r d ivide by N count e r. I n t his m ode, i f N i s l oaded a s c ount v a lue, n, a fter N p ulses, o utput become s l ow only one clock cycle. c ount N i s reloaded and a gain o utput b ecomes h igh rema ins hig h N clock pulse s. o utput i s normally h igh a fter initia lisation o r e ven a l ow signa l o n GA TE i nput c an for ce o utput h igh. I f G ATE g oes hi g h, th e c ounter s tarts counting down from initial value. counte r generates a n a ctive low p ulse a t o utput initiall y, af ter c ount r egister i s l oaded a c ount v alue. n c ount d own s tarts whene ver c ount becomes zero anor active low pulse is genera ted at o utput. d uration o f se a ctive l ow p ulses e qual t o o ne c lock cycl e. n umber o f i nput c lock p ulses b etween t wo l ow p ulses a t o utput i s e qual t o c ount l oaded. Fi gure show s r elated w aveforms for m ode 2. Interestingl y, c ounting i s i nhibited when GATE become s low. Fi g Wavefor ms at pin WR and OUT in Mode 2 M ODE 3 In t his m ode, 8253 ca n be used as a square wave ra te gene rator. In t erms o f op eration t his m ode i s s omewhat s imilar t o m ode 2. W hen, c ount N l oaded i s e ven, n h alf o f th e c ount, o utput r emains h igh remaining half it remains low. If c ount l oaded i s o d d, fir st clock p ulse decreme nts i t by 1 resulting i n a n e ven count value (holding output high). n output remains high half of new count and goes low for remaining h alf. T his procedure is repeated continuously r esulting in generation of a square wave. I n c ase o f o dd c ount, o utput i s h igh l onger d uration l ow fo r s horter duration. d ifference o f o ne c lock cy cle dura tion b etween t wo perio ds i s d ue t o i nitial d ecrementing o f o dd c ount. w aveforms m ode 3 s hown i n F ig. i f l oaded count v alue 'N i s o dd, n for ( N +l)/ 2 puls es o utput r emains hig h (N-l)/ 2 pulse s it remains low. M ODE 4 T his m ode of o peration of 8253 i s name d a s software triggere d st r obe. A fter m ode i s s et, o utput goe s hi g h. W hen a c ount i s load e d, coun ting d own start s. On terminal count, output goes low for one clock c ycle, and n it again goes high. Th is l ow p ulse can b e used a s a strob e, w hile interfacing microproces sor o r periphera l s. c ount i s i nhibited an d count v alue is l atched, when GATE signal goe s l ow. I f a n ew count i s l oaded i n c ount reg ister w hile pr evious c ounting i s in next clock cyc le. counting n proceeds according t o new count. M ODE 5 T his m ode o f o peration a lso gener ates a s trobe i n r esponse t o th e r ising edg e a t t rigger i nput. T his m ode m ay be u sed t o generate a delay ed s trobe i n r esponse t o a n e xternally g enerated s ignal. O nce t his m ode i s p rogrammed coun ter i s l oaded, output goes hig h. c ounter s tarts counti ng after rising edge o f trigger i nput ( GATE). o utput g oes low one c lock p eriod, w hen t erminal c ount i s reached. o utput w ill n ot g o l ow u ntil coun ter c ontent b ecomes zero a fter r ising edg e o f any t r igger. 86

91 G ATE i nput i n t his mode i s used a s trig ger i nput. r elated w aveforms s hown i n Fi g Programming and Interfaci ng 8253 re may be two ty p es of write operations in 8253, viz. ( i) writing a control word into a control word regi ster an d ( ii) writing a c ount value into a count registe r. c ontrol w ord r egister a ccepts b uffer initialize s c ounters, a s require d. c ontrol wor d reg ister c ontents us ed ( a) i nitialising operating m odes ( mode0- m ode4) ( b) s election o f c ounters ( counter0- c ounter2) ( c) c hoosing binary B CD counters (d) loading of counter registe rs. mode c ontrol registe r is a w rite only re gister C PU cannot r ead i ts c ontents. One c an directly w rite m ode c ontrol word cou nter 2 o r c ounter 1 prio r t o writin g c ontrol w ord counter 0. M ode c ontrol w ord r egister h as a separa te addr e ss, s o i t c an b e w ritten independentl y. A count register m ust b e loaded count v alue s ame b yte s equence was pr ogrammed i n m ode c ontrol w ord o f c ounter, u sing b its RL0 and RL 1. loading o f c ount r egisters o f d ifferent c ounters i s again s equence independe n t. O ne c an directly w rite 16-b it c ount r egister count 2 befor e wr iting c ount 0 an d count 1, but t wo byte s i n a coun t m ust b e wr itten i n byte sequenc e p rogrammed u sing RL 0 R L1 b its o f m ode c ontrol w ord o f c ounter. A ll counters in 8253 are down counters, hence ir count value s go on d ecrementing i f CL K input p in i s a pplied a v alid c lock sig nal. A maxi mum c ount is o btained by loading a ll z eros i nto a c ount r eg ister, i.e. 216 for binary count ing and 104 for B CD counting responds to negative clock edg e of clock input. m aximum operating c lock frequency o f 8253 i s 2. 6 M Hz. F or h igher frequenc ies o ne c an use t imer 8254, w hich op erates u p t o 10 M Hz, maintain ing p in c ompatibility f ollowing T able 6. 2 s hows s election o f d ifferent m ode control words and counter register bytes depending upon address lines Ao and A1 In 8253, 16-b it conte nts o f counter c an simply b e read u sing successive 8-b it I N opera t ions. A s s tated e arlier, m ode control r egister c annot b e read any of counters. re are two methods for read ing 8253 counter reg i sters. I n f irst m ethod, eir c lock o r c ounting proce dure ( using GA T E) i s i nhibited t o e nsure a s table c ount. n c ontents r ead b y s electing s uitable c ounter u sing A 0, A l e xecuting u sing IN i nstructions. first I N i nstruction rea ds l east sig nificant b yte s econd I N i nstruction r eads most s ignificant by te. I nternal l ogic o f 8253 i s d esigned i n s uch a way p rogrammer h as t o c omplete readi ng opera tion a s programmed by him, using RL0 and RL l bits of control word. I n second m ethod o f reading a c ounter, cou nter can b e re ad while co unting i s i n p rogress. T his m ethod, a s already mentioned i s c alled a s r eading o n fly. I n t his m ethod, n eir clock n or cou nting n eeds t o b e inhibi ted t o r ead counter. c ontent of a c ounter c an b e r ead ' on fl y ' using a newly define d c ontrol wor d register mat for o nline r eading o f c ount r egister. W riting a s uitable c ontrol w ord, i n m ode c ontrol r egister internally latches contents of counte r. control word mat for ' read on fl y ' mo de i s g iven i n Fi g a long i ts bit de f initions. After latching content of a count er us ing this method, p rogrammer c an read it using IN instru c tions, as discussed befor e Programmable Keyboar d/display Controller I ntel s 8279 i s a genera l p urpose Key board Display c ontroller simultaneously d rives display of a sy stem i nterfaces a Key board C PU. K eyboard D isplay i nterface s cans Key board t o identify i f any key h as be en press ed s ends c ode o f p ressed key to C PU. I t a lso transm its r eceived fro m C PU, t o display device. 87

92 B oth o f se f unctions ar e permed by th e contr oller i n r epetitive fa shion out i nvolving C PU. Keyboard i s interfaced eir i n i nterrupt o r p olled m ode. In i nterrupt m ode, p rocessor i s re quested s ervice only i f any key i s p r essed, o rwise CPU can proceed with its main ta s k. I n p olled mod e, C PU periodically r eads a n i nternal f lag o f 8279 to c heck for a key p ressure. Key board s ection c an interfac e a n array of a maxi mum o f 64 k eys C PU. Key board e ntries ( key c odes) debounced s tored in a n 8-byte F IFO R AM, i s f urr accessed by C PU to r ead key c odes. I f m ore t han e ight c haracters e ntered in F IFO ( i.e. m ore that e ight key s p ressed), b efore any FI FO r ead o peration, overru n s tatus i s s et. I f a F IFO c ontains a v alid k ey e ntry, C PU i s interrupted (in interrupt mode) or CPU checks status (in polling) to read entry. O nce C PU r eads a k ey entr y, FI FO i s u pdated, i.e. k ey entry i s p ushed o ut o f F IFO t o g enerate s pace n ew e ntries normally pr ovides a maxi mum o f s ixteen 7-s eg display inter face C PU I t c ontains a 16-byte display R AM ca n b e u sed e ir a s a n i ntegrated block o f 16x8-b its o r t wo 16x4-b it b lock o f R A M. entry t o RA M b lock is controlled by CPU using command words of Architecture and Signal Descri ptions of 8279 Keyboard display c ontroller chip 8279 provides 1. A set of four scan lines and eight return lines for interfacing keyboar d s. 2. A set of eight output lines for interfacing display. I/O Control and Dat a Buffer I / O control s ection c ontrols flow of data t o/from data buffe r i nterface ext ernal b us o f sy stem i nternal b us of 8279 I/ O s ection i s en abled only i f D i s l ow. Fi g Internal block s of K eyboard display co ntroller p in Ao, RD and WR select command, status or data d/ write opera tions carried out by CPU with Control and Timing Register and Tim ing Contro l se r egisters s tore key board and d isplay m odes o r o perating c onditions p rogrammed by C PU. Th e r egisters w ritten Ao= 1 WR = 0. t iming c ontrol u nit c ontrols b asic t imings for ope ration o f ci r cuit. S can Co unter d ivide down operating frequency of 8279 to derive scan keyboard and scan display f requencies. Scan Counter 88

93 Scan C ounter has tw o m odes t o s can ke y matrix refre sh displa y. I n E ncoded m ode, c ounter p rovides a b inary c ount i s t o b e externally decode d t o p rovide s can l ines keyboard display ( four externally d ecoded s can l ines may d rive u p t o 16 d isplays). I n d ecoded s can m ode, c ounter internally d ecodes l east s ignificant 2 b its p rovides a decode d 1 o ut o f 4 s can o n SL0-SL3 ( four internally de coded s can l ines may d rive u p t o 4 D isplays). Key board Displa y b oth are i n same mode a t a time. Return Buffers and Ke yboard Debounce and Contro l T his s ection s cans a Key c losure row- w ise. I f i t i s d etected, Keyboa rd d ebounce u nit deboun ces key e ntry ( i. e. w ait for 10 m s). A fter de bounce p e riod, i f key c ontinues t o b e detected. c ode o f Key is directly transferr ed to s ensor R AM along with SHIFT and CONTROL key s tatus. FIFO /Sensor RAM and Status Logic I n Key board o r s trobed in put m ode, t his b lock a cts a s 8-by te first-in-first-o ut ( FIFO) R AM. E ach key c ode o f pres sed k ey i s e ntered i n o rder o f entr y, i n m eantime, r ead by C PU, t ill R AM b ecomes empt y. s tatus l ogic g enerates a n i nterrupt request after each FIFO read operation till FI FO is empty. I n s canned se nsor matrix m ode, t his u nit a cts a s s ensor R AM. E ach r ow of s ensor R AM i s l oaded s tatus o f corresponding r ow o f s ensors i n matrix. I f a s ensor c hanges its state, IRQ line goes hig h to interrupt CPU. Display Address Registers and Display RAM. D isplay a ddress regis ters h old a ddresses o f w ord currently bein g w ritten o r r ead b y C PU t o o r display R AM. c ontents o f re gisters automatically u pdated b y 8279 t o accep t next entry by C PU. 16-b yte d isplay R AM c ontains 16-byte of data to be displayed on sixteen 7-seg display s in encoded scan mode. Pin Diagram o f 8279 DB0 - D B 7: se bidire ctional da ta bu s l ines. data an d c ommand words t o an d C PU are transferred on se line s. CLK: This is a clock input used to generate internal timings required by

94 Fi g pins and signals of keyboard controller RESET: T his p in i s u sed t o r eset A h igh o n t his l ine r esets A fter rese tting 8279, its i n s ixteen 8-b it d isplay, l eft e ntry e ncoded s can, 2-key l ock o ut m ode. c lock prescale r i s se t to 31. CS chip sele ct: A l ow o n t his l ine enable s 8279 for normal read o r wr ite ope r ations. O rwise t his p in should be hig h. A o: A h igh o n Ao l ine ind icates transfer o f a c ommand o r sta tus informati o n. A l ow o n t his l ine i ndicates tr ansfer o f d a ta. T his i s u sed t o s elect o ne of i nternal regis ters o f RD, WR: ( Input/Output) READ/ WRI TE i nput p ins ena ble th e buffer t o r eceive o r s end ove r data b us. I RQ: T his i nterrupt o utput l ine goe s h igh w hen re i s i n F IFO sen sor R A M. i nterrupt l ine g oes l ow each FIFO R AM rea d oper a tion. H owever, i f F IFO RA M f urr c ontains any Key-c ode entry t o b e read b y C PU, t his p in a gain goe s hig h t o generate an interrupt to CPU. Vss, V cc : se are ground and power supply lines for circ u it. SL0- S L3 S can Line s : se l ines u sed t o s can k eyboard matrix d isplay di g its. se l ines c an b e programmed as encoded or decoded, using mode control reg i ster. RL0-R L 7 Return Line s : se i nput l ines w hich conne cted to o ne t erminal of key s, w hile o r t erminal o f keys c onnected t o decoded s can l ines. se normally hi g h, b ut pulled low when a key is presse d. 90

95 SHIF T : s tatus o f S hift i nput l ine i s s tored along e ach key code i n F IFO in scanne d k eyboard m ode. T ill i t i s p ulled l ow a k ey cl osure i t i s p ulled u p internally t o kee p i t hig h. CNTL/STB- CONTROL/STROBED I/ P M ode: In Keyboard mode, this line is used as a control input and stored in FIF O on a key closur e. line is a strobe line that enters data into FIFO RAM, in strobed input mode. It has an internal pull up. line is pulled down with a Key c losure. B D Blank Display: T his o utput p in i s u sed t o b lank d isplay d uring dig it s witching or by a b lanking comma n d. OU T A0 O UTA3 and OUTB0 O UTB3: se are output ports for two 16x4 (or one 16 x 8) internal display refresh registe rs. se line s i s synchron ized s can l ines t o scan d isplay keyboar d. two 4-bit ports may also be used as one 8- b it port. Modes of Operati on of 8279 Modes of operation of 8279 are i. Input (Keyb oard) modes i i. Output (Display) modes Input (Keyboard) m o des: 8279 provides three input modes, y : 1. Scanned Keyboar d M o de: T his m ode a llows a k ey m atrix t o b e i nterfaced us ing e ir enc oded o r de coded s cans. In encode d s can, a n 8 x 8 k eyboard o r i n dec oded s can, a 4 x 8 Key board c an be interface d. code o f k ey presse d SHI FT CONTROL sta tus is sto red i nto FI F O RAM. 2. Scanned Sensor Mat ri x: I n t his m ode, a s ensor array c an b e interfa ced 8279 u sing e ir enc oder or decode r sca n s. W ith e ncoder s can 8 x 8 s ensor matrix o r decoder scan 4 x 8 s ensor m atrix c an be interfaced. sensor codes are stored in C PU addressable sensor R A M. 3. S trobed Input: In t his m ode, i f c ontrol l ine goe s l ow, da ta o n r eturn l ines, i s stored i n FI FO byte by by t e. Output (Display) Mode s : 8279 provides two output modes for selecting display o ptions. 1. D isplay Scan: I n t his m ode, 8279 p rovides 8 o r 16 c haracter multiplexe d d isplays t hose c an b e organize d as dual 4-bit or single 8-bit display u nits. 2. Display Ent r y: Display data is entered for display eir from rig h t side or from left side. Details of Modes of Operati on Keyboar d Modes 1. Scanned K eyboard Mode with 2 Key Lock out I n t his m ode o f o peration, w hen a k ey i s p ressed, a d ebounce l ogic come s i nto o peration. Key c ode o f i dentified k ey i s ente red into F IFO SHI FT CNTL s tatus, provided FIF O is not full. 2. Scanned Keyboard with N-ke y Rollover I n t his m ode, e ach key d epression i s t reated independentl y. W hen a key i s pr essed, d ebounce c ircuit w aits 2 keyboa rd s cans n c hecks wher k ey i s sti ll depressed. If it is still depressed, code is entered in FIFO RAM. A ny number of key s can be pressed simultaneously and recognized in order, Key b oard scan record m. 3. Scanned Keyboard Special Error Mo de 91

96 T his m ode i s v alid o nly u nder N-Key r ollover m ode. T his m ode i s p rogrammed u sing e nd i nterrupt/error m ode s et command. I f d uring a s ingle d ebounce period ( two Key board s c an) t wo key s found p ressed, t his i s considere d a s imultaneous depress ion a n err or f lag i s s et. T his f lag, i f s et, p revents f urr w riting i n F IFO b ut a llows g eneration o f f urr interrupts to CPU for FIFO rea d. 3. Sensor Mat rix Mo de I n Se nsor Matrix m ode, d ebounce log ic i s i nhibited 8-byte memory m atrix. s tatus o f s ensor s witch matrix i s f ed directly t o s ensor R AM matrix T hus s ensor RAM bits contains row-wise and column-wise status of sensors in sensor matr i x. 8 Display Modes re v arious o ptions o f display first o ne i s k nown a s l eft entry m ode o r type write r mode. Since in a type writer f irst cha racter type d a ppears a t left-m ost p osition, w hile s ubsequent char acters appe ars successively t o rig ht o f firs t o ne. o r d isplay mat i s known a s rig ht entry mod e, or calculator m ode, s ince calc ulator f irst c haracter e ntered a ppears to right-m ost p osition t his characte r i s s hifted o ne position left when next characte r is enter ed. 1. Left Entry Mo de I n L eft entry mode, data is e ntered l eft s ide o f d isplay u nit. Address 0 of d isplay RA M c ontains l eftmost display chara cter and a ddress 15 o f RA M contains rightmost display characte r. 2. Right Entr y Mo de I n r ight entry m ode, f irst e ntry t o b e d isplayed i s e ntered o n r ightmost displa y. n ext e ntry i s a lso p laced i n r ight m ost d isplay b ut a fter p revious display i s shifted left by one display p osition. Command Words of 8279 A ll C ommand w ords or s tatus w ords are writt en o r rea d A o = 1 C S = 0 t o or fr o m a. Keyboard Display mode set mat o f comm w ord t o s elect differe nt m odes o f o peration o f 8279 i s g iven below with its bit definiti o ns. b. Programma ble Clock c lock for o peration o f 8279 i s o btained by d ividing ext ernal clock i nput s ignal by a programmable constant called presca l er. P PPPP i s a 5-b it b inary constant. i nput frequency i s d ivided by a d ecimal constant ranging from 2 to 31, decided by bits of an internal prescalar, PPPPP. c. Read FIFO /Sensor RAM format of this command is give n as shown below X - d on t care A I - Auto increment fl ag AAA - Address pointer to 8 bit FIFO RAM T his w ord i s w ritten t o s et u p 8279 for reading FIFO/ Se nsor R AM. I n sc anned key board m ode, A I AAA b its o f n o u se w ill automatically d rive b us e ach subsequent read, in same sequence, in which data wa s entere d. d. Re ad Display RAM T his c ommand e nables a prog rammer t o r ead d isplay R AM data CPU w rites t his c ommand word t o 8279 t o prepare i t for d isplay RAM rea d operat i on. A I i s a uto i ncremented fla g A AAA, 4-b it a ddress, poi nts t o 16-byte d isplay R AM i s t o b e r ead. I f A I = 1, addr ess w ill b e automaticall y, incremente d afte r e ach r ead o r w rite t o display R AM. e. Writ e D isplay RAM format of this command is give n as shown below 92

97 A I - Auto increment fl ag AAAA - 4-bit address for 16-bit display RAM to be written Or details of this command are similar to Read Display R AM Command. f. Display Write Inhibit/ Blanki ng I W ( I nhibit w rite fl a g) b its are u sed to mask i ndividual nibble Here D o D 2 c orresponds t o OUTB o O UTB3 w hile D1 D3 c orresponds t o OUTAo-O UTA3 blanking and masking respectively. g. Clear Di splay RAM CD2, CD1, C Do i s a s electable blanking c ode t o c lear a ll r ows o f display R AM as given below. characters A and B represents output nibble s. CD CD1 CDo 1 0 x All Ze ros (x don t care) AB = A3-A o = 2( 0010) and B3-B o = 00(0000) All ones (AB = FF), i. e. clear RAM Here, CA represents clear All and CF represents Cle ar FIFO RAM End Interrupt/Error Mode Set F or sensor m atrix m ode, t his c ommand l owers I RQ l ine enabl es f urr w riting i nto RAM. Orwise, if a charge in sensor valu e i s d etected, IRQ goe s h igh i nhibits writing in sensor R AM. Key-code and stat us Data Forma ts T his briefly desc ribes mats of Key-code /Sensor i n ir resp ective m odes of operation and FIFO Status Word formats of Key-code Data Form a ts: A fter a v alid Key c losure, key code i s entered a s a byte code i nto FI FO R AM, in f ollowing fo r mat, i n sca nned key board m ode. Key code for mat conta ins 3-b it c ontents o f i nternal r ow c ounter, 3-b it c ontents o f c olumn c ounter s tatus o f S HIFT CNTL Key s data forma t o f Key code i n s canned key board mod e i s g iven b e low. I n s ensor mat rix m ode, r eturn l ines i s directly e ntered i nto a n a ppropriate r ow o f sensor R AM, identifie s row o f sensor that chang es i ts stat u s. SHIFT and CNTL Keys are ign ored in this mode. R L bits represent return l ines. R n represe nts sensor R AM r ow n umber i s e qual t o r ow numb er of sensor array in w hich status chang e w as de tected. D ata F ormat o f senso r c ode i n s ensor m atrix mode FIF O Status Word: F IFO s tatus wor d is u sed i n key board s trobed i nput m ode t o i ndicate e r ror. O verrun e rror o ccurs, w hen a n already f ull FIFO i s a ttempted an e ntry, U nder r un e rror o ccurs w hen a n e mpty F IFO r ead i s a ttempted. F IFO s tatus w ord a lso has a b it t o s how unavailability of FIFO RAM because of ongoing clearing o peration. I n sensor m atrix m ode, a b it i s r eserved t o s how a t l east o ne sensor clo sure indic ation i s s tored i n R AM, S / E b it s hows s imultaneous m ultiple c losure err or in spec ial e rror m ode. I n s ensor matrix m ode, a b it i s reserve d to s how that a t least on e sensor c losure i ndication i s s tored i n R AM, S / E b it show s simulta neous m ultiple c losure er ror in specia l error mode. Interfacing and Programmi ng 8279 Pr o blem: Interface keyboard and display c ontroller 8279 with 8086 at a ddress 0080H. Write an ALP to set up 8279 in scanned keyboard mode with encoded scan, N-Key r ollover mode. Use a 16 character display in right entry display mat. n clear display RA M wi th zero s. Read FIFO for key closure. If any key is closed, store it s code to register CL. n write byte 55 to all displays, and return to DOS. clock input to 8279 is 2MHz, operate it at 100K H z. Solution: 93

98 _ 8279 i s i nterfaced l ower by te o f da ta b us, i.e. Do-D7. H ence A o i nput o f 8279 is connected with address linea1. _ datgister of 8279 is to be addressed as 0080H, i. e. Ao= 0. _ For addressing command or status w ord Ao input of 8279 should be 1. _ next step is to write all require d command wor ds for t his problem. Keyboard/Display Mode Se t C W : This command byte sets 8279 in 16-character right entry and encoded scan N-Key rollover mode. Program c lock selection: clock input to 8279 is 2MHz, but operating frequency is to be 100KHz, i. e. clock input is to be divided by 20 ( 10100). T hus prescalar value is and trhe command by t e is set as given. Clear D i splay RAM: This command clears display RAM with programmable blanking code. Read FIF O : This command byte enables programmer to read a key code from FIF O RAM Writ e Display R A M: T his c ommand e nables th e prog rammer t o w rite addresse d d isplay loc ations o f RA M as presented be l ow. 3.7 Interrupt Cont roller I ntel 8259A Prog rammable I nterrupt Contro ller h andles u p t o eig ht vectored priority i nterrupts for CP U. I t i s casc adable u p to 64 vector ed priority in terrupts out a dditional c ircuitry. I t i s p ackaged i n a 28-p in D I P, u ses N MOS technology requires a single a5v supply. Circuitry i s static, requiring no clock input. 8259A i s designed t o m inimize s oftware re al ti me overhea d in handl ing multi- level priority interr u pts. I t ha s seve ral m odes, pe rmitting o ptimization a variety of sy stem r equirements. 8259A i s fully upwa rd co mpatible I ntel S oftware o riginally w ritten 94

99 8259 w ill o perate 8259A i n a ll 8259 equivalen t m odes ( MCS- 80/85, Non-Buffer ed Edge Triggered). F ig.3 Functional b lock diagram of 8259 microproc essor w ill b e executing i ts m ain p rogram only s top t o se rvice p eripheral d evices w hen i t i s t old t o d o s o by d evice i tself. I n e ffect, m ethod w ould p rovide a n e xternal async hronous in put w ould i nform p rocessor i t s hould comple te w hatever i nstruction i s currently being exe cuted and fetch a ne w r outine th at will s ervice r equesting d e vice. O nce t his servicin g i s c omple te, h owever, p rocessor would resume exactly where it left off.this method is called Interr u pt. S ystem t hroughput w ould d rastically i ncrease, t hus m ore t asks c ould b e a ssumed b y microcom puter t o f urr enha nce i ts c ost effectiven e ss. Progra mmable I nterrupt C ontroller (P I C) f unctions a s a n o verall manag er i n a n Interrupt-D riven sy stem environme n t. I t a ccepts r equests periphe ral e quipment, determin es w hich o f i ncoming r equests i s o f highe st i mportance (priorit y ), a r tains whe r incoming r equest h as a h igher priority value t han leve l currently being servi c ed, i ssues a n interrupt to CPU based on this determina t ion. E ach p eripheral d evice or s tructure usually h as a sp ecial prog ram o r ``routi n e' ' th at i s associate d i ts s pecific f unctional o r operatio nal r equirements; t his i s refer red t o a s a ` `service r outine''. P I C, after i ssuing a n Int errupt t o C PU, must s omehow i nput i nformation i nto C PU c an ` `point' ' Progra m C ounter t o s ervice rout ine a ssociated r equesting d evice. T his ``point e r' ' i s a n a ddress i n a v ectoring t able will often be referred to, in this document, as vectoring data. 95

100 Interrupt request register ( I R R) AND in- service register ( I S R) : i nterrupts a t I R i nput l ines h andled by t wo r egisters i n casc a de, I nterrupt R equest R egister ( IRR) In-S ervice ( ISR). I RR i s u sed t o s tore a ll i nterrupt l evels which are requesti ng se rvice; and ISR i s u sed t o s tore a ll i nterrupt le vels which are being se rv iced. Priority r esolver T his l ogic b lock determin es pr iorites of bi ts s et i n IRR. h ighest priority i s selected and strobed into corresponding bit of ISR during I N TA pulse. Interrupt mask reg ister ( I M R) I MR s tores b its w hich mas k interrupt l ines t o b e m asked. I MR o perates o n I RR.Masking o f a h igher priority i nput will n ot a ffect interr upt r equest l ines of lower quality. I NT ( I N TERRUPT) T his o utput g oes directly t o C PU i nterrupt input. V OH leve l o n t his l ine i s designed to be fully compatible with 8080A, 8085A and 8086 input leve l s. I NTA ( INTERRUPT ACKNOWL E DGE) I NTA p ulses w ill c ause 8259A t o r elease v ectoring i nformation o nto b us. format of this data depends on system mode (mpm) of 8259A. Data bus buffer This 3-state, bidirectional 8-bit buffer is us ed to interface 8259A to s ystem Control words and status information are transferred through Data B us B u ffer. D ta a B us. Read/write control logi c function of this block is to accept OUTput comma nds from CPU. I t contai ns I nitialization C ommand W ord ( ICW) r egisters O peration C ommand W ord ( OCW) registers which store various control formats for device operat ion. This function blo ck also allows status of 8259A to be transferred onto Data B u s. CS (CHIP SEL E CT) A L OW o n t his i nput e nables 8259A. No readin g or wr iting o f c hip w ill o ccur u nless devic e is selecte d. WR (WRI T E) A L OW o n 8259A. t his nput i e nables C PU to write c ontrol wor ds ( ICWs an d OC Ws ) t o RD ( REA D ) 96 DEPT.OF ECE

101 A L OW o n t his i nput e nables 8259A t o s end s tatus o f Interrupt R equest R egister ( IRR), I n S ervice R egister ( ISR), I nterrupt M ask R egister ( I MR), o r Inte rrupt l evel onto Dat a B u s. A 0 T his i nput s ignal i s used i n c onjunction WR R D sig nals t o write c ommands i nto v arious c ommand r egisters, a s w ell a s rea ding var ious s tatus r egisters o f c hip. This line can be tieddirectly to one of address line s. Interrupt sequence p owerful feature s of 8259A i n a microcom puter syste m i ts programmability interrupt routine a ddressing c apability. latt er a llows d irect o r i ndirect j umping t o s pecific i nterrupt r outine reque sted out any p olling o f interr upting d evices. normal sequence of events during an interrupt depends on type of CPU being u sed. events occur a s f o llows: 1. O ne or m ore o f I NTERRUPT R EQUEST l ines ( I R7± 0) are raised h igh, s etting th e corresponding I R R bit(s) A evaluates se requests, and sends an INT to CPU, if appropriate. 3. CPU acknowledges I NT and responds a n IN T A pulse. 4. U pon receiving a n INT A C PU g roup, highe st priority I SR b it i s s et, c orresponding I RR b it is r ese t. 8259A will a lso relea se a C ALL instr uction c ode ( ) onto 8-bit Data Bus through its D7± 0 pins. 5. T his C ALL i nstruction w ill i nitiate t wo m ore I NTA p ulses t o b e s ent t o 8259A CPU g r oup. 6. se two INTA pulses allow 8259A to release its preprogrammed su broutine a ddress o nto D ata Bus. lo wer 8-b it a ddress i s r eleased a t f irst INT A pul se higher 8-bit address is released at sec ond INTA p ulse. 7. T his c ompletes 3-b yte C ALL i nstruction rele ased by 8259A. I n A EOI m ode I SR b it i s rese t a t e nd o f t hird INTA p ulse. O rwise, ISR b it r emains s et u ntil a n a ppropriate EOI c ommand i s i ssued a t e nd o f interrupt sequ e nce. eve nts occurring in an 8086 sys tem are same until step U pon r eceiving a n INT A C PU g roup, h ighest p riority ISR b it i s s et corresponding IRR bit is reset. 8259A does not drive Data Bus during this cycle w ill i nitiate a s econd INT A p ulse. D uring this p ulse, th e 8259 A release s a n 8- bit pointer onto Data Bus where it is read by C PU. 10. T his c ompletes i nterrupt c y cle. I n A EOI m ode I SR b it i s r eset a t e nd o f s econd I NTA p ulse. O rwise, I SR b it r emains s et u ntil a n approp riate EOI c ommand i s i ssued a t e nd o f th e inter rupt subr o utine. I f n o i nterrupt requ est i s p resent a t s tep 4 o f e ir s equence ( i.e., r equest wa s t oo s hort i n d uration) 8259A wi ll i ssue a n 97

102 interrupt level 7. B oth vectoring by tes CA S l ines w ill lo ok l ike a n interrupt leve l 7 w as r equested. W hen 8259A PIC receives a n i nterrupt, I NT becom es a ctive a n i nterrupt acknowledg e cycle i s s tarted. I f a hig her priority i nterrupt occur s bet ween t wo I NTA p ulses, I NT l ine g oes inac tive i mmediately a fter s econd INTA p ulse. A fter a n u nspecified a mount o f t ime I NT l ine i s activ ated a gain t o signify h igher priority interrupt waiting for servic e. 3.8 D MA Controller - DMA Controller 8257 D irect M emory A ccess o r D MA m ode o f t ransfer i s f astest a mongst a ll m odes o f t ransfer. I n t his m ode, d evice may t ransfer d irectly t o/from m emory out any i nterference C PU. d evice r equests C PU ( th rough a D MA c ontroller) t o h old i ts, addre ss c ontrol b us, s o d evice m ay t ransfer data directly to/from memory. D MA da ta t ransfer is i nitiated only after rec eiving H LDA sig nal th e CP U. I ntel s 8257 i s a f our c hannel D MA controller desi gned to b e interfac ed with ir family o f microprocessor s. 8257, o n behalf o f devi c es, re quests C PU for b us acc ess using loc al bus reque st input i. e. HOLD in minimum mode. I n maxi mum m ode o f microproc essor RQ/ GT p in i s u sed a s b us requ est i nput. O n receiving HL DA s ignal (in m inimum m ode) o r R Q/GT s ignal ( in maxi mum m ode) C PU, r equesting d evices g ets a ccess o f b us, i t c ompletes r equired n umber o f DMA cycle s for da ta tran sfer n h ands over th e c ontrol of th e bus back to CPU. Internal Architecture o f 8257 i nternal architectur e o f 8257 i s s hown i n figu r e. c hip s upport four D MA chann e ls, i. e. f our p eripheral d evices c an independently requ est D MA transf er throug h se c hannels a t a t ime. D MA c ontroller h as 8-bit i nternal b uffer, ad/write u nit, a c ontrol u nit, a priority re solving u nit along with a se t o f r egisters perfor ms D MA o peration o ver four independe nt D MA c hannels. E ach o f four chann els o f 8257 ha s a pair of two 16-bit registers, viz. D MA address registe r terminal count register. re t wo c ommon r egisters a ll chann e ls, namel y, m ode s et regis ter s tatus r egister. T hus re a t otal o f t en re g isters. C PU s elects o ne o f th ese t en r egisters u sing a ddress l ines Ao-A3. T able s hows h ow Ao-A3 b its m ay b e u sed s electing one of se registe rs. DMA Address Register E ach D MA c hannel h as o ne D MA a ddress regist e r. f unction o f t his r egister i s t o s tore address o f sta rting memory lo c ation, whic h w ill b e acce ssed by th e D MA c hannel. T hus starting address o f memory bloc k wh ich w ill b e accessed by d evice i s f irst l oaded i n D MA a ddress r egister o f chann e l. d evice w ants t o t ransfer over a DMA channel, will access block of memory with starting address stored in DMA Address Registe r. Terminal Count Register E ach o f four D MA c hannels of 8257 has one termin al count register ( T C). T his 16-b it r egister i ssued a rta ining tha t t ransfer through a D MA channe l ceases o r s tops a fter r equired n umber o f DMA cycl e s. l ow o rder 14-b its o f terminal c ount r egister i nitialized b inary e quivalent o f n umber o f requir ed D MA cycle s minus one. A fter e ach D MA cycl e, t erminal c ount registe r conte nt w ill b e d ecremented by o ne finally i t b ecomes z ero a fter r equired n umber o f D MA cycle s ove r. b its o f t his r egister i ndicate type o f D MA oper ation ( transf e r). I f de vice wan ts to write data into memor y, DMA o peration i s c alled D MA wr ite o peration. Bi t 14 of reg ister in this case will be set to one bit 15 will be set to ze ro. 98

103 T able g ives d etail o f D MA ope ration s election c orresponding b it configura tion of bits 14 and 15 of TC register. Table 3. D MA peration selection using A o 15/ RD and A15/ WR Mode Se t Register m ode s et r egister i s u sed programming 8257 a s p er requ irements of syste m. f unction o f m ode s et r egister i s t o e nable D MA chann els individually and also to set various modes of ope rat ion. D MA c hannel s hould n ot b e e nabled t ill D MA a ddress reg ister t erminal c ount r egister c ontain v alid i nformation, o rwise, a n u nwanted D MA r equest m ay initia te a D MA cycl e, probably destroying va lid memory. b its Do-D3 enable one o f f our D MA channe ls o f e xample, i f D o i s 1, c hannel 0 i s e nabled. I f b it 4 is set, rotating priority is enabled, orwise, norma l, i. e. f ixed priority is e nabled. F ig 3.32 B it definition of mode set register If T C S TOP b it i s s e t, selected channel i s d isabled afte r terminal c ount co ndition i s r eached, i t f urr pre vents any D MA cy cle o n ch a nnel. T o e nable c hannel a gain, t his b it m ust b e reprog rammed. I f T C S TOP b it i s p rogrammed t o be z e ro, c hannel i s n ot d isabled, e ven a fter c ount reache s z ero f urr reques t a llowed o n same channel. a uto l oad b it, i f s et, e nables channe l 2 r epeat b lock chaining o perations, out immedia te softw inter vention between t wo suc cessive bloc k s. c hannel 2 reg isters u sed a s u s ual, w hile channel 3 reg isters u sed to s tore th e b lock reinitialisation paramete rs, i. e. DMA starting address and termina l c o unt. A fter f irst b lock i s t ransferred using D MA, th e channe l 2 r egisters reloade d corresponding c hannel 3 register s next b lock t ransfer, if th e updat e f lag i s set. extended write bit, if set to 1, extends duration of MEMW and IOW signals by a ctivating m e arlier, t his i s u seful i n i nterfacing periphera ls d ifferent a ccess time s. I f p eripheral i s n ot ac cessed in stipulate d t ime, i t i s exp ected t o giv e NOT R EADY i ndication t o 8257, to request i t to a dd one or more wa it st ates i n D MA CYCLE. mode set register can only b e written into. Status Register s tatus r egister o f 8257 i s s hown i n f igure. l ower orde r 4-b its o f t his r egister c ontain t erminal c ount s tatus f our i ndividual c hannels. I f any of se b its i s s et, i t indicates that specific channel has reached te rminal c ount c o ndition. 99

104 ROCONTR OLLER Fig 3.33 Status Register se bits remain set till eir status is read by CPU or 8257 is rese t. update f lag i s n ot affecte d by rea d opera t ion. T his f lag c an only b e c leared b y resetting 8257 o r by re setting a uto l oad b it o f m ode se t regist er. I f upda te f lag i s s et, c ontents of channe l 3 r egisters are reloade d t o correspon ding reg isters of c hannel 2 w henever c hannel 2 reac hes a termi nal c ount c ondition, a fter transferring one b lock next b lock i s t o b e transfe rred usin g a uto l oad feature of u pdate f lag i s s et every t ime; th e channe l 2 reg isters ar e loaded c ontents o f cha nnel 3 registe rs. I t i s c leared b y c ompletion o f f irst D MA cy cle o f n ew b lock. This register can only r ead. Data Bus Bu ffer, Read/Write Logic, Control Unit and Priority Res olver 8- b it. T ristate, bidire ctional buffe r interfaces internal b us o f 8257 external system bus under control of various control signa l s. I n s lave m ode, r ead/write l ogic acc epts th e I / O R ead o r I/O W rite sign a ls, d ecodes Ao-A 3 l ines e ir wr ites c ontents o f data bus t o addres sed i nternal r egister o r r eads c ontents o f selecte d r egister d epending upo n w her I OW or IOR sig n al is activated. I n m aster m ode, r ead/write l ogic g enerates I OR I OW sig nals t o c ontrol f low t o o r s elected peripheral. c ontrol logic c ontrols s equences o f o perations generates require d c ontrol signals l ike A EN, A DSTB, M EMR, M EMW, T C M ARK along wi th a ddress l ines A4- A 7, i n master m ode. priority r esolver r esolves p riority o f f our D MA cha nnels depending u pon w her n ormal priority o r rotating priority is prog r ammed. Signal Description of 8257 DRQo-DR Q 3: se f our i ndividual c hannel D MA reque st i nputs, u sed by periphera l d evices r equesting D MA s ervices. D RQo has th e h ighest priority whi le DRQ3 h as lowest one, if fixed priority mode is selecte d. DACKo-DACK 3 : se active-low D MA acknowledg e o utput l ines w hich inform requesting p eripheral request h as b een h onoured and b us is relinquish ed by CPU. se lines may act as strobe lines for requesting devic es. 100

105 F ig 3.34 Pin Diagram of 8257 Do- D 7: se b idirectional, da ta l ines u sed t o i nterface sy stem b us i nternal b us o f se l ines carry c ommand w ords t o 8257 and s tatus w ord from 8257, in s lave mode, i. e. under contr ol of CPU. data over se lines may be transferred in both dir ect ions. W hen 8257 i s bus master ( mas ter m ode, i. e. not u nder C PU cont r ol), it u ses Do-D7 lines t o send highe r byte of gener ated addr ess to la tch. T his a ddress is f urr latc hed u sing ADS TB sign a l. addre ss i s t ransferred o ver Do-D7 d uring th e f irst c lock c ycle o f D MA cycl e. D uring r est o f p eriod, i s a vailable o n b us. I OR: T his i s a n active-l ow b idirectional t ristate i nput l ine a cts a s a n i nput i n s lave m ode. I n s lave m ode, t his i nput s ignal i s u sed by C PU t o r ead i nternal regist ers o f 8257.this l ine a cts o utput in m aster m ode. I n m aster mod e, t his signa l i s use d t o r ead a peripheral during a memory write cy c le. I OW: T his i s a n a ctive l ow bid irection t ristate l ine a cts a s input in slave mo de t o load c ontents o f data bus t o 8-b it m ode regist er o r upper/lowe r byte o f a 16-b it D MA a ddress r egister or t erminal c ount r egister. I n m aster m ode, i t i s a c ontrol o utput loads data to a peripheral during DMA memory read cy c le (write to peripheral). CLK: T his i s a c lock f requency i nput r equired t o d erive b asic sy stem t imings i nternal operation of RESET: T his active-h igh asynchr onous i nput d isables a ll D MA channe ls by clearing m ode register and tristate s all contr o l lines. Ao- A 3: se f our least s ignificant addre ss l ines. I n s lave m ode, y a ct a s input w hich sele ct o ne o f r egisters t o b e r ead o r w ritten. I n m aster m ode, y f our l east significant memory address output lines generated by C S: T his i s a n active-l ow c hip s elect l ine e nables r ead/write o perations /to 8257, i n s lave m ode. I n master m ode, i t i s a utomatically d isabled t o p revent h e c hip g etting s elected (by CPU) while performing DMA ope rat ion. 101

106 A4-A7: T his i s h igher n ibble o f l ower byte address gene rated by 8257 d uring m aster mode of DMA opera t ion. R EADY: T his i s a n active-h igh asynchr onous i nput u sed t o s tretch memory re ad w rite cy cles of 8257 by inserting wait states. This is used while interfacing slower peripheral s.. HR Q : h old re quest o utput r equests acc ess o f th e syste m b us. I n noncascade d 8257 s ystems, t his i s connected HOL D p in o f CP U. I n ca scade m ode, t his p in o f a s lave i s connected with a D RQ i nput line o f m aster 8257, w hile o f m aster i s connect ed HOLD input of CPU. HLD A : C PU d rives t his inpu t t o D MA controller h igh, w hile g ranting b us t o devi ce. T his p in i s c onnected t o H LDA output o f C PU. T his i nput, i f h igh, i ndicates t o DMA controller that bus has been granted to requesting peripheral b y CPU. MEM R: T his a ctive l ow memory r ead o utput i s used t o read data add ressed memory locations during DMA read cycle s. MEM W : T his active-l ow thre e stat e o utput i s u sed t o write t o addre ssed memory loc ation during DMA write oper a tion. AD S T: T his o utput 8257 s trobes h igher by te o f memory addr ess generate d by DMA controller into latche s. A EN: This output is used to disable system data bus and control bus driven by CPU, t his m ay be used t o disabl e system address and bus by using enable i nput of b us d rivers t o i nhibit non-d MA d evices r esponding dur ing D MA operati o ns. If 8257 i s I / O m apped, this s hould b e u sed t o d isable o r I / O devices, w hen th e D MA controller addresses is on addr es s bus. TC: T erminal c ount o utput ind icates t o currently se lected pe ripherals th e prese nt D MA c ycle i s l ast previously prog rammed da ta b lock. If T C STOP b it i n m ode set r egister i s set, selected channel will be d isabled at e nd o f D MA cycl e. TC pin is activated when 14-bit content of ter minal count register of s elected channe l b ecomes e qual t o z e ro. l ower or der 14 b its o f t erminal coun t register are t o b e programmed with a 14-bit equivalent of ( n-1), if n is desired number of DMA cycle s. MARK: modulo 128 mark output indicates to selected peripheral that current DMA cy cle i s 128t h cy cle s ince p revious M ARK outp u t. Th e m ark w ill b e acti vated a fter eac h 128 c ycles o r i ntegral m ultiples o f i t beginning i f b lock ( f irst D MA cycle), if total number of required DMA cycles (n) is completely divisible by 128. Vc c: This is a +5v supply pin required for operation of cir cu it. GN D : This is turn line for supply ( ground pin of I C ). Interfacing 8257 with 8086 O nce a DMA controller i s i nitialized by a C PU propert y, i t i s ready to ta ke c ontrol o f s ystem b us on a D MA r equest, e ir a periphera l o r i tself (in cas e o f memory-to m emory transfer). DM A c ontroller sends a HOL D request to CPU w aits for C PU t o a ssert HL DA si g nal. C PU r elinquishes contr ol o f th e bus befor e asserting HLDA sign al 102

107 F ig 3.35 Interfacing 8257 w th i C PU O nce H LDA sig nal g oes hi g h, D MA con troller a ctivates DA CK s ignal t o r equesting p eripheral g ains c ontrol o f sy stem b us. D MA controller i s sole master of bus, till DMA operation is ove r. C PU remains in HOLD status ( all o f i ts signa ls tris tate exc ept HOL D and H LDA), t ill D MA c ontroller i s m aster o f b us. I n oth er w ords, D MA con troller i nterfacing circui t i mplements a s witching a rrangement a ddress, da ta c ontrol b usses o f m emory peripheral subsystem from/to CPU to/from D MA controller. 3.9 T raffic Light Control: Traffic Light Controller Using 8086 Traffic l ight c ontroller inte rface m odule i s desig ned t o simula te funct ion o f four way traffic lig ht controlle r. C ombinations o f r ed, a mber g reen L ED s p rovided t o i ndicate H alt, Wa it G o signals for vehicle s. Combination of red and g reen LED s are provided for pedestria n crossing. 36 LED s are arrang e d in form of an intersection. A typical junction is represented on PCB with comprehensive legend printing. A t l eft c orner o f each r oad, a g roup o f f ive LED s ( red, amber 3 gr e en) arrang ed i n form of a T-section to control traffic of tha t roa d. E ach r oad i s n amed Nor th ( N), S outh(s), E ast ( E) and We st ( W). L ED s L 1, L 10, L 19 & L28 (Red) are for stop sig n al for vehicles on road N, S, W, & E respectively. L 2, L 11, L 20 & L 29 ( Amber) indica tes w ait s tate v ehicles o n r oad N, S, W, & E respectively. L 3, L4 & L 5 ( Gre en) for l eft, stra it right t urn v ehicles on r oad S. s imilarly L12-L13- L 14, L23-L22-L 21 & L32-L31-L 30 s imulates same f unction roads E, N, W respectively. A total of 16 L E D s (2 Red & 2 Green at each road) are provided for pedestrian crossing. L7-L 9. L16- L 18, L25-L27 & L34-L 36 ( Green) w hen o n a llows pedestrians t o c ross L6- L8, L15-L17, L24-L 26 & L33-L 35 (Red) when on alarms pedestrians to wait. T o m inimize h ardware p edestrian s i ndicator L ED s ( both r ed gre en ar e c onnected to same port lines (PC4 to PC7) with red inverte d. R ed L ED s L 10 & L 28 conne cted t o p ort l ines P C2 & P C3 w hile L 1 & L 19 c onnected t o l ines P C0 & P C1 a fter inversi o n. A ll o r L ED s ( amber gre e n) ar e connected to por t A & B. Working: i s i nterfaced 8086 i n I / O ma pped I / O a ll p orts o utput p orts. b asic op eration o f i nterface i s exp lained h elp o f enc losed progr am. encl osed p rogram a ssumes n o entry of v ehicles N orth t o W e st, r oad E ast t o S outh. A t beg inning o f progra m a ll r ed LE D s are s witch O N, and a ll o r LED s ar e s witched O FF. Amber L ED i s switched O N be fore switching ove r to proceed s tate Halt sta t e. sequence of traffic followed in progra m is given be l ow. 103

108 a ) F rom road north to East From roa d eas t to north Fr om road south to wes t Fr om road wes t to south Fr om road wes t to north b) From road nort h to East Fr om road south to wes t F rom road south to nort h F rom road south to eas t From road nort h to south From road south to nort h Pedestrian crossing at roa ds w es t & eas t d) Fr om road east to wes t Fr om road we st to eas t Pedestrian crossing a t roa d s north & s outh UNIT-I V MICROCONT ROLLER DEVICE ON-C HIP ON-CHIP 16-B IT NO. OF FUL L DAT A PROGR AM T IMER/COUNTER V ECTORED D UPLEX MEMORY MEMORY INTERUPT S I / O 4.1 ( byte s ) AT89 C51 2 AT89 C52 5 ( byte s ) No e no e k OM k OM k EPRO k EPRO Flas h Memory 8 Flas h memory 1 8 n 2 6 n 1 8 R 2 6 R 1 8 M 2 6 M 1 8 k 2 6 k Architecture of 8051: It is a singl e chip Consists of CPU, Memo ry I/ O ports, timers and or peripheral s It is a CPU Memory, I/ O Ports to be connected externally. S mall size, low power, low c o st; Harvard architecture with separate program and data memory; No data corruption or loss of data ; but with comple x circu it 8051 has three very general types of memory. On-Chip Memory refers to any m emory (Code, RAM, or o r) that physically e xists on microcontroller its elf. On-c hip memory can be of several t y pes. 104

109 E xternal Code Memory is code (or program) memory that resides off- c hip. T his i s o ften in form of an external EPRO M. External RAM is RAM memory that resides off-c hip. This is often in form of standard static RAM or flash RA M i s a flexi ble m icrocontroller with latively lar ge numb er o f m odes of opera t ions. Y our p rogram may ins pect /or chang e oper ating m ode of 8051 by manipulating v alues of 8051's Special Function Registers(SFRs). SFRs are accessed as if y were normal In ternal RAM. only difference is that In ternal RAM is from address 00h through 7Fh whereas SFR reg isters exist in ad dress range of 80h throug h FFh Fi g architecture 8051 Clock and Instruct ion Cycle In 8051, one instruction cycle consists of twelve (12) clock cy c les. In struction cycle is sometimes called as Machine cyc le by s ome authors. F ig 4.2 I nstruction cycle of 8051 I n 8051, each instruction cycle has six states (S 1 - S 6 ). Each state has two pulse s ( P1 a n d P2) 128 bytes of Internal RAM Stru cture (lower addres s space) 105

110 Fi g 4.3: Internal RAM Structure lower 32 by tes are divided into 4 separate banks. Each register bank has 8 regi sters of one byte each. A regis ter bank is selected dependi ng upon two bank se lect bits in P SW r egister. Next 16by tes b it a ddressable. I n total, 128bits ( 16X8) available i n a ddressable a. E ach b it c an b e accesse d modi fied by s uitable instructio n s. b it a ddresses from 00H ( LSB of f irst by te i n 20 H) t o 7 FH (MSB of l ast by t e in 2FH). Remaining 80by tes of RAM are available for genera l purpose. Internal Data Mem ory and Special Function Register ( SF R) Ma p Fi g I nternal Data Memory Map s pecial f unction regis ters (S F Rs) mapp ed i n u pper 128 byte s o f internal data memory addre s s. Henc e re is a n a ddress overlap b etween uppe r 128 by tes o f R AM S FRs. P lease no te th at u pper 128 byte s o f da ta R AM p resent only in 8052 famil y. l ower128 byte s o f R AM ( 00H - 7 FH) c an b e a ccessed b oth by dire ct or indire ct addressing whil e u pper 128 bytes o f RA M ( 80H - F FH) a ccessed by i ndirect addressing. S FRs (80H - FFH) a ccessed by d irect a ddressing onl y. This f eature distinguishes u pper 128 by tes of memory SF Rs, a s shown in fi g 5. Processor Status Wor d ( P S W) Addre ss=d0h F i g 4.5: Processor Status Word PSW register stores important status conditions of microcontrolle r. I t also stores bank select bits (RS1 & RS0) for register bank sele ct ion. 106

111 4.2 S pecial Function Registers: 8051 i s a flexi ble m icrocontroller with latively larg e n umber of m odes o f opera t ions. Y our prog ram m ay i nspect /or c hange operating m ode o f 8051 by manipulating values of 8051's Special Function Regi sters (SFRs). S FRs a ccessed a s i f th ey w ere n ormal Internal R AM. o nly differenc e i s I nternal R AM i s a ddress 00h t hrough 7 Fh wherea s S FR reg isters exi st i n a ddress range of 80h through FFh. Each SFR has an address (80h throug h FFh) and a name. f ollowing c hart prov ides a g raphical presen tation o f 8051' s S F Rs, ir n ames, ir address. A s y ou c an s ee, althoug h addr ess rang e o f 80h t hrough F Fh o ffer 128 p ossible addres s es, re only 21 SF Rs in a s tandard A ll o r a ddresses i n SFR rang e ( 80h thr ough F Fh) considered invalid. Writi ng to o r reading se registers may p roduce undefined values or behavior. SFR Types S FRs related t o I/O ports: 8051 ha s four I/O p orts of 8 b its, for a t otal o f 32 I/O line s. Wh er a give n I/O l ine i s hig h o r l ow v alue r ead from lin e are c ontrolled by SFRs. S FRs c ontrol o peration o r config uration o f s ome aspect o f Fo r example, T CON controls timers, SCON controls serial port, th e r e maining SFRs, are a uxillary SF Rs i n s ense y don' t directly config ure 8051 bu t obviously 8051 c annot o perate out m. F or e xample, o nce s erial por t has b een config ured u sing SCON, program may r ead or write to serial port using SBUF registe r. SFR Descripti ons P 0 ( P ort 0, A ddress 80h, Bit-Addressab l e) : T his i s i nput/output p ort 0. E ach b it o f t his S FR c orresponds t o o ne o f p ins o n microcont r oller. F or ex a mple, b it 0 o f p ort 0 i s p in P 0.0, bi t 7 i s i n P 0.7. W riting a v alue of 1 to a b it o f t his SFR w ill send a hig h leve l o n corresponding I/ O pin whereas a value of 0 will bring it to a low leve l. S P ( Stack P ointer, A ddress 81h) : T his i s s tack p ointer o f microcont r oller. T his S FR i ndicates w here n ext v alue t o b e t aken s tack w ill b e r ead i n Inte rnal RA M. I f y ou p ush a value o nto s tack, va lue w ill b e w ritten t o ad dress o f SP + 1. T his S FR i s m odified b y a ll i nstructions which modify th e sta c k, such a s PUS H, POP, L CALL, R ET, R ETI, w henever i nterrupts provoke d by mi c rocontroller. Stack Pointer, like all registers except DPTR and PC, may hold an 8-bit ( 1-by t e) value. W hen y ou p op a v alue o ff s tack, 8051 r eturns v alue memory location indicated by S P, and n decrements value of SP. T his o rder o f opera tion i s import a nt. W hen 8051 i s i nitialized S P w ill b e initialize d to 07h. I f y ou i mmediately p ush a v alue o nto s tack, value w ill b e stor ed i n Interna l RA M addr es s 08h. F irst 8051 w ill incre ment value of SP (fr om 07h to 08h) and n will store p ushed v alue a t memory a ddress ( 08h). I t i s a lso u sed intrinsically whenever a n interrupt is triggere d. DPL/DPH (Dat a Pointe r L o w/high, A ddresses 82h/83h) : SFRs DPL D PH wor k toger t o represe nt a 16-b it v alue ca lled D ata Pointer. data p ointer i s u sed i n o perations r egarding e xternal R AM s ome i nstructions i nvolving c ode memor y. S ince i t i s a n u nsigned two-by te i nteger v alue, i t c an re present v alues 0000 h t o FFFFh ( 0 through 65,535 decima l ). P CON ( Power C ontrol, Addres ses 87h) : P ower C ontrol S FR i s u sed t o control 8051's p ower c ontrol m odes. C ertain o peration m odes o f 8051 a llow 8051 t o g o i nto a t ype o f " sleep" mode w hich r equires m uch le ss p ower. se modes o f o peration c ontrolled through P CON. Additionally, o ne o f b its i n PCON is us ed t o double th e effective baud rate of 8051' s serial por t. T CON ( Timer Control, A ddresses 88h, Bit-A d dressable) : T imer C ontrol S FR is u sed t o c onfigure m odify way i n w hich 8051' s t wo t imers o per ate. T his S FR c ontrols w her e ach of t wo t imers i s r unning o r s topped c ontains a f lag t o indic ate 107

112 e ach t imer h as over f lowed. Additionall y, s ome non-t imer r elated b its l ocated i n T CON S FR. se b its u sed t o configur e way i n w hich ext ernal i nterrupts are a ctivated a lso conta in ext ernal interrup t f lags which s et w hen an ext ernal interrupt has occurre d. T MOD ( Timer M ode, A ddresses 89h) : T imer M ode S FR i s u sed t o c onfigure th e m ode o f o peration o f e ach o f th e t wo t imers. U sing t his S FR y our p rogram m ay c onfigure e ach t imer t o b e a 16-b it t imer, a n 8-b it a utoreload t imer, a 13-b it t imer, o r t wo sep arate time rs. A dditionally, y ou m ay config ure time rs to only c ount whe n a n ext ernal p in i s a ctivated or to count " e vents" that are indicated on an externa l pin. T L0/TH0 ( Timer 0 Lo w /High, A ddresses 8Ah/8Bh ): se t wo SFR s, t aken to g er, r epresent t imer 0. ir exa ct b ehavior depends o n h ow t imer i s configur ed i n T MOD S FR; however, th ese timers alway s c ount u p. W hat is config urable i s h ow whe n y increment in value. T L1/TH1 ( Timer 1 Low / High, A ddresses 8 Ch/8Dh) : se t wo S FRs, t aken t oger, r epresent t imer 1. ir exa ct b ehavior depends o n h ow t imer i s configur ed i n T MOD S FR; however, th ese timers alway s c ount u p. W hat is config urable i s h ow whe n y increment in value. P 1 ( P ort 1, A ddress 90h, Bit-Addressab l e) : T his i s i nput/output p ort 1. E ach b it o f t his S FR corre sponds t o on e o f p ins o n micro c ontroller. F or e xample, b it 0 o f p ort 1 i s p in P 1.0, b it 7 i s p in P 1.7. W riting a value o f 1 to a b it o f t his SFR w ill sen d a hig h l evel o n corresponding I/ O pin whereas a value of 0 will bring it to a low leve l. S CON ( Serial C ontrol, A ddresses 98h, Bit-Addressab l e) : S erial Con trol S FR i s u sed t o configur e be havior o f 8051' s on-b oard se rial p ort. T his S FR contr ols b aud r ate o f s erial p ort, wheth er s erial p ort i s a ctivated t o r eceive dat a, als o conta ins f lags that are set when a byte is successfully sent or receive d. S BUF ( Serial C ontrol, A ddresses 99h ): S erial Buf fer S FR is u sed t o s end receive v ia on-b oard s erial p ort. A ny v alue written to S BUF w ill b e s ent o ut s erial p ort' s TXD p in. A ny v alue whic h 8051 r eceives v ia s erial p ort' s R XD pin w ill b e d elivered t o u ser p rogram v ia SBU F. I n o r w ords, S BUF s erves a s o utput p ort w hen w ritten to and as an input port when read fr o m. P 2 (Por t 2, A ddress A0 h, Bit-A ddressab le) : T his i s i nput/ o utput p ort 2. E ach b it o f t his S FR c orresponds t o o ne o f p ins o n microcont r oller. F or e xample, b it 0 o f port 2 is p in P 2.0, b it 7 i s p in P 2.7. W riting a value o f 1 to a b it o f t his SFR w ill sen d a hig h l evel o n corresponding I/ O pin whereas a value of 0 will bring it to a low leve l. I E ( Interrupt E nable, A ddresses A8h ): I nterrupt E nable S FR i s u sed t o e nable disab le s pecific i nterrupts. l ow 7 b its o f S FR use d to ena ble/dis able specif ic interrupts, where as highe st b it i s used t o e nable or d isable AL L interrupt s. T hus, i f hig h b it o f IE i s 0 a ll inte rrupts are disabled regardless of wher an individual interrupt is enabled by setting a lowe r bit. P 3 ( Port 3, Address B 0h, Bit-Addressab l e) : Thi s i s i nput/output p ort 3. E ach b it o f this S FR corre sponds t o o ne o f p ins o n micro c ontroller. F or e xample, b it 0 o f p ort 3 i s p in P 3.0, b it 7 i s p in P 3.7. W riting a value o f 1 t o a b it o f t his S FR w ill sen d a hig h l evel o n corresponding I / O pin whereas a value of 0 will bring it to a low leve l. I P ( Interrupt P riority, A ddresses B 8h, Bit- A ddressable) : Interrupt Priority SFR i s u sed t o specify relativ e priority o f e ach inte r rupt. O n 8051, a n i nterrupt may e ir be of low (0) priority or high (1) priority. An interrupt may only interrupt interrupts of lower priority. For ex a mple, i f w e config ure 8051 s o a ll inter rupts are o f low priority e xcept s erial interru p t, s erial i nterrupt w ill a lways b e a ble t o i nterrupt syste m, e ven if anor interrupt is currently executing. However, if a seria l interrup t i s exe cuting n o o r i nterrupt w ill b e a ble t o i nterrupt serial i nterrupt r outine s ince th e seria l inter rupt routine has highest priority. 108

113 P SW ( Program S tatus W ord, A ddresses D0h, Bit-Addressab le ): P rogram S tatus W ord i s u sed t o s tore a n umber o f i mportant b its s et and c leared by 8051 instruc t ions. P SW S FR c ontains carry fla g, auxiliar y carry fl a g, o verflow f lag, parity f lag. Additionall y, P SW r egister c ontains r egister b ank se lect flag s which are used to select which of "R" registe r ban ks are currently selecte d. A CC ( Accu m ulator, Ad dresses E 0h, Bit- A ddressable) : Accumula tor i s o ne of m ost u sed S FRs o n 8051 s ince i t i s involved i n s o many instruct io ns. A ccumulator r esides a s a n S FR a t E0 h, w hich m eans instru ction M OV A,#20h i s really same a s M OV E0h,#20h. f irst m ethod r equires t wo byte s whe reas s econd o ption r equires t hree byte s. I t c an h old an 8-b it (1-b y te) v alue and M ore t han half o f 8051 s 255 instruct ions manipulate or use accumulator in some way. F or ex a mple, i f y ou want t o a dd n umber 10 20, r esulting 30 w ill be s tore i n Accumulator. O nce y ou h ave a v alue i n A ccumulator y ou may c ontinue processing value or you may store it in anor register or in memory. B ( B Registe r, A ddresses F 0h, Bit-Address a ble) : " B" register i s u sed in t wo instruc t ions: th e m ultiply d ivide o perations. B r egister i s a lso commonly u sed by prog rammers a s a n a uxiliary r egister to temporarily s tore valu e s. T hus, i f y ou w ant t o quickly easily multiply o r d ivide A by a nor n umber, you m ay s tore o r n umber i n " B " m ake u se o f se two instructi on A side from MUL DI V instru c tions, " B" register i s often used as yet anor temporary storage register much like a ninth "R" reg i ster Basic Registers " R" registers: " R" r egisters a se t o f e ight reg isters named R 0 t o R 7. se r egisters u sed a s a uxiliary registers i n many op e rations. To continu e a bove e xample, p erhaps y ou a dding o riginal n umber 10 may b e s tored i n A ccumulator w hereas th e v alue 20 may b e sto red i n, sa y, r egister R 4. T o p rocess a ddition y ou w ould exe cute c ommand: A DD A, R 4 A fter exe cuting thi s i nstruction A ccumulator w ill contain v alue 30. " R" r egisters a lso used t o temporarily store value s. Fo r e xample, l et s s ay yo u w ant t o a dd v alues i n R 1 R 2 toge r n subtract values of R3 an d R4. One way t o do this would be: MOV A, R3; Move value of R3 into accumulat or A DD A, R4; add value o f R4 MOV R5, A; Store resulting value temporarily in R 5 MOV A, R1; Move value of R1 into accumulat or ADD A, R2; Add value of R 2 SUB B A, R5; Subtract value of R5 (which now conta i ns R3 + R 4) A s y ou c an s ee, w e use d R 5 t o temporarily h old th e s um o f R 3 R 4. O f co u rse, t his is n t m ost effi cient way to calcula te ( R1+R2) - ( R3 + R4) but i t does illustr ate use of " R" registers as a way to store values temporarily. Program Counter ( P C ) Prog ram Counter ( P C) i s a 2-by te address w hich t ells 8051 where next i nstruction t o exe cute i s f ound i n m emory. W hen 8051 i s i nitialized P C always s tarts a t 0000h and is incremented each time an instruction is execute d. P C is n t a lways i ncremented by o ne. s ome instruc tions r equire 2 o r 3 bytes PC w ill b e incremented by 2 or 3 in se case s. P rogram C ounter h as n o way t o directly mo dify i ts valu e. B ut if y ou e xecute LJM P 2340h y o u can make PC=2340h. Y ou m ay chang e valu e o f P C (by executing a j ump i nstruction, e tc. ) re i s n o way t o read value of P C. 109

114 4.3 I/O ports and circuit s Each port of 8051 has bidirectional capability. P ort 0 is called ' t rue bidirectional port' a s it floats (tristated) when configure d as input. Port- 1, 2, 3 are called ' quasi bidirectional por t'. Port-0 Pin Structure Port -0 has 8 pins (P0. 0- P 0.7). F ig 4.6 Port-0 Structure Port-0 c an b e config ured a s a n ormal b idirectional I / O por t o r i t c an b e use d a ddress/data i nterfacing accessing ext ernal memor y. W hen c ontrol i s '1', por t i s u sed address/data interfacing. Whe n c ontrol i s '0', th e p ort c an be u sed a s a n ormal b idirectional I/ O por t. L et u s a ssume c ontrol i s '0'. W hen p ort i s u sed a s a n i nput p ort, '1' i s writte n t o l atch. I n this s ituation b oth o utput MOSF ETs ar e ' off '. Henc e o utput pi n flo a ts. T his h igh impedanc e pin c an b e p ulled u p o r l ow by an ext ernal s ource. W hen th e port i s use d a s a n o utput p ort, a '1' w ritten t o l atch again turns ' of f' b oth outp ut MOSF ETs c auses o utput pin to fl oa t. A n ext ernal pull-u p i s requir ed t o o utput a '1'. B ut w hen '0' i s w ritten t o l atch, p in i s pull ed d own by l ower MOS F ET. H ence output b ecomes ze ro. W hen c ontrol i s '1', a ddress/data b us c ontrols th e o utput d river MOSFE T s. I f a ddress/data bus ( internal) is '0', upper MOSFET is ' off' and lower MO SFET is ' on'. o utput b ecomes '0'. I f address/data b us i s ' 1', upper t ransistor is ' on' lo wer t ransistor i s ' off'. H ence th e o utput i s '1'. Hen ce for n ormal a ddress/data interfacing ( for e xternal memory access) no pull- u p resistors are required. Port-0 latch is written to with 1' s when used for external memory a ccess. Port-1 P in Structure Port-1 h as 8 p ins ( P1.1-P1. 7). struc ture of a port-1 p in i s s hown i n f ig below. 110

115 Fig 4.7 Port 1 Str ucture Port-1 d oes n ot h ave any alter nate func tion i.e. i t i s d edicated solely for I / O interfacing. W hen u sed as o utput p ort, p in i s p ulled u p o r d own throu gh inte rnal pull- u p. T o u se port-1 a s i nput p ort, '1' h as t o b e writt en to lat c h. I n t his i nput m ode w hen '1' i s wr itten t o p in by ext ernal d evice n it r ead fin e. B ut w hen '0' i s w ritten t o p in by ext ernal d evice n ext ernal s ource m ust s ink c urrent d ue t o int ernal pull- u p. I f ext ernal d evice i s n ot a ble t o sink c urrent pin volt age may r ise, l eading t o a possible wrong reading. P ORT 2 Pin Structure Port-2 has 8-pins (P2. 0- P 2.7). structure of a port-2 pin is shown in figure be l ow: Fig Port 2 struc ture Port-2 i s u sed highe r ext ernal a ddress byte o r a nor mal input/ out put p ort. I / O operation is similar to Port-1. Port-2 latch remains stable when Port- 2 pin are used for ext ernal m emory a ccess. Here again due to internal pull-up re is limited current driving capability. P ORT 3 Pin Structure Port-3 has 8 pin (P3. 0-P 3. 7). Port-3 pins have alternat e funct ions. structure of a port-3 pin is shown in figu re 111

116 Fi g P ort 3 structure Each pin of Port-3 can be individually programmed for I/ O operation or for alternate funct ion. alternate function can be activated only i f corresponding latch has been w ritten to '1'. To use port as input port, ' 1' shou ld be written to latch. This por t al so has internal pull-up and limited current driving capability. Inte rfacing External Memory I f external program/data memory to be interfaced, y interfaced in following way. F ig 4.10 Circuit Diagram for Interfacing of External Memory External progr am memory i s fetched if eir of following t wo conditions are satisfied. 1. ( Enab le Addre s s) is low. microco ntroller by default starts search ing program from external program memory. 2. PC is hig h er than FFFH for 8051 or 1FFFH for P SEN t ells o utside w orld w her ext ernal memory fetche d i s progra m m emory or data memory. 112

117 Instructi ons 8051 has about 111 instruct ions. se can be gr ouped into following categories 1. Arithmetic In structions 2. Log ical In structions 3. Data Transfer instruct ions 4. B oolean Variable In structions 5. Prog ram Branching In structions following nomenclatures for regi ster, data, address variables are used while write instruc t ions. A: Accumulat or B : " B" regi ster C : Carry b it Rn: Register R0 - R 7 of currently selected regi ster bank Direct: 8-bit internal direct address for data. data could be in lower 128bytes of RAM (00-7 FH) or it could be in special function reg ister (80 - F Ri: 8-bit external or internal RAM address available in reg i ster R0 or R1. T his is used for indirec t addressing m ode. # data8: Immediate 8- b it data available in instruction. # data16: Immediate 16- b it data available in instruction. Addr11: 11-bit destination addres s for short absolute jump. U sed by i nstructions AJMP & ACALL. Jump range is 2 kb y te (one page). Addr16: 16-bit destination addres s for long call or long j ump. Rel: 2's complement 8- bit offset (one - byt e) used for short jump (SJMP) and all conditiona l jumps. b it: Directly a ddressed bit in internal RAM or SFR Arithmetic Instruct ions Mnemonics Descr iption Byt es Instruct ion Cyc les ADD A, Rn A A + R n 1 1 ADD A, direct A A + ( direc t ) 2 1 ADD A A Ri 1 1 ADD A, # dat a A A + dat a 2 1 A DDC A, Rn A A + R n + C 1 1 A DDC A, direct A A + (direc t ) + C 2 1 AD DC R i A A Ri + C 1 1 A DDC A, # dat a A A + + C 2 1 DA A Decimal a djust acc umulator 1 1 DIV AB D ivide A by B A quotien t 1 4 B remainder DE C A A A DE C Rn R n Rn DEC direct ( direc t ) ( dire ct ) D R Ri IN C A A A IN C Rn R n R n INC direct ( dire ct ) ( direct) Ri I NC DP TR DP TR D PTR MUL AB M ultiply A by B A low by t e (A*B)

118 B high by te (A* B) SUBB A, Rn A A - R n - C 1 1 SUBB A, direc t A A - ( dir ect ) - C 2 1 SUBB A A Ri - C 1 1 SUBB A, # dat a A A - da ta - C 2 1 Log ical In structions Mnemonics Descri ption Bytes Instruct ion Cycles A NL A, Rn A A A ND R n 1 1 A NL A, direc t A A AND ( direc t ) 2 1 A NL A A 1 1 A NL A, # dat a A A AND dat a 2 1 A NL direct, A ( direc t ) ( direc t ) AND A 2 1 A NL direct, # dat a ( dire ct ) ( direct) AND dat a 3 2 CLR A A 00H 1 1 C PL A A A 1 1 O RL A, Rn A A OR Rn 1 1 O RL A, direct A A O R ( dire ct ) 1 1 O RL A A 2 1 O RL A, #data A A OR dat a 1 1 O RL d irect, A ( dire ct ) ( direct) OR A 2 1 O RL d irect, #data ( dire ct ) ( direct) OR dat a 3 2 R L A Rotate accumulator left 1 1 RLC A Rotate accumulator left through 1 1 carry R R A Rotate accumula tor righ t 1 1 R RC A Rotate accumulator right through 1 1 carry SWA P A Swap nibbles within Acumulat or 1 1 X RL A, Rn A A E XOR R n 1 1 X RL A, direct A A EXO R ( dire ct ) 1 1 X RL A A EXO Ri 2 1 X RL A, #data A A E XOR 1 1 X RL d irect, A ( direc t ) ( direc t ) EXOR A 2 1 X RL d irect, #data ( direc t ) ( direct) EXOR dat a 3 2 Data Transfer Instructio ns Mnemonics Descri ption Bytes Instruct ion Cycles M OV A, R n A R n 1 1 MOV A, direct A ( dire ct ) 2 1 M OV Ri R i 1 1 M OV A, # data A dat a 2 1 M OV R n, A R n A 1 1 MOV Rn, direct R n ( dire ct ) 2 2 MOV Rn, #dat a R n dat a 2 1 MOV direc t, A ( dire ct ) A 2 1 MOV direc t, Rn ( dire ct ) R n 2 2 MOV dire c t1, ( direc t 1) ( dire ct 2) 3 2 direct 2 114

119 MOV dir ec R i ( direc t Ri 2 2 MOV direct, # dat a ( dire ct ) # dat a 3 2 M Ri, Ri A 1 1 Ri ( direc t ) 2 2 #dat R i dat a 2 1 M OV D PTR, DP TR data # data1 6 M OVC A, A Code byt e pointed by A + DPTR 1 TR M OVC A, A Code byt e pointed by A + PC 1 P C MOVC R i A Code byt e pointed by Ri 8- b it address) 1 2 M OVX A, A E xternal data pointed by D PTR 1 TR M R i, R i A (External data - 8bit addre s s) 1 2 M A PUSH direct ( SP) ( direc t ) 2 TR A(External data - 16bit addre s s) 1 2 POP direct ( direc t ) ( SP) 2 2 XC H Rn Exchange A with Rn 1 1 XCH direct Exchange A with direct byt e 2 1 XC E xchange A with indirect RAM 1 1 X CHD R i Exchange least sign ificant nibble of A with 1 1 that of indirect RAM Boolean Variable Instruct ions Mnemonics Descri ption Bytes Instruc tion Cycles CLR C C-b it CLR bit bit S ET C C S ET b it bit C PL C C 1 1 C PL b it b it 2 1 A NL C, /bit C C. 2 1 A NL C, bit C C. bit 2 1 O RL C, /bit C C O RL C, bit C C + b it 2 1 M OV C, bit C b it 2 1 M OV b it, C bit C

120 Pr ogram B ranching Instructions Mnemonics Descri ption Bytes Instructi on Cycles ACALL a ddr11 P C + 2 ( SP) ; ad dr 11 PC 2 2 AJM P addr11 Addr11 P C 2 2 CJNE A, direct, rel Compare with A, jump (PC + rel) if n ot 3 2 equal CJNE A, #data, rel Compare with A, jump (PC + rel) if n ot 3 2 equal CJNE Rn, #data, rel C ompare with Rn, jump (PC + rel) if n ot 3 2 equal #data, rel Compare A, jump (PC + rel ) if 3 2 not equal D JNZ Rn, rel Decrement Rn, jump if n ot zero 2 2 D JNZ d irect, rel Decrement (direct), jump if not zero 3 2 J C rel Jump ( PC + rel) if C bit = JN C rel Jump ( PC + rel) if C bit = J B b it, rel Jump ( P C + rel) if bit = J NB bit, re l Jump ( P C + rel) if bit = JBC bit, rel Jump ( P C + rel) if bit = A+ DP TR PC 1 2 J Z r el I f A=0, jump to PC + rel 2 2 J NZ r el I f A 0, jump to PC + rel 2 2 LC ALL a ddr16 P C + 3 ( SP), addr1 6 PC 3 2 LJMP add r 16 Addr 16 P C 3 2 NOP No operation 1 1 RET ( SP) P C 1 2 RETI ( SP) P C, Enable Interru pt 1 2 SJMP rel PC rel PC 2 2 J A+DPTR A+ DPT R PC 1 2 JZ rel I f A = 0. jum p PC+ re l 2 2 JNZ rel If A 0, jum p P C + re l 2 2 NOP No operation Addressing Modes 8051 has four addre s sing modes. 1. I m mediate Addressing: D ata is immediately a vailable in instruct ion. F or example - ADD A, #77; Adds 77 (decimal) t o A and stores in A ADD A, #4DH; Adds 4D (hexadeci mal) to A and stores in A MOV DPTR, #1000H; M oves 1000 (hexadecimal) to data pointer 2. Ba nk Addressing or Reg i ster Addressing: T his way of addressing accesses bytes in current regi ster bank. Data i s available in regi ster specified in instruction. register bank is decided by 2 bits of Processor Stat us 116 Dept. of ECE

121 Word (PSW). For example- ADD A, R0; Adds content of R0 to A and stores in A 3. Direct Addressing: address of data is available in instruct ion. F or example - MOV A, 088H; Moves conten t of SFR TCO N ( addres s 088H)to A 4. Reg ister Indirect Addre s sing: address of data is available in R0 or R1 registers as specified in instruc t ion. For example - MOV moves content of ad dress pointed by R 0 to A. 5. External Data Addressing: Pointer used for external data addressing can be eir R0/R1 (256 byt e access) or DPTR ( 64kby t e access). F or example - MOVX Moves content of 8-b it address pointed by R 0 to A MOVX Moves content of 16-b it address pointed by D PTR to A 6. External Code Addressing: S ometimes we may want to store non-v olatile data into ROM e. g. look-up table s. Such may require reading code memory. T his may be done as follows - M OVC Moves content of address pointed by A +DPTR to A MOVC Moves content of addres s pointed by A +PC to A 4.6 Assembly language Programming Character transmission using a time delay: A program shown below takes character in 'A' register, transmits it, delays for t ransmission time, and returns to calling program. Timer-1 is used to set bau d rate, which is 1200 baud in this program delay for one character transmission (in Mo de 1 i.e.10 bits) is 10/2400 = seco nds Or, 8.33 milliseco nds H ence software delay o f 10ms is used. Timer- 1 generates a baud rate close t o Using a 12MHz crys tal, reload value is O r, 230 i. e. E 6H. This gi ves rise to an actual b aud rate of SMOD is programmed to be 0. A ssembly l anguage Program is as follows 117 Dept. of ECE

122 ; Code to wait for tra nsmission to complet e subroutine TRMITTIM E generates a delay o f about 10ms. W ith a clock of 12MHz, one instruction cyc le time is loop "MILSEC" generates a delay of about 1 x 10-3 a total delay of 10 x 10 s ec or 10ms -3 s ec. This gets execu ted 10 times U NIT V I NTERFACING MIC 5.1 Programming 8051 Timers: Using Timers to Measure Time O ne of primary u ses of timers is to measure time. W hen a t imer i s i n i nterval t imer m ode ( as o pposed t o e vent c ounter m ode) correctly c onfigured, i t w ill i ncrement b y 1 every ma chine c y cle. A s ingle machin e cy cle c onsists o f 12 crys tal pulses. T hus a running timer will b e incremented:11,059,000 / 12 = 921,583 t imes per se co nd. 118 Dept. of ECE

123 U nlike i nstructions w hich r equire 1 machine c y cle, o rs 2, ors 4-- t imers c onsistent: y w ill alway s b e i ncremented o nce p er m achine cycl e. Th us i f a t imer h as counted from 0 to 50,000 you may c alculate: 50,000 / 921,583 = s econds h ave pas s ed. T o e xecute a n event o nce p er sec ond you d have to wait for timer to count from 0 to 50, time s. T o calculate h ow many t imes t imer will b e increme nted i n. 05 s e conds, a simple multiplication can be done : 0.05 * 921,583 = 46, T his tells us that it will take.05 seconds (1/20th of a second) to count from 0 to To work with timers is to control timers and in i tialize m. TMOD SFR T MOD ( Timer Mod e ): T MOD S FR i s used t o c ontrol m ode o f o peration o f both time rs. E ach b it o f S FR g ives microc ontroller s pecific information concerning h ow t o r un a t imer. hig h f our b its ( bits 4 t hrough 7 ) re late t o T imer 1 whereas l ow four b its ( bits 0 t hrough 3 ) pe rform exa ct s ame f u nctions, b ut time r 0. m odes of opera tion are: TxM1 TxM0 Table 5.1 modes of Timer Timer Mo de Descr iption of Mo de bit Time r bit Timer bit auto-reload bit Time Mode ( mode 0) T imer m ode " 0" i s a 13-b it t imer. W hen t imer i s i n 13-b it m ode, TLx w ill c ount 0 t o 31. W hen TLx i s incremented 31, i t wil l " reset" t o 0 and increme nt THx. T hus, effectivel y, o nly 13 b its o f t wo t imer byte s are b eing u sed: b its 0-4 o f TLx b its 0-7 o f THx. t imer c an only conta in 8192 value s. I f y ou s et a 13-b it tim er t o 0, it w ill overflow back to zero 8192 machine cy c les later. 16-bit Tim e Mode ( m o de 1) T imer m ode "1" i s a 16-b it t imer. T Lx i s i ncremented 0 t o 255. W hen TLx i s i ncremented from 255, it resets t o 0 c auses THx t o b e incre mented by 1. Since t his i s a fu ll 16-b it t imer, t imer may c ontain u p t o d istinct v alues. I f y ou s et a 16-b it t imer to 0, it will overflow back to 0 after 65,536 machine cycle s. 8-bit Tim e Mode ( m o de 2) T imer mode "2" is an 8-bit auto-reload mode. Wh en a t imer i s i n m ode 2, THx h olds " reload v alue" TLx is th e ti mer itsel f. T hus, T Lx s tarts c ounting u p. W hen T Lx r eaches 255 i s subsequently in c remented, i nstead o f r esetting t o 0 ( as i n c ase o f m odes 0 1 ), i t w ill b e r eset t o v alue s tored i n THx. F or exa mple, i f T H0 hold s v alue FDh TL 0 h olds value F Eh valu es o f TH 0 TL0 for a few machine cy c les: value of TH0 never changed. When we use mode 2 you almost always set THx to a known value and TLxis SFR that is constantly incremente d. benefit of auto-reload m ode is timer always have a value from 200 t o 255. If you use mode 0 or 1, yo u d hav e to check in code to see if timer had overflowed and, if so, reset timer to 200. T his takes precious instructions of execution time to check value and/ or to reload it. When 119 Dept. of ECE

124 Table 5.2 mode 2 operati on Mach ine Cycl e T H0 Value T L0 Value FDh FE h FDh FFh FDh F Dh FDh FE h FDh FFh FDh F Dh FDh FE h y ou use m ode 2 micro controller take s care o f t his. Auto-r eload mode is very commonly used for establishing a baud rate in Serial Communic at ions. Split Timer Mode (mode 3 ) T imer m ode " 3" i s a split-ti mer m ode. W hen T imer 0 i s p laced i n m ode 3, i t essentially b ecomes t wo separa te 8-b it t imers. T imer 0 i s T L0 T imer 1 is T H0. B oth t imers c ount 0 t o 255 overflo w b ack t o 0. A ll bits r elated t o Time r 1 will n ow b e t ied t o T H0. While T imer 0 i s i n s plit m ode, r eal T imer 1 ( i.e. T H1 T L1) c an b e p ut i nto m odes 0, 1 o r 2 normally--ho w ever, y ou m ay n ot s tart o r s top real tim er 1 sin ce th e b its d o th at are now l inked t o T H 0. r eal ti mer 1, e, w ill b e incremented every ma chine c ycle alwa y s. only r eal u se i n s plit t imer m ode i s i f y ou n eed t o h ave t wo s eparate t imers, additionally, a ba ud r ate g enerator you c an u se r eal Timer 1 as a baud rate generator and use TH0/TL0 as two separate time r s. Reading Time r Th ere t wo c ommon way s o f rea ding va lue o f a 16-b it t imer; w hich you u se de pends o n y our s pecific applicat i on. Y ou m ay e ir read a ctual value o f t imer a s a 16-b it number, or you may simply d etect when timer has overflowed. Reading va lue of a Time r I f timer i s i n an 8-b it m ode eir 8-b it A uto R eload m ode or in split t imer m ode, y ou s imply r ead 1-by te va lue o f timer. W ith a 13-b it or16-b it t imer t imer v alue w as 14/255 ( High by te 14, l ow b yte 255) b ut y ou read 15/255.Becaus e y ou r ead l ow by te a s 255. B ut w hen y ou e xecuted n ext i nstruction a s mall a mount o f t ime passed--b ut enoug h for timer to increment again at which time value rolled over from 14/ 255 to 15/ 0. Bu t i n process yo u ve r ead timer as being 15/255. Y ou r ead hig h by te of t imer, n r ead l ow by te, n re ad hi gh by te a gain. If h igh by te r ead sec ond t ime i s n ot same a s hig h byte r ead th e f irst time y ou repeat cycle. In code, this w ould appe ar a s : REPEAT: MOV A, TH0 MOV R0, TL0 C JNE A, TH0, REPEAT I n this case, we load accumulator with hig h byte of T imer 0. We n load R0 l ow by te o f Time r 0. Finall y, w e check t o s ee i f hig h byte we r ead o ut o f Timer 0--w hich i s n ow s tored in Accumulator--i s s ame a s cur rent Tim er 0 hig h b y te. W e d o by going back t o R EPEAT. W hen l oop exi ts w e w ill have l ow byte o f timer in R0 and high by t e in Accumulator. A nor much s impler al ternative i s t o simply tur n o ff timer run bi t ( i.e. CLR TR0), read timer value, and n turn on time r run bit (i. e. S ETB TR0). Detecting Time r Overf low 120 Dept. of ECE

125 W henever a t imer overflo ws i ts h ighest v alue b ack t o 0, microcontrolle r automatically s ets TFx b it i n T CON regi s ter. i f T F1 i s s et i t mean s th at t imer 1 h as overflow ed. W e c an u se t his a pproach t o c ause p rogram t o exe cute a fixe d d elay. i t t akes /20thof a s econd t o c ount from 0 t o 46,079. H owever, T Fx f lag is s et w hen t imer o verflows b ack t o 0. T hus, i f w e w ant t o use TFx f lag t o indicate w hen 1 /20th o f a s econd h as p assed w e mu st s et t imer initially t o l ess 46079, o r 19,457. I f w e s et timer to 19,457, 1/20th of a second later timer will overflow. following code to execute a pause of 1/20th of a se co nd: MOV TH0,#76;High by t e of 19,457 (76 * 256 = 19,456) MOV TL0,#01;Low by t e of 19,457 (19, = 19,457) MOV TMOD,#01;Put Timer 0 in 16-b it mode SETB TR0; Make Timer 0 sta rt co unting JNB TF 0,$ ; If TF0 is not set, jump back to this same instruct ion I n above c ode firs t t wo l ines initialize T imer 0 starting v alue to 19,457. n ext t wo i nstructions config ure timer 0 tu rn i t o n. Finall y, l ast i nstruction JNB T F0, $, r eads "J u mp, i f TF0 i s n ot s et, back to t his s ame instructi on." "$" operand m eans, i n m ost a ssemblers, addr ess of curr ent instruct io n. T hus a s l ong a s timer h as n ot o verflowed T F0 b it h as n ot been s et progra m w ill ke ep exe cuting this s ame i nstruction. A fter 1 /20th o f a s econd t imer 0 w ill o verflow, se t T F0 b it, and program execution will n break out of l oop. 5.2 Serial P ort Programming: 8051 Serial Commu nication O ne o f 8051 s many powe rful f eatures -integ rated UA RT, k nown a s a seria l p ort t o e asily r ead w rite valu es t o s erial p ort i nstead o f t urning o n of f o ne o f I/O l ines in rapid succession to properly " clock out" ea ch i ndividual b it, i ncluding s tart b its, s top bits and parity b its. S etting S erial P ort M ode c onfigures i t b y specify ing 8051 h ow many b its w e w ant, b aud r ate w e w ill b e u sing h ow b aud r ate w ill b e d etermined. Fir s t, l et s p resent " Serial C ontrol" ( SCON) SFR d efine wha t e ach b it o f SF R represe n ts: Table 5.3 Definition of SCON SFR Bit Name 7 S M0 6 S M1 5 S M2 4 R EN 3 TB8 2 RB8 1 T 1 0 RI B it Addres s 9Fh 9 Eh 9 Dh 9 Ch 9 Bh 9AH 99h 98h Explanation of Fu nction Serial port mode b it 0 Serial port mode b it 1. Mutli processor Communicat ions Enable Receive r Enable. T his bit must be set in order to recei ve Character s. Tran smit bit 8. 9th bit to transmit in mode 2 a n d 3. Receive b it 8. 9th bit received in mode 2 a n d 3. Tra nsmit Flag. S et when a byte has been completely Transmitted. Rece ive Flag. S et when a byte has been completely Receive d. Additionally, it is necessary to define function of SM0 and SM1 by a n additional table: T able 5.4 S CON as serial Port 121 Dept. of ECE

126 Table 5.4 Modes of SCO N SM0 SM1 Ser ial Mo de Explanation Baud Rate bit Shift Register Oscillator / bit UART Set by T imer 1 (*) bit UART Oscilla t or / 32 (*) bit UART Set by T imer 1 (*) S CON S FR a llows u s t o c onfigure Seria l Port. f irst f our bi ts ( bits 4 through 7) are config u ration bits: B its S M0 S M1 i s t o s et s erial m ode t o a v alue b etween 0 3, inclu sive a s i n t able a bove selecting S erial M ode se lects m ode o f o peration (8- bit/ 9- b it, UART o r S hift R egister) a lso d etermines h ow b aud r ate w ill b e calculated. I n m odes 0 and 2 baud rate is fixed based on oscillator s frequency. I n mode s 1 and 3 ba ud rate i s variable based on how often Timer 1 ove r flows. next b it, SM2, i s a f lag " M ultiprocessor c ommunication whenever a by te h as be en r eceived 8051 w ill s et "R I " ( Receive I nterrupt) f lag t o l et p rogram k now a byte has been received and that it needs to be processe d. H owever, w hen S M2 i s s et "R I " f lag w ill only b e t riggered i f 9 th b it r eceived w as a " 1". i f S M2 i s s et a byte i s receive d wh ose 9 th b it i s c lear, RI f lag wil l never b e s et. You wil l a lmost a lways wa nt t o c lear t his b it s o f lag i s s et u pon r eception of a ny character. next bi t, REN, i s " Receiver E nable." i s set i ndicate t o received v ia seria l port. l ast f our b its ( bits 0 t hrough 3 ) o perational b its. y u sed w hen actually sending and receiving data--y are not used to config u re serial port. TB8 b it i s u sed i n m odes 2 3. I n mod es 2 3, a tota l o f n ine b its are transmitte d. f irst 8 da ta b its 8 b its o f m ain valu e, an d ninth b it is ta ken T B8. I f TB 8 i s s et a v alue i s writte n t o s erial p ort, da ta s bits w ill b e w ritten t o s erial l ine f ollowed by a " set" n inth b it. I f T B8 i s c lear n inth bit wi ll b e " clea r. " R B8 a lso o perates in m odes 2 an d 3 and func tions essentially s ame way a s T B8, b ut o n r eception s ide. W hen a b yte i s r eceived i n m odes 2 o r 3, a t otal o f n ine b its r eceived. I n t his c ase, f irst e ight b its receiv ed o f se rial by te r eceived v alue o f nine th b it r eceived will b e p laced in RB 8. T I m eans " Transmit I n terrupt. " W hen a p rogram w rites a v alue t o s erial p ort, a c ertain a mount o f t ime w ill pas s before individual bits of by te " clocked o ut" s erial p ort. I f p rogram w ere t o w rite a nor byte t o s erial p ort b efore f irst byte w as completely o utput, b eing s ent w ould b e garb l ed. T hus, 8051 l ets p rogram k now i t h as " clocke d o ut" last byte by setting TI b it. W hen T I b it i s s et, progra m may assume s erial p ort i s " free" ready t o s end n ext b y te. F inally, R I b it m eans " Receive I nterrupt. " I t f unctions similarly t o " TI" b it, b ut i t i ndicates a byte h as be en receiv e d. W henever 8051 has received a complete b yte it will trigger RI bit to let program know that it needs t o read value quickly, before anor by t e is read. S etting Serial Port Baud Rate O nce Serial Port Mode has been confi gured, prog ram must configu re serial port s b aud r ate. T his only app lies t o S erial Po rt mode s 1 and 3. B aud R ate i s dete rmined b ased o n oscilla tor s frequency w hen i n mod e 0 and 2. In m ode 0, b aud rate is 122 Dept. of ECE

127 alway s osc illator frequency d ivided by 12. T his m eans i f y ou r e cryst al i s M hz, m ode 0 b aud r ate w ill alway s b e 921,583 baud. I n m ode 2 baud r ate i s alway s o scillator frequency d ivided b y 64, s o a M hz c rystal s peed w ill yie ld a b aud r ate of 172,797. I n m odes 1 3, ba ud r ate is deter mined by h ow frequently t imer 1 o verflows. m ore f requently t imer 1 o verflows, highe r th e b aud r ate. re m any way s o ne c an cause timer 1 to overflow at a rate that determine s a baud ra te, but most c ommon method i s t o p ut t imer 1 i n 8-b it auto-r eload m ode ( timer m ode2) s et a r eload v alue ( TH1) causes Timer 1 to overflow at a frequency a ppropriate to generate a baud rate. To determine value that must be placed in TH1 to g enerate a given baud rate, ( assuming P CON.7 is clear). TH1 = ((Cry stal / 384) / B au d) I f P CON. 7 i s s et n b aud r ate i s effectively d oubled, th us e quation become s : TH1 = ((Cry stal / 192) / B au d) F or ex a mple, i f w e ha ve a n M hz crysta l an d w e w ant t o configure seria l port to 19,200 baud we try plugging i t in first equation: TH1 = ((Cry stal / 384) / B au d) TH1 = (( / 384) / 19200) TH1 = (( 28,799) / 19200) T H1 = = To obtain 19,200 baud on a Mhz crystal we d have t o set T H1 t o I f we set it t o 254 w e w ill h ave achieve d 14,400 b aud i f we s et i t t o 255 w e w ill have achieve d 28,800 b aud. T o achieve 19,200 baud w e simply ne ed to s et PC ON. 7 ( SMOD). Wh en w e do t his we double baud rate and utilize second equation mentione d above. Thus we have: TH1 = ((Cry stal / 192) / B au d) TH1 = (( / 192) / 19200) T H1 = (( 57699) / 19200) T H1 = = 253 refore, to obtain 19,200 baud with an MHz crystal we m ust: 1) Configure Serial Port mode 1 or 3. 2) Configure Timer 1 to timer mode 2 ( 8-bit auto reloa d ). 3) Set TH1 to 253 to reflect correct frequency for 19,200 ba u d. 4) Set PCON.7 (SMOD) to double baud rate. Writing to Serial Port O nce S erial P ort h as b een properly configur ed a s exp lained a bove, s erial p ort i s ready to be used to send data and receive data. T o w rite a by te t o se rial w rite va lue t o SBU F ( 99h) S FR. F or e xample, i f you w anted to send letter "A" to serial port, it could be accomplished as easily a s : MOV SBUF, # A U pon exe cution o f a bove i nstruction 8051 w ill b egin t ransmitting charac ter v ia s erial po r t. O bviously t ransmission i s n ot instantaneous--i t take s a measureable a mount o f t ime t o t ransmit. And s ince 8051 doe s not h ave a se rial o utput buff er w e need t o b e sure that a character is completely t ransmitted before we try to transmit next chara ct er l ets u s k now w hen i t i s don e t ransmitting a chara cter by se tting T I b it i n SC O N. W hen t his b it i s s et l ast c haracter ha s b een t ransmitted s end next character, if any. C onsider following code se gment: CLR TI; Be sure bit is initially c lear MOV SBUF, # A ; Send letter A to serial port JNB TI, $;Pause until RI b it is set. 123 Dept. of ECE

128 a bove t hree instruc tions w ill successfully trans mit a charac ter w ait TI b it t o be set before continuing. last instruction says "Jump if TI b it is not set to $ " $, i n m ost a ssemblers, m eans " same address o f c urrent instructi o n. " T hus 8051 w ill p ause o n JN B instruction u ntil T I b it i s s et by 8051 u pon s uccessful transmission of characte r. Reading Se rial Po rt R eading r eceived by s erial p ort i s equally eas y. T o r ead a by te fro m seria l p ort o ne j ust n eeds t o r ead v alue s tored i n SBU F ( 99h) S FR afte r 8051 h as automatically set R I flag i n SCON. F or ex a mple, i f y our prog ram w ants t o w ait a c haracter t o be r eceived subsequently read it into Accumulator, following code segment may be use d : JNB RI, $;Wait for 8051 to set RI f lag MOV A,SB UF; Read character from serial port f irst line of above c ode s egment w aits 8051 t o s et RI fla g ; a g ain, 8051 s ets RI f lag automatically when i t receives a c haracter v ia seria l p o rt. S o a s long a s b it i s n ot s et p rogram repea ts "J N B" ins truction continuousl y. O nce RI b it i s s et u pon c haracter recepti on a bove c ondition automatically f ails p rogram f low f alls throug h to " MOV" instruction which reads value. 5.3 Interrupt Programm i ng: What Events Can Trigger interrupts, and whe re do y go? following events will cause an interr u pt: Time r 0 Overf l ow. Time r 1 Overf l ow. Reception/Transmission of Serial Characte r. External Eve n t 0. External Eve n t 1. T o d istinguish b etween v arious i nterrupts e xecuting dif ferent code depending o n w hat in terrupt w as t riggered 8051may b e jumping t o a fixe d a ddress w hen a g iven i nterrupt occur s. Table 5.5 Interrupt hand ling Interru pt Fl ag Interrupt Handle r Addres s External 0 IE0 0003h T imer 0 TF0 000Bh External 1 IE1 0013h T imer 1 TF1 001Bh Serial RI/ TI 0023h I f T imer 0 o verflows ( i.e., T F0 b it i s s et), m ain progra m w ill b e temporarily s uspended and c ontrol wi ll j ump t o 000BH i f w e h ave code a t address 0003H th at handle s situation of Timer 0 overflowing. Setting Up Interrupts B y d efault a t p ower u p, a ll i nterrupts d isabled. E ven i f, ex a mple, T F0 b it i s s et, 8051 will not execute interru pt. Your program must specifically t ell 8051 i t w ishes t o e nable i nterrupts specifically w hich interr upts i t w ishes t o e nable. Your program may enable and disable interrupts by modify i ng IE SFR (A8h): 124 Dept. of ECE

129 E C6504 MICROPROCESSOR & MIC T able 5.6 I nterrrupt and address B it Name B it Add res s Explanatio n of Fu nction EA AFh Global In terrupt Enable/Disable AE h Undefined ADh Undefined E S AC h Enable Serial Interru pt ET1 ABh Enable Timer 1 Interru pt EX1 AAh Enable External 1 In terrupt ET0 A9h Enable Timer 0 Interru pt EX0 A8h Enable External 0 In terrupt Ea ch o f 8051 sinterrupts h as i ts o wn b it i n I E S FR. Y ou e nable a g iven i nterrupt by s etting corresponding b it. For e xample, i f y ou w ish t o e nable Timer 1 I nterrupt, y ou would exec ute ei r: MOV I E,#08h SETB E T1 B oth o f a bove i nstructions s et b it 3 o f I E, t hus e nabling T imer 1 Interru p t. O nce T imer 1 I nterrupt i s enabl e d, w henever TF 1 bi t i s s et, 8051 w ill automatically p ut " on hold" m ain progra m exe cute T imer 1 I nterrupt Handler a t ad dress 001Bh. However, b efore T imer 1 I nterrupt ( or any o r i nterrupt) is truly e nabled, y ou m ust a lso s et b it 7 o f I E. B it 7, G lobal Inter rupt Enable/Disabl e, en ables o r d isables a ll interrupts simultaneously. That i s to sa y, i f b it 7 i s c leared th en n o interrupts w ill oc c ur, e ven if al l o r b its o f I E s et. S etting b it 7 w ill e nable a ll i nterrupts h ave b een selecte d by s etting o r b its i n I E. T his i s u seful i n prog ram exe cution i f y ou ha ve time-c ritical code n eeds t o ex e cute. I n t his c ase, y ou may n eed c ode t o e xecute s tart t o f inish out any i nterrupt gett ing in way. T o accom plish t his y ou c an simply c lear b it 7 of I E ( CL R EA) and n set it after y o ur time critical code is done. To enable Timer 1 Interrupt execute following two instruc t ions: SETB ET 1 SETB EA reafter, T imer 1 I nterrupt H andler a t 01Bh w ill automatically b e call ed wheneve r TF1 bit is set (upon Timer 1 over flow). Polling Sequence 8051 automatically e valuates w her a n i nterrupt s hould o ccur afte r every instru c tion. When checking for interrupt conditions, it checks m in following orde r: 1 ) External 0 Interru pt 2) Timer 0 Interru pt 3) External 1 In terrupt 4) Timer 1 Interru pt 5) Seria l Inter rupt Interrupt Priorities 8051 o ffers t wo leve ls o f i nterrupt priorit y : h igh l ow. B y u sing in terrupt p riorities y ou may a ssign hig her priority t o c ertain interrupt c onditions. F or e xample, y ou may h ave e nabled T imer 1 I nterrupt w hich i s a utomatically c alled every t ime Tim er 1 overflows. A dditionally, y ou may h ave enable d S erial I nterrupt w hich i s c alled every t ime a c haracter i s receive d v ia s erial p ort. H owever, y ou may c onsider r eceiving a c haracter i s m uch m ore i mportant t han t imer i nterrupt. I n t his c ase, i f T imer 1 I nterrupt i s already e xecuting y ou m ay w ish se rial i nterrupt i tself i nterrupts T imer 1 Inter r upt. When seria l i nterrupt i s c omplete, c ontrol p asses b ack t o Tim er 1 Interrupt 125 Dept. of ECE

130 f inally b ack t o m ain p rogram. Y ou may accom plish t his by assigning a h igh priority t o Serial Interrupt and a low priority to Timer 1 I n terrupt. Interrupt priorities are controlled by IP S FR (B8h). IP SFR has following forma t : Bit Name Bit Address Explanation o f Functi on 7 Undefined 6 Undefined 5 Undefined 4 PS BCh Serial In terrupt Priority 3 PT1 B Bh Timer 1 In terrupt Priority 2 P X1 BAh External 1 Interrupt Priority 1 PT0 B9h Timer 0 Interrupt Priori ty 0 P X0 B 8h External 0 Interrupt Priority When considering interrupt priorities, following rules apply: N othing c an i nterrupt a high-priority interrupt--n ot e ven a nor hig h priority inter r upt. A high-priority interrupt may i nterrupt a low priority i nterrupt. A low-priority interrupt may only occur if no or interrupt is already e xecuting. I f t wo i nterrupts o ccur a t s ame t ime, i nterrupt wit h h igher priority w ill e xecute f irst. I f b oth i nterrupts o f s ame priority interrupt w hich i s serviced first by p olling sequence will be executed first. What Happens When an Interrupt Occur s? W hen a n i nterrupt i s trigge r ed, f ollowing actions take n automatically by microcontrolle r: current Program Counter is saved on stack, low-by t e first. Interrupts of same and lower priority are blocke d. In case of Timer and External interrupts, corresponding i nterrupt flag is se t. Program execution transfers to corresponding interrupt handle r vector addre s s. I nterrupt H andler R outine ex e cutes. T ake s pecial n ote o f thir d s tep: I f interrupt b eing h andled i s a T imer o r Ext ernal i nterrupt, m icrocontroller a utomatically c lears i nterrupt f lag b efore p assing c ontrol t o y our interrup t h andler routine. What Happens When an Interrupt E nds? A n i nterrupt e nds w hen y our p rogram executes R ETI i nstruction. W hen RETI instruction is executed following actions are taken by microcontroller: T wo b ytes p opped o ff s tack i nto P rogram Cou nter t o r estore n ormal program exe cu tion. Interrupt status is restored to its pre-interrupt sta t us. Serial Interrupts S erial I nterrupts slightly d ifferent tha n res t o f interrupt s. This i s d ue t o fac t re t wo i nterrupt f lags: RI T I. If e ir f lag i s s et, a s erial i nterrupt is trigger ed. A s y ou w ill r ecall s ection o n s erial p ort, RI b it i s s et w hen a byte i s r eceived by se rial p ort TI b it i s s et w hen a by te h as be en sen t. T his m eans w hen yo ur s erial i nterrupt i s e xecuted, i t m ay h ave b een t riggered because RI f lag w as s et o r b ecause TI f lag w as set--o r b ecause bot h f lags w ere s et. T hus, y our r outine m ust c heck s tatus o f se f lags t o d etermine wha t a ction i s a ppropriate. A lso, s ince 8051does n ot automatically c lear RI TI fla gs y ou m ust c lear th ese b its i n y our interrupt handle r. INT_SERIAL: JNB RI, CHECK_ TI; If RI f lag is not set, we jump to check TI MOV A, SBUF ; I f we got to this line, it s because RI bit * was * set CLR RI; Clear RI b it after we ve processed it CHECK_TI : JNB TI, EXIT_INT; If TI flag is not set, we jump to exit poi nt CLR TI; Clear TI b it before we send anor character 126 Dept. of ECE

131 MOV SBUF, # A ; Send anor character to serial port EXI T_ IN T: RETI A s y ou c an s ee, o ur code c hecks s tatus o f bot h interrupts fla g s. I f both f lags we re s et, b oth s ections o f c ode w ill b e ex e cuted. A lso n ote e ach s ection o f c ode clea rs i ts cor responding i nterrupt f lag. I f y ou get t o c lear i nterrupt b its, s erial i nterrupt w ill b e e xecuted over ove r u ntil y ou clear bi t. T hus i t i s very i mportant you alway s clear interrupt flags in a serial interr u pt. Important Interrupt Consideration: Regist er Protecti on O ne very importa nt r ule a pplies t o a ll i nterrupt ha n dlers: I nterrupts m ust l eave processor i n s ame s tate a s i t w as i n when th e interrup t initiat e d. R emember, i dea be hind interrupts is main program i sn t a ware tha t y ar e e xecuting i n th e "backg round." However, consider following code: C LR C; Clear carry MOV A, #25h; Load accumulator 25h ADDC A, #10h; Add 10h, with carry After above three instructions are executed, accumulat or w ill conta in a value o f35h. B ut w hat w ould h appen i f r ight af ter MOV i nstruction a n i nterrupt occu r red. D uring this i nterrupt, carry b it wa s s et value o f a ccumulator w as chang ed t o 40h. Wh en i nterrupt f inished and c ontrol was passed b ack t o main progr a m, ADDC w ould add 10h to40h, and additionally add an additional 1h because carry bit is set. I n this c as e, a ccumulator w ill con tain v alue 51h a t e nd o f executi o n. I n th is c ase, m ain p rogram h as seemingly cal culated w rong a nswer. H ow c an25h + 10h y ield 51h a s a r esult? I t d oesn t m ake sense. A prog rammer w as u nfamiliar i nterrupts w ould be c onvinced micro controller w as dama ged i n s ome w ay, provokin g p roblems mamatical calculat ions. What has happened, in reality, is interrupt did not protect reg i sters it used. T o i nsure v alue o f a ccumulator i s s ame a t e nd o f i nterrupt a s i t w as at b eginning. T his i s generally accomplished a P USH and P OP s equ ence. Fo r example: PUSH AC C P USH P SW MOV A, #0FFh AD D A,#02h POP PSW P OP A CC g uts o f i nterrupt i s M OV i nstruction A DD i nstruction. H owever, se t wo i nstructions m odify Accumul ator ( M OV i nstruction) a lso m odify value o f carry b it ( ADD i nstruction w ill cause carry b it t o be set). S ince a n i nterrupt r outine m ust g uarantee r egisters remain unchang ed by ro u tine, r outine p ushes orig inal va lues o nto stack u sing th e P USH i nstruction. I t i s th en f ree t o use registers it protected to its heart s content. Once interrupt has finished its tas k, it pops o riginal v alues b ack i nto r egisters. W hen i nterrupt ex i ts, m ain p rogram w ill n ever k now d ifference b ecause registers exactly s ame a s y were b efore inter rupt execute d. I n general, your interrupt routine must protect following registe r s: P SW DPTR (DPH/DPL) P SW A CC B Registers R0-R Dept. of ECE

132 P SW c onsists o f many i ndividual b its s et by va rious 8051instructions. Always p rotect P SW by pushing popping i t o ff s tack a t beginning e nd of y our inter r upts. I t will not be allow to execute instruction: P USH R0 B ecause depending o n w hich register b ank i s s e lected, R 0 may r efer t o eith er interna l r am a ddress 00h, 08h, 10h, or 18h.R0, i n o f itsel f, is n ot a valid memory a ddress P USH P OP instructio ns c an u se. T hus, i f you using any " R" r egister i n y our i nterru pt routine, y ou will have to push register s a bsolute address onto stack i nstead of just say ing PU SH R0. For example, instead of PUSH R0 yo u would execute: PUSH 00h 5.4 Interfacing a Microprocessor to Keyboard W hen you p ress a key o n your c ompute r, you activating a s witch. re m any d ifferent way s o f m aking se switches. A n o verview o f c onstruction operation of some of most common ty p es. M echanical k ey s witches: I n mechanical-s witch k eys, t wo p ieces o f m etal p ushed t oger w hen y ou p ress ke y. a ctual s witch e lements are o ften made o f a phosphor-b ronze a lloy g old p latting o n c ontact are a s. k ey s witch usually contai ns a spring t o retur n key t o n onpressed p osition perhaps a s mall piece o f foam to help damp out bouncing. S ome m echanical key sw itches n ow c onsist o f a m olded s ilicon d ome a s mall p iece o f c onductive rubbe r foa m s hort two trac e o n printed-c ircuit boa rd t o produce key pressed signa l. M echanical s witches relatively i nexpensive bu t y h ave severa l d isadvantages. F irst, y s uffer c ontact b ounce. A p ressed k ey may m ake br eak c ontact s everal times before it make s solid contac t. S econd, c ontacts ma y be come oxidize d o r dirty a ge s o y no l onger make a dependable conne ct ion. Higher- quality m echanical s witches typically h ave a r ated l ife t ime o f a bout 1 million keys trokes. silicone dome type typically last 25 million key s trokes. Memb rane k ey s witches: se s witches really a specia l ty pe of m echanical switches. y consist of a three-lay e r plastic or rubber sandwich. t op lay er ha s a cond uctive l ine o f s ilver ink r unning unde r ea ch key p osition. bottom layer has a conductive line of silver ink running under each column of key s. Fig.5.1 Mechanical key and its response to key pres s key boa rd interfac ed i s a matrix key board. T his k ey board i s desig ned with a p articular r ows c olumns. se r ows colum ns conne cted t o m icrocontroller t hrough i ts p orts o f m icro c ontroller W e normally u se 8 * 8 matrix k ey bo a rd. S o only two ports of 8051 can be easily c onnected to rows and columns of key board. W henever a key i s pr e ssed, a r ow a c olumn g ets s horted throug h tha t p ressed k ey a ll o r keys ar e l eft o pen. W hen a k ey i s p ressed only a bit i n p ort g oes h igh w hich i ndicates microcontroller ke y i s p r essed. By t his hig h o n b it key i n corresponding c olumn is identifie d. O nce w e sure o ne o f key i n key board i s pressed next o ur a im i s t o i dentify key. T o d o t his w e firstly c heck pa rticular r ow n w e che ck th e corre sponding column key boa rd. 128 Dept. of ECE

133 EC6504 MIC ROPROCESSOR & MIC To check row of pressed key in keybo ard, one of row is made high by making one of bit in output port of 8051 hig h. This is done until row i s found out. O nce w e g et r ow next o ut j ob i s t o f ind out c olumn of pressed ke y. c olumn i s detecte d by con tents i n i nput p orts h elp of a counte r. c ontent of input port is rotated with carry until carry b it is set. c ontents o f coun ter i s n c ompared and d isplayed i n display. T his display i s d esigned u sing a seve n segme nt d isplay a B CD t o s even s egment decod er I C B CD e quivalent n umber o f c ounter i s s ent t hrough o utput p art o f 8051 d isplays n umber of pressed key. F ig 5.2 Interfacing Keyboard to 8051 Microc ontroller Fi g. 5.3 Interfacing To Alphanume ric Displays T o g ive d irections o r v alues t o us e rs, many microprocessor-contro lled i nstruments m achines n eed t o d isplay l etters o f a lphabet n umbers. I n sy stems w here a l arge amo unt o f n eeds t o b e d isplayed a C RT i s u sed t o display. I n s ystem w here only a small amount of data needs to be displayed, simple digit-type display s are often used. re s everal tech nologies u sed t o make se digit-or iented display s b ut w e are discussing only two major ty p es. se l ight emitting diodes (L ED) and liquid- c rystal displays (L C D). L CD d isplays u se v ery l ow p ower, s o y are o ften u sed i n p ortable, battery-p owered instruments. y do not e mit ir own l ight, y simply chang e re flection o f ava ilable lig h t. refor e, a n in strument i s t o b e u sed i n low-l ight conditi o ns, y ou ha ve t o include a lig ht source for L CDs or use LEDs which emit ir own lig h t. 5.5 Interfacing Analog to Digital Data Converters I n m ost o f cas e s, th e PPI 8255 i s u sed in terfacing analog t o d igital c onverters with microproc es sor. analo g t o dig ital converters i s t readed a s an i nput d evice by microproc e ssor, tha t s ends a n i nitialising sig nal t o A DC to start analogy t o dig ital conve rsation proces s. start of conversation sig nal is a pulse of a specific dura t ion. p rocess o f analog t o d igital c onversion i s a s low p rocess, m icroprocessor has t o w ait d igital t ill c onversion i s o ver. A fter c onversion i s o ver, A DC s ends e nd o f c onversion E OC s ignal t o i nform microproce ssor conver sion is 129 Dept. of ECE

134 o ver and r esult i s ready a t o utput buffer of A D C. se t asks o f i ssuing a n SO C p ulse t o A DC, r eading E OC s ignal A DC reading d igital o utput o f A DC are carried out by CPU using 8255 I / O ports. t ime take n by A DC a ctive edg e o f S OC p ulse t ill a ctive edg e of E OC signal is called as conversion delay of A DC. I t may r ange anywhere a few microsecon ds i n c ase o f f ast ADC t o e ven a f ew hundred millise conds in case o f slow ADCs. a vailable A DC i n m arket u se different c onversion techniqu es c onversion of a nalog signa l t o d igitals. S uccessive a pproximation t echniques d ual s lope i ntegration techniques are most popular techniques used in integra ted A DC c h ip. General algorithm for ADC interfacing contains following step s: 1. Ensure stability of analog input, applied to A DC. 2. Issue start of conversion pulse to AD C 3. Read end of conversion sig nal to mark end of conversion processe s. 4. Read dig ital data output of ADC as equivalent digita l output. 5. Analog i nput v oltage m ust b e c onstant a t i nput o f A DC r ight s tart o f c onversion t ill e nd o f conve rsion to get corr ect resul t s. T his m ay be e nsured by a s ample h old c ircuit w hich s amples a nalog sig nal and h olds i t c onstant a spec ific t ime d uration. m icroprocessor may i ssue a hold s ignal t o sample hold c i rcuit. 6. I f a pplied i nput c hanges befor e comple te c onversion proc ess is o ver, digital equivalent of analog input calculated by ADC may not be corre ct. ADC 0808/0809: a nalog t o d igital c onverter c hips b it C MOS, s uccessive a pproximation c onverters. T his t echnique i s o ne o f f ast t echniques analog t o d igital conve rs ion. c onversion delay i s 100μs a t a clo ck frequency o f 640 K H z, whic h i s q uite l ow a s c ompared t o o r c onverters. se c onverters d o n ot n eed any ext ernal ze ro o r f ull scale adjustments as y are already taken care of by i nternal circuits. Fi g. 5.4 Interfacing ADC with 8255 o f micro controller se c onverters i nternally h ave a 3 : 8 a nalog m ultiplexer s o a t a t ime e ight d ifferent a nalog conversio n by using a ddress l ines - A DD A, A DD B, ADD C. U sing se a ddress i nputs, m ultichannel a cquisition syst em can b e desig ned using a single A DC. C PU may d rive se l ines u sing o utput p ort l ines i n c ase o f m ultichannel a pplications. In case of single input applications, se may b e hardwired to select proper input. re u nipolar a nalog t o d igital conv e rters, i.e. y able t o c onvert only positive a nalog i nput v oltage t o ir d igital e quivalent. se c hips d o n o c ontain any internal 130 Dept. of ECE

135 s ample h old c ircuit. I f o ne ne eds a s ample h old c ircuit for co nversion o f f ast s ignal i nto equiva lent dig ital q uantities, i t h as to b e externally connecte d a t e ach of analog i nputs. I nterfacing D igital to A nalog C onverters: d igital t o analog converte rs conver t binary n umber i nto ir equiva lent v oltages. D AC f ind a pplications i n as l ike digitally controlled gains, motors speed controls, programmable gain amplifie rs e t c. A D b it Multiplyin g D AC: T his i s a 16 p in D IP, m ultiplying d igital t o a nalog c onverter, conta ining R- 2 R l adder for D-A conve rsion along singl e p ole double thrown NMOS switches to connect digital inputs to ladde r. Fi g. 5.5 Interfacing ADC with 8255 of microc ontroller 5.6 External Memory Interfac e: Fi g. 5.6 External Memo ry interfacing 131 Dept. of ECE

136 Fig 5.7 Interfacing external m emories with mi crocontroller Fi g. 5.8 External Memory Timi ng 5.7 Stepper Motor Interface c omplete b oard consist s o f t ransformer, c ontrol c ircuit, k eypad s tepper m otor a s s hown i n s nap. circ uit h as i nbuilt 5 V p ower supply s o whe n i t i s connec ted transformer i t w ill g ive supply to circui t m otor b oth. 8 Key keypad i s conne cted c ircuit th rough w hich u ser can g ive c ommand t o c ontrol s tepper m otor. c ontrol c ircuit i ncludes m icro contr oller 89C51, indicati ng LEDs, cur rent dr iver c hip U LN2003A. One c an p rogram c ontroller t o c ontrol o peration o f s tepper m otor. H e c an g ive di fferent c ommands t hrough key pad l ike, r un c lockwise, r un a nticlockwise, i ncrease/decrease R PM, increase/decrease revolutions, stop motor, change mode, etc. Unipolar stepper motor:- u nipolar s tepper m otor h as f our c oils. O ne e nd o f e ach c oil i s tie d tog er i t g ives c ommon t erminal w hich i s alway s c onnected wit h p ositive t erminal o f suppl y. or e nds o f e ach c oil are give n interfac e. S pecific c olor c ode may a lso b e g iven. L ike i n my 132 Dept. of ECE

137 m otor orang e i s f irst coil ( L1 ), b rown i s s econd ( L2 ), y ellow i s t hird ( L3 ), b lack i s f ourth (L4) and red for common termina l. By means of controlling a stepper motor operation we can 1. Increase or decrease R PM ( speed) of i t 2. In crease or decrease number of rev olutions of it 3. Change its direction means rotate it clockwise or anticlock wise T o v ary R PM o f m otor w e h ave t o vary P RF ( Pulse R epetition Frequency). Number of applied pulses will vary number of rota tions and last to c hange direction we have to change pulse seque n ce. S o all se t hree thing s ju st d epends o n a pplied pu lses. Now re t hree different m odes to rotate t his motor 1. Single coil excitat ion 2. Double c oil exci tation 3. Half ste p excitat ion table g iven below will g ive y ou complete idea that how to give pulses in each mode Table 5.7 Pulses for stepper m otor mo dule c ircuit c onsists o f very f ew c omponents. m ajor c omponents 7805, 89C51 ULN2003A. Connec tions: - 1. transformer terminals are g iven to bridge rectifier to generate rectif ied D C. 2. It i s filtere d and g iven t o reg ulator I C 7805 to g enerate 5 V pur e DC. L ED i ndicates supply i s ON. 3. A ll p ush b utton m icro s witches J1 t o J8 connecte d with p ort P1 a s s hown t o m serial key b oard MHz crystal is connected to oscillator terminals of 89C51 with two biasing capacitor s. 5. All LE Ds are connected to port P0 as shown 6. Port P2 drives stepper motor through current driver chip ULN2003A. 7. c ommon t erminal o f mot or i s c onnected t o V cc r est a ll f our t erminals connected to port P2 pins in sequence through ULN c h ip. 133 Dept. of ECE

138 F ig.5.9 S tepper motor control board circuit Question Ban k Part-A UNIT I- THE 8086 MI CROPROCESSOR 1. What is microprocessor? A m icroprocessor i s a m ultipurpose, p rogrammable, clock-d riven, register-b ased e lectronic d evice r eads binary i nformation a s torage d evice c alled m emory, a ccepts binary a s i nput p rocesses accor ding t o t hose i nstructions, p rovides r esult a s o utput. 2. What is Accumulator? A ccumulator i s a n 8-b it r egister i s p art o f a rithmetic/logic u nit ( ALU ). T his r egister i s u sed t o store 8-b it t o perfor m a rithmetic l ogical o perations. r esult o f a n o peration is s tored i n accumulat o r. a ccumulator i s a lso i dentified a s registe r A. 3. What is stack? s tack i s a group o f m emory loc ations i n R / W m emory i s use d for storage of binary information during execution of a progr am temporary 4. Wha t is a subroutine progra m? A s ubroutine i s a group o f i nstructions w ritten separately m ain pr ogram t o p erform a f unction that occur s repeatedly i n m ain progr a m. T hus subroutines avoid repe tition of same set of instructions in main progra m. 134 Dept. of ECE

139 5. Define addressing mode. A ddressing m ode i s u sed t o s pecify way i n whi ch a ddress o f ope rand i s specifie d within instruc t ion. 6. Define instruction cycle. I t is defined as time required to complete execution of an instruction. 7. Write a program to add a data byte located at offset 0500H in 2000H segme nt to an or data byte available at 0600H in same segment and store result at 0700H in sam e segme n t. MOV AX, 2000H; initialize D S with val ue MOVD S, AX ; 2000H MOV AX, [500H]; Get first data byte from 0500H offset ADD AX, [600H]; Add this to second byt e from 0600H MOV [700H], AX; stor e A X in 0700H HL T ; Stop. 8. What are different types of addressing m odes of 8086 instruction set? different addressing mode s : i. Immediat e i i. Direct iii. Register i v. Register indirect v. In dexed v i. Register relat ive vii. Based indexed viii. Relative based indexed 9. What are different types of instructions in 8086 microprocessor? different types of instructions in 8086 microprocessor are: i. Data copy / transfer instruct ions i i. Arithmetic and logical instruct ions iii. Branch instru ctions i v. Loop instruct ion v. Machine co ntrol instruction v i. Flag manipulation instruct ion vii. Shift and rotate instruct ion viii. String instruct ion 10. What is assembly l evel programming? A p rogram c alled assemb ler i s u sed t o c onvert m nemonics o f i nstruction i nto ir e quivalent o bject c ode m odules. object c ode m odules are fur r conve rted i nto e xecutable code u sing l inker loade r pro g rams. T his t ype of prog ramming i s c alled assembly level programming. 11. What is a sta c k? Stac k i s a top-d own s tructure, w hose eleme nts a ccessed using a implemented using SS and SP registe rs. It is a LIFO data segme n t. p ointer i s 135 Dept. of ECE

140 12. How is stack top address calculate d? stack t op address i s calcula ted using c ontents o f SS SP registe r. c ontents o f s tack s egment ( SS) r egister i s s hifted l eft by f our b it p ositions ( multiplied by ( 0h)) r esulted 20-b it c ontent i s a dded 16-b it o ffset va lue o f sta ck p ointer ( SP) registe r. 13. What ar e macr o s? M acros s mall r outines u sed t o r eplace s trings i n pro g ram. y c an h ave parameters passed to m, which enhances functionality of micro itself 14.how are constants decld? Constants are declared in same way as variables, using forma t : C onst Lab el EQU 012h W hen c onstants label i s e ncountered, cons tant n umeric va lue i s exchanged string. 15. W rite an assembly language program for a 16-b it increment and will not affect contents of accumulator. MACRO inc16 variable; Increment two bytes starting a t variable Loca l IN C16 End I NC variable; Increment low 8 bits PUSH AC C MOV A variable; Are incremente d low 8 bits = 0? JNZ I NC 16 End INC variable + 1 Inc 16 End; Yes increment upper 8 bits P OP A CC E ND M AC 16. What will happen if a label within a macro is not declared loc al? If a label within a macro is not declared local, n at assembly time, re will be two types of error s : I. first will state that re are multiple labels in sour ce. II. second will indicate that jump instructions don t know which one to use. 17 e lse 18. Write an assembly language prog ram to load accumulator with a constant value. MACRO inver t val ue i f (value== 0 ) M OV A, # 1 clr A e nd i f E ND M AC.. What is difference between microprocessor and microcontrolle r? 136 Dept. of ECE

141 M icroprocessor d oes no t c ontain R AM, ROM I / O por ts o n c hip. B ut a microcontroller contains RAM, ROM and I/ O ports and a timer all on a single c h ip. 19. What is assemble r? asse mbler transla tes assembly language p rogram t ext w hich i s g iven a s i nput to a ssembler to ir binary equivalents k nown a s obje ct c ode. time r equired to translate assembly code to objec t code is called access time. assembler checks for syn tax errors & displays m before giving objec t code. 20. W hat is loade r? l oader c opies p rogram i nto c omputer s progr am execution at e xecution time. m ain emo m ry a t load time and begins 21. W hat is linker? A l inker i s a p rogram use d t o jo in tog er severa l o bject f iles i nto o ne la rge objec t file. F or l arge pr ograms it i s m ore effic ient t o divid e la rge progra m modul es i nto s maller m odules. E ach mod ule i s individually w ritten, tes ted & debu g ged. When all mo dules work y linked toger to form a large functioning program. 22.Explain ALIG N & A SSUME. A LIGN d irective ces assemble r t o alig n th e n ext s egment a t a n a ddress divisibl e by specified div isor. mat i s A LIGN n umber w here n umber c an b e 2, 4, 8 or 16. Examp le ALI G N 8. A SSUME d irective assig ns a l ogical s egment t o a physi cal s egment a t a ny g iven time. I t t ells a ssembler w hat a ddress w ill b e i n s egment regis ters a t execution time. Exam ple ASSUME CS: cod e, DS: data, SS: stack 23. E xplain PTR & GROUP A p rogram may conta in s everal s egments o f s ame t y pe. G ROUP d irective c ollects m u nder a single n ame s o y ca n res ide i n a single segmen t, usually a data segmen t. format is Name GROUP Seg-nam e,.. Seg-name P TR i s u sed t o assig n a s pecific type t o a vari able or a lab e l. I t i s a lso u sed t o override declared ty pe of a v a riable. 24. E xplain about MODEL T his direct ive p rovides s hort c uts i n d efining s egments. I t i nitializes m emory m odel b efore d efining any s egment. memory m odel c an b e S MALL, M EDIUM, COMPA CT o r L A RGE. Model C ode segments Data segments Smal l One On e Med ium Multipl e On e Compact One Multipl e Large Multipl e Multipl e 25 E xplain PROC & ENDP P ROC d irective d efines p rocedures i n p rogram. p rocedure n ame m ust b e unique. A fter PROC term NEAR o r F AR u sed to specify type o f p rocedure. E xample F ACT P ROC F AR. E NDP i s u sed along P ROC d efines th e e nd o f procedure. 26. Explain SEGME NT & ENDS An assembly p rogram in.exe format consists of one or more segme nts. Th e starts o f se s egments d efined by S EGMENT an d e nd o f seg ment is indicate d by ENDS directive. Format Name SEGM ENT Name ENDS 137 Dept. of ECE

142 27. Explain TI T LE & T YPE TITL E directi ve help s t o c ontrol mat o f a l isting o f a n assembl ed prog ra m. I t c auses a t itle for th e progra m t o prin t o n lin e 2 o f e ach pag e o f prog ram listing. Maximum 60 charac ters are allowed. Format TI T LE text. T YPE o perator t ells a ssembler t o d etermine ty pe o f specif ied varia ble i n b y tes. F or by tes assemb ler giv e s a value 1, for word 2 & double word D efine SOP s egment o verride p refix a llows prog rammer t o devia te defa ult segmen t E g : MOV CS: [ BX ], AL 29 D efine variable. A v ariable i s a n i dentifier i s associate d fir st byte of i tem. In assemb ly language statement: COUNT DB 20H, COUNT is v a riable. 30. What are procedur es? Procedur es a g roup o f i nstructions s tored a s a s eparate p rogram i n memory and i tis c alled from m ain p rogram whenever required. type of p rocedure de pends o n where p rocedures s tored i n memor y. I f i t i s i n s ame c ode s egment a s o f main progr am n it is a near pro cedure o rwise i t is a far proced u re. 31. E xplain linking pr o cess. A l inker i s a p rogram use d t o jo in tog er severa l o bject file s i nto o ne larg e o b ject file. linker produces a link file which contains binary codes a ll c ombined module s. I t a lso p roduces a l ink m ap whic h conta ins a ddress i nformation a bout link files. l inker d oes not assig n Absolute addresses but only relative address starting from zero, so programs are relocatable & ca n be put anyw here in memo ry t o be run. 32, D efine variable A v ariable i s a n i dentifier i s associate d fir st byte of i tem. In assemb ly language statement: COUNT DB 20H, COUNT is v a riable. 33. What are procedur es? P rocedures a g roup o f i nstructions s tored a s a s eparate p rogram i n memory and i t is c alled from main p rogram whenever required. ty pe o f p rocedure d epends o n where p rocedures s tored i n memor y. I f i t i s i n s ame c ode s egment a s o f main progr am n it is a near pro cedure o rwise i t is a far proced u re. 34. E xplain linking pr o cess. A l inker i s a p rogram use d t o jo in tog er se veral o bject file s i nto o ne larg e ob ject file. l inker p roduces a l ink f ile whic h contain s binary code s a ll combi ned module s. I t a lso p roduces a l ink m ap w hich c ontains a ddress i nformation a bout l ink fil e s. l inker d oes n ot assign a bsolute a ddresses b ut only r elative a ddress starting from zero, so programs are reloca t able & c an be put anyw here in memo ry t o be run C ompare Proce dure & Ma cro. Proced ur A ccessed by CAL L & e RET inst ruction Macro A ccessed during assemb ly with name d uring progr am e xecution tgi o vm ean cro when defined M achine code for instructio n is put onl y M achine c ode is generated for inst ruction o nce each tim e when m acro is called iw n ith procedur memo rye s less memo ry is req uired With m acro more memo ry is requ ired Parameters ca n be passed in register s, Parameters pas sed as par t of stateme nt memo ry l ocations or stack which c alls ma cro 138 Dept. of E CE

143 36. What is maximum memory size that can be addressed by 8086? I n 8086, a n memory locat ion i s a ddressed by 20 bi t a ddress and address bu s is 20 bit addr ess address bus is 20 bits. So it can address up to one mega by t e (2^20) o f memory s pace. PART-B 1. ( a) W rite a n assembly l anguage progr am i n 8086 t o search largest data i n th e array ( 10) ( b) E xplain var ious stat us flags i n 8086 ( 6 ) 2. ( a) D iscuss various a ddressing m odes o f 8086 ( 10) ( b) E xplain followi ng a ssembler d irective i n 8086 ( 6) i. AS SUME i i. E QU iii. DW 3. ( a) W rite s hort n otes o n Macro ( 6) ( b) E xplain funct ion o f assembler directive s ( 10) 4. E xplain architecture o f 8086 ( 16) 5. ( a) E xplain regi ster o rganization o f 8086 ( 10) ( b) E xplain p in diagram o f 8086 ( 6 ) 6. D iscuss inst ruction s et o f 8086 i n detail ( 16) U NI T II SYSTEM BUS STRUCTURE 1. Differentiate between minimum and max imum m ode 2. Give any f our pin definitions for minimum m ode. 139 Dept. of ECE

144 3. What are pins that are used to indicate type of transfer in minimum mode? M/IO, RD, WR lines specify ty pe of transfer. It is indicated in following table: 4. What are functional parts of 8086 CPU? two independent functional parts of 8086 CPU are: i. B us Interface Unit (BIU): BIU sends out addresses, fetches instruction from memory, reads data from por ts an d memory and writes data to ports and memory. i i. Exe cution U n it ( E U) : EU tells BIU where to fetch instructions or data, decodes instruc tions and executes instruc t ions. 5. W hat is operation of S0, S1 and S2 pins in maximum mode? S2, S1, S0 indicates type of transfer to take place during current bus cy c le. 6. Give any four pin definitions for maximum mo d e. 140 Dept. of ECE

145 7. Draw bus request and bus grant timings in minimum mode sy s tem. 8. What is purpose of a decode r in EU? decoder in EU translates instructions fetched from memory into a series of a ct ions, which EU carrie s out. 9. Give register classification of conta i ns: i. General purpose registers: y are used for holding, variables and intermediate results temporarily. i i. Special purpose registers: y are used as segment registers, pointers, index regi ster or as offset storage registers for particular addressing mode s. 10. What are general datgiste rs? registers AX,BX,CX and DX are general datgiste rs. L L and H represents lower and higher bytes of particular registe r. AX register is used as 16-bit accumula t or. BX register is used as offset storage for forming phys ical addresses in case of certain addressing mode s. CX register is used as a default counter in case of string and loop instruc t ions. D X register is used as an implicit operand or destination in case of a f ew instruc t ions. 11. Give different segme nt registe rs. four segment reg isters : i. Code seg ment register: It is used for addressing a memory location in code segm ent of memory, where executable program is store d. i i. Data segment reg ister: It points to data segment of memory, where data is resided. iii. Extra segment reg ister: I t also contains data. i v. Stack segment register: It is used for addressing stock segment of memory. It is used to stor e stack data. 12. What are pointers and inde x registe r s? I P, B P and S P pointe rs c ontain offse ts in c ode, data and sta ck segme nts respectively. SI DI ar e index r egisters, wh ich used a s genera l p urpose r egisters 141 Dept. of ECE

146 a lso for offset storage i n addressing mode s. c ase o f n i dex e d, ba sed indexe d relati ve base d indexe d 13.How is phy s ical address calculated? Give an example. physical address, which is 20-bits long is calculated using segm ent and offset registers, each 16-bits long. segment address is shifted left bit-w ise four times and offset address is added to this to produce a 20 bit physic al addre s s. 14. What is meant by memory s egmentation? Memory segmentation is process of completely dividing physically a vailable memory into a number of logical segm ents. E ach segment is 64K byte in size and is addressed by one of segment register. 15. What are advantages of segmented memory? advantages of segmented memory : i. Allows memory capacity to be 1Mbyte, although actual addresses to be handled are of 16-bit size. i i. Allows placing of code, data and stack portions of same program in different part s of memory data and code protection. iii. Permits a program and/or its data to be put into different areas of memory, each times program is executed i.e., provision for relocation may be done. 16. What is pipelining? Fetching next instruction while current instruction executes is called pipel ining 17. What are two parts of a flag registe r? two parts of 16 bit flag register are: i. Condition code or status flag registe r: It consists of six flags to indicate some condition produced by an instruc t ion. i i. Machine control flag register: It consists of three flags and are used to control certain operations of proces sor 18.Draw format of 8086 flag registe r flag registe r: 142 Dept. of ECE

147 19. Explain three ma chine contr ol flag s. i. Tra p flag: If this flag is set, processor enters single step exec u tion. i i. I nterrupt flag: If this flag is set, markable interrupts are recognized by CPU, orwise y are ig n ored. iii. Direction flag: This is used by string manipulation instruc tions. If this flag bit is 0, string is processed from lowest to hig hest address i. e., auto incrementing mode. Orwise, string is processed from highest address to lowe st addre ss, i. e., au to decrementing mode. 20. What are three groups of sig n als in 8086? 8086 signals are categorized in three gr o ups. y : i. signals having common functions in mini mum maximum mod e. i i. signals having specia l func tions for minimum mode. iii. signals having special functions for maximum mode. 21. What are uses of AD 15 AD0 line s? A D15 AD0 are time multiplexed memory I/ O address and data lines. Addr ess r emains on lines during T1 state, while data is available on data bus during T2, T3, Tw T4 states. se lines are active high and float to a tristate during interrupt acknowledge an d local bus hold acknowledg e cycle s. 22. What is operation of RD signa l? RD is an active low signal. When it is low, it indicates peripherals that processor i s performing a memory or I / O read operation. 23.Give function of i. Ready and ii. INTR signa l. i. Ready signal: It is an acknowledgement from slow devices of memory that y h ave completed data transfer. signal is synchronized by 8284 A clock generator to give ready i nput t o signa l is active hig h. i i. INTR sig nal: It is a level trigge red input. This is sampled during last cycle of each instruction to determine availability of reque st. If any interrupt request is pending, processor enters interrupt acknowledge cycle. This can be internally masked by resetting inte rrupt enable flag. signal is active h igh and i nternally synchronized. 143 Dept. of ECE

148 24. What is operation performed when TE S T input is low? W hen TEST input is low, execution will continue, else, processor remai ns in an idle state. 25. W hat is NMI ( Non- M askable Interrupt)? NMI is an edge-triggered input, which causes a ty pe 2 interrupt. It is not maskable internal ly by software and transition from low to hig h initiate interrupt response at end of current instruct ion. This input is internally sy n chronized. 22. What is purpose of cloc k input? clock input provides basic timing for processor operation and bus contr ol activity. It is an asymmetric square wave with 33% duty cyc le. range of frequency varies fro m 5 MHz to 10MHz. 23. What is function of M N/MX pin? log ic leve l a t MN /MX p in decide s whe r pr ocessor operates i n m aximum m ode. m inimum o r 24. What happens when a high is applied to RESE T pin? When a hig h is given to RESET pin, processor terminates current activity and start s executing from FFFF0H. It must be active for at least four clock cy cles. It is internally sy n chronized. 25. W hat will happen when a DMA request is made, while CPU is performing a memory or I/ O cy c les? When a DMA request is made, while CPU is performing a memory or I/ O cyc les, it will request local bus during T4 provide d : i. request occurs on or before T2 state of current cycle. i i. current cycle is not operating over lower by t e of a word. iii. current cycle is not first acknowledge of an interrupt acknowledge seque n ce. i v. A lock instruction is not being execute d. 26. What is multiprogramming? I f m ore t han o ne proc ess i s c arried o ut a t s ame t ime, n i t i s k now a s multiprogramming. A nor d efinition i s interleaving o f C PU I / O o perations a mong s everal p rograms i s c alled m ultiprogramming. T o i mprove utilization o f CPU I / O d evices, w e designing t o p rocess a se t o f independe nt p rograms concurrently b y a single C PU. This technique is known as multiprogram ming 27. Write advantage s of loosely coupled sys tem over tightly coupled system s? 1. More number of CPUs can be added in a loosely coupled sys tem to improve sys tem performance 2. sys tem structure is m odular and hence easy t o maintain and troubleshoot. 3. A fault in a single module does not lead to a complete sy s tem breakdown. 28. W hat is different clock frequencies use d in 80286? V arious v ersions o f ava ilable tha t r un o n 12.5MHz, 10MHz an d 8M Hz cloc k frequencie s. 29. Define swap ping i n? p ortion o f a prog ram i s r equired exe cution by CP U, i t i s fetch ed from secondary memory p laced i n phy sical memor y. T his i s c alled s wapping i n o f progra m. 144 Dept. of ECE

149 30. What are diffe rent operating m o des used in 80286? works in two operating modes 1. R eal addressing m ode 2. Protected virtual address mode. 31. What are C PU contents used in 80286? CPU c ontains almost same set of registe rs, as in 8086 Eight 16- bit general purpose regi ster Four 16-bit segment regi sters Status and control regi ster I n struction pointer. PART-B 1. ( a) D raw explain th e m aximum m ode o f 8086 ( 12) ( b) List ad vantages o f multiprocessor sys tem ( 4) 2. ( a) E xplain f unctions o f ( 8 ) i. HLD A i i. RQ/ GT0 iii. D EN iv. ALE ( b) D raw e xplain m inimum mo de o f 8086 ( 8 ) 3. ( a) D raw and explain block diagr am o f minimum m ode of operatio n ( 12) ( b) W rite n otes on addressing m emory ( 4 ) 4. D efine bus cyc le and min imum m ode r ead wr ite b us cyc les with proper t iming diagr am ( 16) 5. ( a) D raw input output tim ing diagr am o f maximum m ode of operatio n i n 8086 ( 10) ( b) E xplain th e addressing capabilities of 8086 ( 6 ) 145 Dept. of ECE

150 E C6504 MICROPROCESSOR & MIC UNIT-III I/O INTERFACING 1. What is memory mapped I / O? T his i s o ne o f t echniques interfacing I/O d evices μ p. I n m emory m apped I /O, I / O d evices a ssigned i dentified b y 16-b it addr e sses. T o t ransfer da ta betwe en M PU I / O devices memory related instructions ( such as LDA, STA etc.) and memory control sig n als ( MEMR, MEMW) are used. 2. What is I/ O mapped I / O? This is one of techniques for interfacing I/O devices with μp. In I / O mapped I/O, I/ O devices assign ed i dentified by 8-b it a ddresses. To t ransfer between M PU an d I / O devices I / O related ins tructions ( I N and OUT ) and I/ O control sig nals ( I OR, I O W) are used. 3. What is simple x and duplex transmission? Simplex t ransmission: t ransmitted i n only one directi o n. Duplex t ransmission: f low i n both dir ect ions. If transm ission g oes one way a t a t ime, i t is called half duplex; if i t g oes both way s imultaneously, n it i s called full duplex 4. Define Ba u d. rate at which bits are transmitted, bits pe r se cond is calle d B au d. 5. What are signals available for seria l communic at ion? SI D serial input dat a SOD serial output dat a 6. What is USART? I t i s a prog rammable d evice. I ts f unction s pecification s erial I / O c an b e d etermined by writing instructions in its internal registers. Intel 8251A USART is a device widely u sed in serial I/O. 7. Write features of 8255A. 8255A h as 24 I / O p ins c an b e primarily g rouped primarily i n t wo 8-b it P arallel p orts: A B, eig ht bits as port C. 8-bits of port C can be used as two 4-bit ports:c UPPER CU and CLOWER CL. 8. What is BSR mode? A ll fu nctions o f 8255 classified according t o 2 m odes. I n c ontrol w ord, i f D7 = 0, n i t represe nts bit set reset mode operat ion. BSR mode is used to set or reset bits in p ort C. 9. What is mode 0 operation of 8255? I n this mode, ports A and B are used as two simple 8-bit I/O ports and port C as two 4-b it ports. E ach p ort can be programmed to function a s an input por t or an output port. input/ output features in mode 0 a s follow s : i. outputs ar e latched i i. inputs ar e not latched iii. p orts do not have handshake or interrupt capability. 10. What are modes of operation supported by 8255? i. Bit set reset mode(b S R) i i. I/ O mode Mode 0 Mode1 Mode2 146 D ept.of ECE

151 E C6504 MICROPROCESSOR & MIC 11. W rite control word format for BSR mode. 12. Wha t is ADC and DAC? electronic circuit that translates an analog signal into a digital signal is called analog-to-digi tal co nverter(adc). electronic circuit translates a digital signal into an analog signal is called Digital-to-a nalog co nverter(dac). 13. Define conversion time. I t i s define d as t otal t ime required t o conve rt a n ana log sig nal i nto a digital o utput. I t is determi ned conversion technique used and by propagation delay i n various circuits What are functions to be performed by μp while interfacing an ADC? i. Send a pulse to START p in. i i. Wait unti l end of convers ion iii. Read digital sig nal a t an input port. Write different types of AD C. i. Single slope ADC i i. Dual slope ADC iii. Successive approximation ADC i v. Parallel comparator type AD C v. Counter typ e ADC 16. What is resolution time in A D C? It is defined as a ratio of change in value of input voltage Vi, needed to change digital output by 1 LSB. If full scale input voltage required to cause a digital output of al l 1 s is ViFS. n re solution can be give n as R esolution = ViFS / ( 2n- 1 ) 17. List functions performed by i. It has built-in hardware to provide key d ebounce. i i. It provides a scanned interface to a 64 contact key ma t rix. iii. It provides multiplexed display interface with blanking a n d inhibit options. i v. It provides three input modes for keyboard interface. 18. What is key d ebounce? p ush b utton k eys whe n p ressed, b ounces a f ew t imes, c losing open ing c ontacts b efore p roviding a steady r eading. S o r eading t aken dur ing b ouncing may b e fault y. refore microproc essor m ust w ait until key reach to steady s tate. This is known as key debounce. 147 D ept.of ECE

152 E C6504 MICROPROCESSOR & MIC 19. What are operating mode s in 8279? i. Scanned keyb oard mode i i. Scanned sensor mat rix iii. Strobed input 20. What is N-key r ollover? I n N-key r ollover e ach k ey d epression i s t reated independently a ll ot h ers. W hen a key i s d epressed, debounce logic is set and 8279 checks for key depress during n ext two scans. 21. Find program clock command word if external clock frequency i s 2 MHz. P rescalar value = (2 x106) / (100 x 103) = ( 10100) 2 refore comma nd w o rd = ( ) What is multiple interrupt processing capability? W henever a n umber o f d evices i nterrupt a C PU a t a t ime, i d properly, it is said to have multiple interrupt processing c apability p rocessor i s a ble t o handl e m 23. What is hardware inte rr upt? A n 8086 i nterrupt c an com e any o ne o f three s ources. One sou rces i s a n ext ernal s ignal applie d t o n onmarkable interrupt( NM I ) i nput i n or t o i nterrupt ( I NTR ) input p in. A n i nterrupt c aused by th e sig nal applied to one of se input is referred to as a hardware inter ru pt. 24. What is software inter ru pt? interrupt caused due to execution of interrupt instruction is called softw interr u pt. 25. What are two ty p es of interrupts in 8086? two ty pes of interrupts : i. External inte rru pts: I n this, interrupt is generated outside processor. Example: Key b oard interrupt. i i. Internal inte rru pts: It is generated internally by processor circuit or by execution of an interrupt instruction. Example: Z e ro interrupt, overflow interrupt. PAR T B 1. D raw block diagr am o f 8279 e xplain f unction o f eac h. ( 16) 2. With th e h elp o f neat diagr am e xplain h ow 8251 is interf aced wi th 8085 used serial commu nication ( 16) 3. D iscuss silent f eature o f 8259 and explain block d iagram of progr ammable in terrupts controllers ( 16) 4. ( a) Describe various modes of operation in 8253 programmable internal timer ( 8) ( b) E xplain operation o f DMA c ontroller 8237 ( 8 ) 5. (a) D raw and explain interfacing of cascaded 8259 wi th 8086 ( 10) ( b) E xplain in deta il wi th modes of operat ion o f 8255 ( 6) 6. D raw pin diagr am o f 8257 progr ammable D MA c ontroller e xplain function of each pin in d etail ( 16) 7. D iscuss various operatin g m odes o f 8253 tim er wi th n ecessary control wo rds ( 16) UNIT-I V MICROCONTROLLE R 148 D ept.of ECE

153 E C6504 MICROPROCESSOR & MIC 1. What are special functoin registe r? special function register are stack pointer, index pointer (DPL and DPH), I / O port addresses, status(psw) and accumulator. 2. What are uses of accumulator registe r? accumulator registers (A and B at addresses OEOh and OFOh, respectively) are used to store temporar y values and results of arithmetic opera t ions. 3. What is PS W? Program status word (PSW) is set of flags that contains status informa tion is considere d as one o f special function register. 4. What is stack pointe r ( s p)? Stack pointer (SP) is a 8 bit wide register and is incremented before data is stored into stack using PUSH or CALL i nstructions. It contains 8-b it stack top address. It is defined anywhere in on-chip 128-by t e RAM. A fter reset, SP register is initialized to 07. After each write to stack operation, 8-bit contents of operand are stored onto sta ck, after incrementing SP register by o ne. It is not a top-down data structur e. I t is allotted an address in special function registe r ba n k. 5. What is data pointe r ( DTPR)? It is a 16-bit register that contains a higher byte (DPH) and lower byte (DPL) of a 16-b it external data RAM addr es s. It is accessed as a 16-bit register or two 8-bit registe rs. It has been allotted two addresses in special function register bank, for its two bytes DPH and DPL. 6. Why oscillator circuit is used? Oscillator circuit is used to generate basic timing clock signal for operation of circuit using crystal oscillator. 7. What is purpose of using instruc tion registe r? Instruction register is used for purpose of decoding opcode of an instruction to be executed and gives i nformation to timing and control unit generating necessary signals for execution of instruc t ion. 8. Give purpose of ale/prog signa l. ALE/PROG is an address latch enable output pulse and indicates that valid address bits available o n respective p ins. ALE pulses are emitted at a rate of one-s ixth of oscillator frequency. signal is valid only external memory acce s ses. It may be used for external timing o r clockwise purpose. One ALE pulse is skipped during e ach access to external data memory. 9. Explain two power saving mode of opera t ion. two power saving modes of opera tion : I. Idle mode: 149 D ept.of ECE

154 E C6504 MICROPROCESSOR & MIC In this mode, oscillator continues to run and interrupt, serial port and timer blocks are active, but clock to CPU is disab led. CPU status is preserved. This mode can be terminated with a hardware interrupt or hardware reset signal. A fter this, C PU resumes program execution from where it left off. II. Power down mode: In this mode, on-chip oscillator is stopped. All functions of controller are held maintaining contents of RAM. only way to terminate this mode is hardware rese t. reset redefines all th e SFRs but RAM contents are left unchange d. 10. Differentiate between program memory and data memory. i. In stores programs to be execute d. i i. It stores only progr am code which is to be executed and thus it need not be written, so it is implemented using EPROM It stores data, line intermediate results, variables and constants required for exec ution of progr am. data memory may be read from or written to and thus it is implemented using R AM. 11. What are addressing modes? various ways of accessing data are called addressing m odes. 12. Give addressing modes of 8051? re are six addressing modes in 8051.y ar e D irect addre ssing Indirect a ddressing Register i nstruction Registe rspecific (regis t er implicit) Immediate m ode Indexed addr essing 13. W hat is direct addressing mode? operands are specified using 8- bit address field, in instruction format. Only i nternal data Ram and SFRS can be directly addressed. This is known as direct addressing mode. Eg: Mov R0, 89H 14. What is indirec t addressing mode? In this mode, 8-b it address of an operand is stored in gister and register, instead of 8-b it address, is specified in instruct ion. registers R0 and R1 of selected bank of registers or stack pointer can be used as address registers for storing 8-bit addresse s. address register for 16- bit addresses can only be da ta pointer (DP TR). Eg : ADD R What is meant by register instructions addressing mode? operations are stored in reg i sters R0 R7 of selected registe r b ank. One of se eig ht register s ( R0 R7) is specified in instruction using 3-bit reg ister specification field of opcode format. A register bank can be selected using two bank select bits of PSN. This is calle d as register instruct ion addressing m ode Eg : A D D A, R What is immediate addressing mode? An immediate data ie., a constant is specified in instruction, after opcode byte. 150 D ept.of ECE

155 E C6504 MICROPROCESSOR & MIC Eg: MO V A, #100 immediate data 100 (decimal) is added to contents of accumulator. For specifying a hex number, it should be followed by H. se are known as immediate addressing mode. 17. What is indexed addressing? This addressing mode is used only to access program memory. It is accomplished in 8051 for look-u p table manipulat ions. Program counter or data pointer are allowed 16-bit address storage regi sters, in this mode of addressing. se 16-bit registers point to base of look-up table and ACC regi ster contains a code to be converted using look-up table. look- up table data address is fo und out by adding contents of register ACC with that of program counter or data pointe r. In case of jump instruction, contents of accumulator are added with one of specified 16- bit register s to form jump destina tion addr es s. Eg: MOV C, A + DPTP A + DPTR 18. List five addressing modes of 8051 microcontrolle r. five addressing mode s, I. Im mediate addressing II. Regi ster addressing III. Direct addres sing IV. Reg ister indirect addres sing a. I ndexed addressing. 19. MOV R4, R7 is invali d. Why? movement of data between accumulator and Rn (for n = 0 to 7) is val id. But movement of dat a between Rn registe r is not al lowed. That is why M OV R4, R7 is invalid. 20. WHAT I S SFR? I n 8051 microcontroller registers A, B, PSW and DPTR are part of gr oup of registers commonly referred to as special func tion registe rs (SFR). 21. WHAT ARE THE TWO MAI N F E ATURES OF SFR ADDRESSES? following two points should be noted SF R addres ses. special function reg isters have addresses betwee n 80H and FFH. se addresses are above 80H, since addresses 00 to 7FH are addresses of RAM memory inside II. Not all address space of 80 to FH is used by SFR. unused locations 80Hto F FH are reserved and must not used by 8051 prog r ammer. 22. What is difference between direct and reg ister indirect addressing mode? Loop is most efficient and is possible only in register indirect addressing whereas looping i s not direct addressing mode. 23 Li st out some compa re instructions. compare instruc tions are: a. CJN E b. CLR c. CPL 151 D ept.of ECE

156 E C6504 MICROPROCESSOR & MIC 24 Write a program to save accumulator in r7 of b ank 2. C L R PSW 3 S ETB PSW 4 MO V R 7, A. 25. What are single bit instructions? Give example. Instructions that are used for single bit operation are called sing l e bit instructions. Examples: SET B b it CLR bit CPL b it 26. Write a program to save status of bits p1.2 and p1.3 on ram bit LOCATIO NS 6 AN D 7 RESPECTIVEL Y. MOV C, P1. 2; save status of P 1.2 on CY MOV O6, C; save carry i n RAM bit location 06 MOV C, p1.3; save stat us of p1.3 on CY MOV 07, C; save carry i n RAM bit location Write a program to see if bits 0 and 5 of register b r 1. If y not, make m so and s ave it in r0. JNB OF O H, NEXT 1 ; JUMP i f B.0 is low SET BOFOH; Make bit B. 0 high NEX T 1 :JNB OF5H, NEXT 2; JUMP if B. 5 is l ow SETB OF 5H; Make B. 5 high NEX T 2: MOV R0, B; Save register B. PART-B 1. W ith n ecessary diagr am o f control wo rd mat, e xplain va rious operating m odes of tim er i n 8051 microcontroller 2,(a) With help of neat diagram explain memory o rganization of 8051 microcontroller 3. With neat sketch explain architecture of 8051 microcontr o ller. Bloc k Diagram E xplanation about all blocks in block diagram 4. Draw Pin Diagram of 8051 and explain function of various sig n als. 5. L ist various Instructions available in 8051 microcontrolle r. Data Transfer In structions Arithmetic Instruct ions Log ical In structions Boolean variable Manipulation In structions Prog ram and Machine Control In structions UNIT-V INTERFACING MICROCONTRO LLERS 1. What is a serial data buf fer? Serial data buffer is a special function register and it initiates serial transmission when byte is written to it and if read, it reads received serial data. It contains two independent registers internally. One of m is a transmit buffer, which is a parallel-in serial-out register. or is ceive buffer, which is a serial-in parallel-out register 152 D ept.of ECE

157 E C6504 MICROPROCESSOR & MIC 2. What are timer reg i sters? Timer registers are two 16-bit registers and can be accessed as ir lower and uppe r byt es. TLO represents lower byte of timing register 0, while THO represents higher bytes of timing regi ster 0. Similarly, TLI and THI represent lower and higher byt es of timing register 1. se registers can be accessed using four addresses allotted to m, which lie in special function registers address range, i.e., 801 H to F F. 3. What is use of timing c o ntrol unit? Timing and control unit is used to derive all necessary timing and control signals required for internal operation of circuit. It also derives control signals that are required for controlling external system b us. 4. When are timer overflow bits se t rese t? timer overflow bits are set when timer rolls over and reset eir by execution of an RET instruction or by software, manually clearing bits. bits are located in TCON register along with timer ru n contr o l ( T Rn) bits. 5. Explain mode (0 and1) operation of time r. operations ar e a s f o llows: Timer mode 0 and 1 operations are similar for 13 bit (mode) or 16 bit (mode 1) counter. When ti mer reaches limits of count, overflow flag is set and counter is reset back to ze ro. modes 0 and 1 can be used to time exte rnal eve n ts. y can be used as specific time delays by loading m with an initial value before allowing m to execute and overflow. 6. What is different modes in which timer 2 can operate? two different modes in which Timer 2 opera tes. i. Capture m ode Timer 2 operates as free running clocks, which saves timers value on each high to low tran sition. It can be used for recording bit lengths when receiving Manchester- e ncoded data. i i. Auto-reload mode: When timer overflows, value is written into TH2/TL2 registers from RCA P2H/RCA P21 registers. T his feature is used to implement a system watch dog time r. 7. What ia use of a watch dog time r? A watching timer is used to protect an application in case controlling microcontroller beg ins to run am ok and execute randomly rar than preprog r ammed instructions written for application. 8. Define inte r rupt. I nterrupt is defined as request that can be refuse d. If not refused and when an interrupt reques t is acknowledged, a special set of routine or events are followed to handle inte r rupt. 7. What are steps followed to service an interrupt? ste ps followed ar e: I. Save context reg i ster information. II. Reset hardware requesting interr u pt. III. Reset interrupt controlle r. IV. Process inter ru pt. V. Restore context informa t ion. VI. Return to previously executing c ode. 153 D ept.of ECE

158 E C6504 MICROPROCESSOR & MIC 8. How can 8051 be interrupte d? re are five different ways to interru pt Two of se are from external electrical signal s. or three are caused by internal 8051 I / O h ardware operations. 9.Give format of interrupt enable registe r. format of interrupt enable register i s, EA - - ES ET1 EX1 ET0 EX0 register is used to enable or disable all 8051 interrupts and to selectively enable or disable each of five different interr u pts. EA: Disables all interr upts Es: Enables or disable serial port interr u pt. ET1: Enable or disable timer 1 overflow inter r upt. EX1: Enable or disable external inte rru pt 1. ET0: Enable or disable time r 0 overfl ow interr upt. EX0: Enable or disable external inte rru pt What is meant by nesting of inter r upts? Nesting of interrupts means that interrupts are re-enabled inside an interrupt handle r. If anor interrupt r equest codes in, while first interrupt handler is executing, processor execution w ill acknowledge new interr upt and jump to its vector. 11. How is 8051 serial port different from or mic ro controlle rs? 8051 serial port is a very complex peripheral and able to send data synchronously asynchronously i n a variety o f different transmission modes. 12. Explain sy n chronous data transmission. In sy n chronous mode (mode 0), instruction clock is used. Data transfer is initiated by writing to serial data port addre s s. Txd pin is used for clock output, while R xd pin is for data transfe r. When a character is received, status of data transfer is monitored by polling RI-n bit in serial control reg i ster ( SCO N ). 13. Give an application for synchronous serial communic t ion. A n application for synchronous serial communication is RS When is an external memory access generated in 8051? In 8051, during execution data is fetche d co ntinuous. Most of data is executed out of 8051 s built-in control stor e. When an address is outside internal control store, an external memory acce ss is generate d. 15.Give priority level of interrupt source s. Interrupt source Priority within a level I E0 (External I N T0 ) TF0( Time r 0 ) I E 1 (External I N T 1) TF 1 ( Time r 1) RI = TI ( Serial port) Highest 154 D ept.of ECE

159 E C6504 MICROPROCESSOR & MIC.. Lowes t 16. Wha t is use of stepper m otor? A s tepper m otor i s a devi ce u sed t o obta in a n accurate po sition contr ol of r otating s hafts. A s tepper m otor employ s r otation o f i ts s haft i n t erms o f r otation as in case of A C or DC motor. s teps, rar than c ontinuous 17. W hat is meant by k ey bouncing? Microprocessor m ust w ait u ntil k ey re ach t o a steady s tate; t his i s k nown as Key bounce PART-B 1. With neat sketch explain functions of 8255 PPI. Bloc k Diagram Explanation about all por ts availa b le. Explanation about modes of transfer Explain control Word Register 2. With neat sketch explain functions of Bloc k Diagram Types of data transfe r Explanation about all bloc k s. Explain control Word Register, Status Register 3. With neat sketch explain function of DMA controlle r. Bloc k Diagram Explanation about all blocks in block diagram W ith neat sketch explain function of Prog rammable Interrupt Controller. Bloc k Diagram Explanation about all blocks in block diagram 4. With neat sketch explain function of Keyboard and display c ontroller. Bloc k Diagram Types of Display A vailable Types of keys available Explanation about all blocks in block diagram 5. With neat sketch explain func tion of A/D converte r. Fundamental step s Figure E xplain functions. 6. With neat sketch explain func tion of D/A converte r. Fundamental step s Figure Explain func t ions. 155 D ept.of ECE

160 E C6504 MICROPROCESSOR & MIC UNIVERSITY QUESTIO NS 156 D ept.of ECE

161 E C6504 MICROPROCESSOR & MIC 157 D ept.of ECE