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1 Question Bank UNIT 1 1. Define Computer Architecture. Illustr a te seven dimensions of an ISA?(10 marks (M a/ June 2010 (June 2012 (Dec 2012 ( June 2011 ( June What is dependabilit? Explain two measures of Dependabil i t? ( 06 mark s (Ma /June 2010 ( December 2012 ( Decembe r Give foll owing m e asurements ( 06 m arks (M a/ June 2010 ( Dec2 012 Frequenc of FP operati o ns=25% CPI of or instructi o ns=1.33 CPI of FP operati o ns=4.0 Frequenc of F PSQR=2% CPI of F P SQR=20 Assum e at e tw o design alternati ve to d ecrease e C PI of FPSQR to 2 or t o d ecrease a verage C PI o f a ll F P operation s to 2. 5 com pare e two design alternatives using processor performance equati o ns. 4. Explain in brief measuri ng, reporting and summarizing perfor m ance of computer.(8 marks (Decembe r 2012 (June Explain wi learning curve how cost of processor varies wi time al o ng wi factor s influencing cost. ( 6 marks 6.. Find number of dies per 200 cm wafer of circular shape at is used to cut die at is 1. 5 cm side and compare number of dies produced on same wafer if die is 1.25 cm. (6 marks. Define Amdahl ' s la w. Derive n expression for CPU clo ck as a fu nction of instruction count, clocks per instruction and clock ccle time. (8 marks ( June/Jul (Dec List and explain four important technologies, which has lead to impr o vements in computer sstem. ( Dec D efine d ependabilit a nd i ts m easures. A ssume a di sk subsste m wi e follo w ing c omponents and MTTF: 10 disks, each rated at 1,000,000- h our MTTF ( June13 1

2 1 SCSI controller, 500,000- h o ur MTTF 1 power suppl, 200,000- hour M T TF 1 fan, 200,000- h our MTTF 1 SCSI cable, 500,000- h our MTTF Assuming failures are independent, compute MTTF of sstem as a whole. S uppose w e made foll owing m e asurements: Frequenc of FP operatio ns = 25% A verage CPI of F P operations = 4. 0 CPI of or instructi o ns = 1.33 Frequenc of F PSQR = 2% CPI of F P SQR = 20 Assum e at e tw o design alternati ves to d ecrease e C PI of F PSQR to 2 or to d ecrease a verage C PI of al l F P operation s t o C ompare se t wo desig n alternatives using processor performance equati o n. 10.We will run two application needs 80% of resources and or onl 20% of r esources. i >Given at 40% of first application is parallelizable, how much speed up would ou a chieve wi at application if run in isolation? ii>given at 99%pf second application is parallelized, how much speed up would is a pplication observe if run in isolation? i ii> Given at 40% of first application is parallelizable, how much overall speed up w ould ou observe if ou parallelized it? UNIT 2 1. Wi a neat diagram explain classic five stage pipeline for a RISC processor. ( 10 m arks (June 2010 (Decembe r 2010 (June What are major hur d les of pipelining? Illustrate branch hazar d in detai l?( 10 marks (June 2010 (Dec 2012 (June 2012 (Jul (De c W i a n eat diagram ex plain classic five s tage p ipeline for a RI SC processor. ( 10 m arks ( D ec 2012 (June 2011 (June Explain how pipeline is implemented in MIPS. (6 m arks (June Explain different techniques in reducing pipeline branch penalt ies. ( 6 mar k s (June 2012 (June 2010 ( June What are major hurdles of pipelining? Explain briefl. ( 8 marks (June 2012 (June 2011 (Decembe r List and expl ain five was of classifing exception in a computer sstem. ( 05 Mar ks(jul

3 8. List pipeline hazard s. Expl ain an one in detail. ( 10 m arks ( D ec 2010 ( June2013 UNIT 3 1. W hat t echniques u sed t o r educe bran ch c osts? Expl ain b o s tatic and dnamic branch pr ediction used for s ame? ( 10 marks (June 2010 ( Dec 2012 ( June wi a neat diagram give basic structur e of tomasulo based MIPS FP unit a n d explain various field of res ervation stations.(10 marks ( June 2010 (Dec 2012 ( Dec What are data dependencies? Explain name dependencies wi exampl e s between two instru ctions. (6 marks (June What are correlating predictors? Explain wi example s (6 marks 5. For following instructions, using dnamic scheduling show status of R,O.B, reservation station when onl MUL.D is r ead to commit and two L. D committed. ( 8 marks 6. What is dra wback of 1- bit dnamic branch prediction meod? Clearl state how it is overcome in 2- bit pre diction. Give state transition diagram of 2- b it predictor. ( 10 mark s (Dec 2010 ( June2013 UNI T 4 1. E xplain b asic V LIW a pproach for expl oiting I LP u sing multiple issues? ( 10 mar ks (Jun 2010(June/ Jul (Dec 2010 (Dec 2012 (June w hat k e i ssues i n implementi ng advanced speculation t echniques? E xplain m in detail? ( 10 marks (Jun 2010 (June What ar e ke issues in implementing advanced specul a tion techniques? Explain in detail? ( 08 Marks 4.Write a note on value predictors. ( 04 Marks 5. Explain branch-target buffer. ( 8 marks ( Dec Write a shor t note on value predictor. ( 4 mark s (Dec w hat k e issues i n implem enting a dvanced s peculation techn iques? Explain m in detail? ( 10 m arks (Dec 2012 (June2013 3

4 UNIT 5 1. Explain basic schemes for enforcing coherence in a shared memor multiprocessor s stem? ( 10 marks (Jun 2010 ( June Expalin director based coherence for a distributed memor multiprocessor sstem? ( 10 marks (Jun Expl ain director bas ed cac he coheren ce for a dis tributed memor multiprocessor sstem along wi state transition diagra m. ( 10 Mark s ( June/Jul (Dec 2010 (Dec Explain an two hardware primitive to implement snchronization wi example. ( 10 Mar k s 5. List and explain an ree hardware primitives to implement snchroniz a tion. ( 8 mark s (Dec 2010 (June Explain director based coherence for a distributed memor multiprocessor sstem? ( 10 mark s ( Dec Assume w e h ave a compute r wh ere cloc k p er instructio n (CPI i s 1.0 when al l memor a ccesses h it e c ache. e on l data a ccesses loa ds an d stor es a nd ese tota l 50 % of instructions. i f e m ass penalit i s 25 cloc k ccles an d e m ass rate i s 2%. how much fast e r would computer be if all instructions were cache hit s? ( 10 marks( J une 2010 ( June Explain in brief, tpes of basic cache optimiz ation? ( 10 mark s ( June 2010 (June Ex plain block replacement str ategies to replace a block, wi exampl e w hen a cach e. ( 06 Mar k s 4. Explain tpes of basic cache optimiza tion. ( 09 Marks 5. Wi a diagram, explain organization of data cache in opter o n microprocessor. ( 06 Marks 6. Assume we have a computer where CPI is 1.0 when all memor accesses hits in cache. The onl data accesses ar e loads and store s, and se 50% o f instru ction. If miss penalt is of 25 ccl es and miss ra te is 2%, how m uch faster computer be, if all instr u ction were cache hits? (8 m arks (Dec 2010 ( June Briefl explain four basic cache optimiz a tion meods. ( 12 mark s (Dec 2010 (June2013 4

5 7 1. Which are major categories of advanced optimization of cache perform ance? explain an one in details ( 10 marks (Jun 2010 ( Dec Explain in detail architecture support for protecting processes from each o r via virtual memor ( 10 marks ( Jun 2010 (Dec Explain following advanced optimiza tion of c ache: 1. Compiler optimiz ations to re duce miss ra te. 2. Merging write buffer to re duce miss penalt. 3. Non blocking cache to increase cache band-wid. ( 09 Marks 2011 (Dec 2010 ( June Explain internal organization of 64 Mb DRA M (Dec 2010 (Dec 2012 (June 2013 ( 05 Marks 8 1. Explain in detail hardware support for preserving exception behavior dur i ng specula tion ( 10 marks (Dec 2012 (Jul 11 ( J u ne Explain prediction and Speculation support pr o vided in IA64? ( 10 marks ( Dec 2012 (June Expl ain i n d etail h ardware suppor t for preser ving e xception b ehavior during specula tion. ( 10 Mar ks (Dec 2012 ( Jul 2012 (Dec 2010 (June Explain architecture of IA64 Intel processor and also prediction and speculation support pro vided. ( 10 Mar k s ( Dec 2012 ( Dec 2010(Dec 2012 ( June Consider loop bel o w: F or ( i = 1; i 100 ; i = i+ 1 { A[ i ] = A[i] + B[i] ; 1 * S1 * 1 B[ i+1]= C[i] + D [ i] ; 1 * S2 * 1 } W hat d ependencies betwee n S 1 and S 2? I s e l oop parallel? If not show how to make it parallel. ( 8 mar k s (Dec 2010 D ept of C SE, S JBIT, B angalore 5 5

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