Bus transit = 20 ns (one way) access, each module cannot be accessed faster than 120 ns. So, the maximum bandwidth is

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1 32 Flynn: Coputer Architecture { The Solutions Chapter 6. Meory Syste Design Proble 6. The eory odule uses 64 4 M b chips for 32MB of data and 8 4 M b chips for ECC. This allows 64 bits + 8 bits ECC to be accessed in parallel, foring a physical word. T access =odule = 20 ns T c = 20 ns T nibble = 40 ns up to four accesses Physical word = 64 bits + 8 bits ECC Bus transit = 20 ns (one way) ECC = 40 ns a. Meory syste access tie b. Maxiu eory data bandwidth = Bus transit + T access =odule + T ECC + Bus transit = = 200 ns Since we are allowed to have ultiple buses and ECC units, we think of 4 eory odules as one very wide eory with 256 bits (64 bits 4) wide datapath. That is, 256 bits can be fetched in parallel. The only liiting factor here is T c for each odule. For rando access, each odule cannot be accessed faster than 20 ns. So, the axiu bandwidth is 256 bits 20ns = Bps = 254M Bps. c. Fro above, 256 bits can be fetched in parallel. We can use nibble ode for 4 consecutive accesses. Thus we can fetch = 024 bits every 20 + (4 ) 40 = 240 ns. So the axiu bandwidth is = Bps = 509MBps. 024 bits 240ns The low-order bits of the address are divided up as follows: bits 0{2: bits 3{4: bits 5{6: byte oset odule address nibble address Proble 6.2 a. For a page ode, the best organization will place a single page on a single odule; this takes advantage of locality of reference as consecutive references to a single (2K) page will be able to take advantage of page ode. This is better than nibble ode, where only references to the sae four words can take advantage of the optiized T nibble tie. Thus, the lower bits of the word address are used as a (DRAM) page oset, and the address is broken up as follows: bits 0{2: byte oset bits 3{3: page oset bits 4{5: odule address The advantage to interleaving is that accesses to dierent pages can be overlapped.

2 Proble b. This syste will perfor signicantly better than nibble ode for:. Non-sequential access patterns. 2. Access patterns that exhibit locality within a DRAM page. 3. Access patterns that exhibit locality within ultiple pages. 4. Access patterns that sequentially traverse pages. Proble 6.3 Haing Code Design Data size () = 8 bits 2 k + k + Solve for k, and get k = 5 Total essage length = = 23 bits Each correction bit covers its group bits () k :, 3, 5, 7, 9,, 3, 5, 7, 9, 2, 23 k 2 : 2{3, 6{7, 0{, 4{5, 8{9, 22{23 k 3 : 4{7, 2{5, 20{23 k 4 : 8{5 k 5 : 6{23. Code for SEC (single error correction): f f f f f f f f f f f f f f f f f f f f f f f k k k k k The logic equation for each k is just XOR of each k's group bits. 2. Code for DEC (double error correction): To detect double bit errors, we ust add a nal parity bit for the entire SEC code. f f f f f f f f f f f f f f f f f f f f f f f f k k k k k k Proble MIPS 0.9 Instruction refs/inst 0.3 Data read/inst and 0. Data write/inst T a = 200 ns T c = 00 ns

3 34 Flynn: Coputer Architecture { The Solutions Use open queue odel a. The allocation of odules to instruction and data i) Meory odules for instruction MAPS for instruction = 0:9 40 = 36 MAPS = s = T c = = = 3:6= Use = 8, = :45 So, 8 odules are necessary. ii) Meory odules for data MAPS for data = :4 40 = 6 MAPS = = :6 Use = 4, = :4 So, 4 odules are necessary. 2 odules are necessary in total. b. Eective T w per reference (overall) Assue this is M B =D= p = T w = p 2( ) = T c 2( ) For instruction eory, T w = :45 :25 = 29:55 ns 2( :45) For data eory, T w = 00 0 Overall T w = :929:55ns+:42:5ns :4+:9 = 24:3 ns c. Queue size 9 :4 :25 = 2:5 ns 2( :4) For instruction eory, Q ot = T w for Inst = : = :06 For data eory, Q ot = T w for data = :5 0 9 = :2 Overall Q ot = :06 + :2 = :26 d. Coparison to a single integrated I and D eory syste MAPS = :3 40 MIPS = 52 MAPS = s T c = = 5:2 Use = 6, =.325 T w = T c = 00 ns : ( ) 2( :325) = 9:4 ns Q ot = T w = 9:4 ns per sec = :009 Type Nuber of odules T w Q ot Split ns.26 Integrated ns

4 Proble Proble 6.5 Use M B =D= closed queue odel for realistic results T c = 00 ns; T a = 20 ns Two references to eory in each eory cycle: n = 2 Eight interleaved eory odules: = 8 a. Expected waiting tie a = q ( ) = :233 T w = T a c 2( a) = 00 ns :233 8 b. Total access tie 2( :233) = 7:04 ns T a + T w = 20 ns + 7:04 ns = 27:04ns c. Mean total nuber of queued (waiting) requests n B = n a = 2 8 :233 = :36 d. Oered eory bandwidth Oered = n=t c = 2=00 ns = 20 MAPS e. Achieved eory bandwidth B(; n)=t c = 8 :233=00ns = 8:64 MAPS f. Achieved bandwidth using Strecker's odel B(; n) = ( ( ) n ) = 8( ( 8 )2 ) = :875 Bandwidth = B T c = : = 8:75 MAPS Proble 6.7 Integrated Meory with = 8 C P = 2 (Instruction source and data source; assues no independent writes fro a data buer. If data buer is assued, then C p = 3.) Z = C P T Tc = 3 00( ns) = 2 =(400 6 ) = Z n = :3 00( ns) = :433 2 =(400 6 ) Perf ach = 3:74 5:2 B(; n; ) = + n 2 :433 = 8 + 5:2 2 = 3:74 40 MIPS = 28:8 MIPS. q q ( + n 2 )2 2n :433 (8 + 5:2 2 )2 2 5:2 8

5 36 Flynn: Coputer Architecture { The Solutions Proble 6.8 T a = 200 ns, T c = 00 ns, = 8, T bus = 25 ns, L = 6; Copyback with write allocate. a. Copute T line:access. L > and T c < T bus b. Repeat for = 2 and = 4. = 2; < L and T c > T bus = 4; < L and T c T bus T line:access = T a + (L ) T bus = = 575 ns T line:access = T a + T c (d L e) + T bus ((L )od ) = (7) + 25() = 925 ns T line:access = T a + (L )T bus = (25) = 575 ns c. Nibble ode is now introduced: T nibble = 50 ns; = 2; v = 4; T v = 50 ns T line:access = T a + T c (d v L e ) + T bus(l = () + 25(6 2) = 650 ns L v ) Proble 6.9 CBWA with w = :5, T a = 200 ns, T c = 00 ns, = 8, T bus = 25 ns, L = 6 a. Unbuered line transfer starting at line address T :iss = ( + w) T line:access = :5 575 ns = 863 ns T c:iss = ( + w) T line:access = :5 575 ns = 863 ns T busy = 0 ns b. Write buer, line transfer starting at line address T :iss = ( + w) T line:access = :5 575 ns = 863 ns T c:iss = T line:access = 575 ns T busy = w T line:access = 288 ns c. Access rst word T :iss = ( + w) T line:access = :5 575 ns = 863 ns T c:iss = T a = 200 ns T busy = T :iss T c:iss = 663 ns

6 Proble Proble 6.3 A processor without a cache accesses every t-th eleent of a k eleent vector. Each eleent is physical word. Assuing T a = 200 ns, T c = 00 ns, and T bus = 25 ns, plot the average access tie per eleent for an 8-way, low-order interleaved eory for t = to 2 and k = 00. Figure 2: Proble 6-3. Proble 6.4 s = 75 MAPS and T s = 00 ns = s T s = = 7:5 Since should be around.5, use = 6. Then, = 7:5 6 =.469. Q o = ( p) = :469(:469 6 ) 2( ) 2( :469) = :795 Q ot = 6 :795 = 2:87 a. Using Chebyshev Prob (q > BF).0 Prob (q BF +).0 Q o BF +.0 BF + Qo P = :795 = 7:95 8 :0 BF 7 Total BF (TBF) = 7 6 = 272

7 38 Flynn: Coputer Architecture { The Solutions b. Using M/M/ Prob (overow).0 Solve for (TBF=)+2 = :0 :469 (TBF=)+2 = :0 TBF 66 Proble 6.5 You are to design the eory for a 50 MIPS processor ( ~ /I) with instruction and 0.5 data references per instruction. The eory syste is to be 6MB. The physical word size is 4B. You are to use M x b chips with T c = 40 ns. Draw a block diagra of your eory including address, data, and control connections between the processor, DRAM controller, and the eory. Detail what each address bit does. If T a = 00 ns, what are the expected eory occupancy, waiting tie, total access tie, and total queue size? Discuss the applicability of the Flores odel in the analysis of this design? A3,A2 CS CPU Addr 24 DRAM Ctrl RAS/CAS Addr 0 CS CS CS Meory Chips (32) Data 32 Figure 3: Proble 6-5. = 75MAP S = =T c = = = 3= = 4 = 0:75 = T w = T c 2( ) = T c = 40 ns ( =) Q o = = 0:75 2( ) Q o t = 3 Because of the high occupancy of the eory, the Flores odel is not particularly well suited to this design.

8 Proble Proble 6.7 IF/cycle =.5 DF/cycle =.3 DS/cycle =.3 = 8 and T s = 00 ns(eory) Processor cycle tie (T ) = 20 ns! 50 MIPS = : = 45 MAPS n = (:5 + :3 + :) = 4:5 z = = 5 = n z = 4:5 5 =.3 = n = 4:5 8 =.563 B(; n; ) = 8 + 4:5 :3 2 r (8 + 4:5 = 3:377 Bw = 3: = 33:77MAP S :3 2 ) :5 a = B = 3:377 = :422 8 MIPS ach = a : MIPS = = 37:48 MIPS :563 T w = n B B T 4:5 3:377 s = 00( ns) = 33:25(ns) 3:377 Q ct = n B = 4:5 3:377 = :23 Proble 6.8 a. Line size = 6B This is already calculated in study 6.3. Perf rel = :78 b. Line size = 8B Miss rate =.07 L = 8B=4B = 2 L T line access = T a + T c ( ) + T bus ((L ) od ) = ( ) + 40((2 ) od 2) = = 60 ns T :iss = ( + w)t line access = :5 60 ns = 240 ns Perf rel = + f p T :iss = + : = :704

9 40 Flynn: Coputer Architecture { The Solutions c. Line size = 32B Miss rate =.02 L = 32B 4B = 8 8 T line access = ( 2 = 460 ) + 40((8 ) od 2) T :iss = ( + w) 460 ns = :5 460 ns = 690 ns Perf rel = + :02 =( ) = :743 9 In conclusion, the cache with 6B line size shows the best perforance.