Arithmetic Unit for Complex Number Processing

Transcription

1 Abstract Arithetic Unit or Coplex Nuber Processing Dr. Soloon Khelnik, Dr. Sergey Selyutin, Alexandr Viduetsky, Inna Doubson, Seion Khelnik This paper presents developent o a coplex nuber arithetic unit (CAU), based on the single-coponent representation o coplex nubers by positional binary codes with coplex radix. Algoriths o the basic arithetic operations in this representation are described and analyzed. The results o CAU design, siulation and synthesis and coparison o CAU characteristics to those o traditional arithetic units (TAU) are presented. It is shown that ipleentation o CAU algoriths in ath processors achieves signiicant (5-10 ties) speed-up o coplex nuber processing over TAU equivalents. 1. Introduction Matheatical operations with coplex nubers are coonly required in nuerous coputer applications, such as digital signal processing, wireless counication and telecounication systes, control o power systes, etc. Algoriths or coputer gaes and 3D graphics applications can be expressed using coplex nubers. These operations usually include arithetic operations, odulus coparisons, square and cube roots, logarithic, trigonoetric and hyperbolic unctions, as well as ast Fourier transors, to nae a ew. Following historical atheatical notation, coplex nubers in digital coputers are represented as pairs o real nubers. Matheatic operations on coplex nubers in TAU are ipleented using operations on real nubers. Consider operation o addition (subtraction) o two coplex nubers: ( a + jb) ± ( c + jd ) = ( a ± c) + j( b ± d ) where j is an iaginary unit. This operation involves 2 real additions (subtractions). Multiplication o two coplex nubers: ( a + jb) ( c + jd ) = ( ac bd ) + j( ad + bc) will involve 6 real operations (our ultiplications, one addition and one subtraction). Division o two coplex nubers: ( a + jb) /( c + jd ) = ( ac + bd )/( c + d ) + j( bc ad )/( c + d ) will involve 11 real operations (2 divisions, 6 ultiplications, 2 additions and one subtraction). Siilarly, it can be shown that operation o coplex square root can be reduced to 6 real operations. 1

2 Due to representation o coplex nubers with separate real and iaginary coponents, processing o coplex nubers in TAU requires ore systes resources and has uch slower perorance than real nuber processing. To iprove perorance o coplex nuber processing in coputer systes several proposals have been ade or a single-coponent representation. The essence o these proposals is to present coplex nubers in such a positional nuber syste, which allows or coplex operations to be ipleented on a single data eleent without a need or separate processing o real and iaginary coponents. S. Khelnik [2,5,9] was aong the irst to analyze and propose various positional codes or presentation and processing o coplex nubers. He proposed and analyzed several positional coding systes, including those with j 2 radix and (-1+j) radix. Other early researchers in this ield include D. Knuth [1] who suggested to use an iaginary radix j 2 or positional coplex codes and W. Penney [4] who also suggested to use a coplex radix (-1+j). In his works [2,5,6,7,9,14,15] S. Khelnik suggested techniques or coding and decoding coplex nubers and apparatus or arithetic and atheatic processing o coplex nubers, and then in [3,8,14-17] ipleentation o these operations in digital hardware. Last works by S. Khelnik [14-17] are being ipleented in specialized ALUs or coplex nuber processing. Later several authors [11-13] suggested techniques or design o coplex nuber ultipliers. They used redundant codes or coplex nuber representation, in order to achieve ore regularity in ASIC hardware. However these coding systes were never applied to ipleentation o other arithetic operations, such as division. Six dierent coplex radixes suggested in [2,5,9] by S. Khelnik are discussed below in ore detail. 2. Positional codes o coplex nubers In positional code systes the value o a real and coplex nuber is expressed as weighted su o radix powers ultiplied by real or coplex digits. The radix itsel ay be a positive, negative or coplex (iaginary) nuber. The positional code o a coplex nuber ay be constructed by coposition o positional codes o its real and iaginary coponents, presented in negative radix [9]. Consider a coplex nuber Z = X α + jy β. Let X α and Y β be its real and iaginary coponents presented in a radix ρ = -2 nuber syste as: X α = αρ and Y = βρ () β. () The ollowing binary codes correspond to these presentations: K ( X α ) = {α } and K ( Y β ) = { β }. 2

3 Consider two ethods o coposing these codes into a single code o coplex nuber. In the irst ethod a pair o digits (α, β ) is designated by a nueral λ, which akes radix (-2) code with digits λ {0, 1, j, 1+j}: K (Z) = { λ } As shown in [4], this code ay be also viewed as a positional code o or: with binary digits: and variable radix: ( ρ, ) γ / ρ = ( jρ Z = γ, α, = β, 2, 1) / ( ρ ) i is even i is odd i is even 2, i is odd In the second ethod digits { } α and { } β are interleaved: { β + 1α + 1βα β 1α 1}. Let designate nowα = σ 2, β = σ 2 1 and rewrite this sequence in another or: where k = 2. This sequence ors a ollowing code: { σ σ σ σ σ σ 3}, k+ 2 k+ 1 k k 1 k 2 k K (Z) = { σ } It is shown in [9] that this code corresponds to radix ρ = j 2 code o a coplex nuber Z = X α + j 2 Y β with binary digits σ { 0,1 } : Z = σ () ρ Two types o positional codes described above support basic arithetic operations on coplex nubers: addition, subtraction, ultiplication and division. In [2,5,9,14,15] soe other positional coplex codes were analyzed. Several radices or building positional binary codes o coplex nubers are presented in Table 1. 3

4 Table 1. Radices used to build positional codes o coplex nubers. Radix Code o 2 1 / 2 ρ, i is even ρ = ( 1) / 2, ρ = 2 j ρ, i is odd (, ) 2.1 ( ) ρ = ρ 2.2 ( ) 3.1 ( ),, ρ = j 2 ρ, = ρ, ρ = j 2 ρ = ρ 3.2 ( ) 4,, ρ = ( 1+ j) ρ = ρ,, ρ = ( 1 j) ( ρ ) = ρ 1,, ρ = ( 1 + j 7) / 2 ρ, i is even By ar, usage o radix ( ρ, ) = ( 1) / 2, ρ = 2 gives uch j ρ, i is odd sipler and ore eective hardware ipleentation o coplex arithetical unit. The described coding syste with coplex radix have a nuber advantages copared to conventional coding systes with real radix: uniied coplex 2n-bit code with (-2) radix and interleaved iaginary and real bits vs pair o two n-bit codes in radix 2 or real and iaginary part the sign operations are not required due to (-2) radix there is no need or 2 s copleent transorations rules o overlow and underlow detection are sipliied algoriths o operations with variable length codes are sipler digit-by-digit technique can be used or coputation o all eleentary unctions o coplex arguents 4

5 3. Basic operational blocks o coplex arithetic unit 3.1. Addition and Subtraction Taking into account the described ethods o positional coding, algebraic addition o coplex nubers in these systes is perored according to the rules o algebraic addition in positional codes o real nubers with (-2) radix. Fig. 1 illustrates the pattern o suation and carry propagation in the process o algebraic addition o singlecoponent coplex codes. Although coplex nubers are represented by single-coponent codes, due to described [9,15] properties o coding systes even and odd digits are processed separately and in parallel, which aounts to the sae speed o operation and double length o operands copared to traditional adders or real nubers. It was shown [9] that carry propagation signals can be represented by two bits in all binary coplex nuber systes with coplex radices Multiplication and Division Multiplication o two coplex nubers: V = vk ( ρ, k) and W = wh ( ρ, h) k h results in a product deterined as: Z = [ Vw ( ρ, ) ] ρ, h is equivalent to the h-digit shit o the code Multiplication by the basic unction ( ) with radix ρ. Since w = { 0,1} h, the ultiplication o codes in this nuber syste is reduced to the series o additions and shits. Fig. 2 shows a traditional sequential ultiplication circuit, which is also applicable to the ultiplication o coplex nubers. 5

6 The ajor dierences ro traditional ultiplication o real nubers are absence o sign operations and execution o operation on the codes as a whole, without separate processing o real and iaginary coponents. Multiplication perorance and speed is deterined by the nuber o analyzed digits at each add-and-shit cycle. For the two types o coding systes, having =2 requires an adder circuitry to support addition (subtraction) o X, -X and -2X ultiples [15]. Division using proposed code systes is soewhat siilar to traditional division o real nubers, with the ollowing exception. The goal o division is to converge reainder to zero. In traditional algoriths the sign o reainder is analyzed and is used to deterine value o next subtraction (addition). In our case analysis o coplex odulus is perored to achieve the sae goal. Once again, division operation is executed as a whole, without need or separate processing o real and iaginary coponents Eleentary Functions o Coplex Arguent Although it goes beyond the scope o this discussion. It is worth entioning that digitby-digit technique or coputation o eleentary unctions o real arguents [10] ay be extended on coplex arguents as well. Algoriths or coputation o coplex eleentary unctions were developed in [9,15] and include trigonoetric and hyperbolic unctions, logarith and antilogarith, raising to a coplex power, odulus calculation, inding square root, transoration between polar and Cartesian coordinates, vector rotation. 6

7 3.4. Coplex Arithetic Unit Architecture In order to support described operations CAU will include such ajor blocks as adder, ultiplier etc, auxiliary blocks to support execution o iscellaneous unary and binary operations and icroprogra block to ipleent coputation o eleentary unctions. The overall architecture o CAU is shown at Fig Coparison with traditional arithetic unit It was deonstrated earlier that coplex operations in TAU are ipleented using operations on real nubers. We will show that ipleentation o coplex operations in CAU requires ore or less the sae aount o tie consued by their real equivalents in TAU. Traditional AU will use our n-bit real codes to represent two coplex nubers with n- bit precision and CAU will use two 2n-bit coplex codes to represent two coplex nubers with n-bit precision. Due to ebedded parallelis in processing o even and odd bits, CAU will peror a coplex addition o these codes at the speed o one n-bit real addition, whereas TAU will require two n-bit real additions to support the sae operation o coplex addition. 7

8 In the case o addition o loating-point nubers, a better precision vs. traditional approach is achieved due to coon exponent or real and iaginary parts. It can be shown that or 64-bit codes this is equivalent to 14% savings in bit length vs. traditional approach, where separate exponents are used in representation o loating-point reals and iaginaries. Siilarly, it can be shown that coplex ultiplication o two 2n-bit coplex codes in CAU can be perored at the speed o one ultiplication o n-bit real codes. At the sae tie TAU will require our ultiplications o n-bit real codes and two additions o n-bit real codes. In general, a coplex arithetic operation on 2n-bit codes in CAU takes the sae tie as corresponding real arithetic operation on n-bit codes in TAU. To speed up perorance o ath operations even urther traditional hardware acceleration techniques such as carry-save/ripple-carry adders and atrix ultipliers can be ipleented in CAU, resulting in increased syste requency. The ollowing table shows how any real operations are required or sotware ipleentation o soe coplex algebraic operations in TAU. Operation Algebraic addition o integer coplex nubers Multiplication o integer coplex nubers Aine integer transoration Basic operation or integer FFT Algebraic addition o loating coplex nubers Multiplication o loating coplex nubers Aine loating transoration Basic operation or loating FFT Table 2. Coparison o TAU versus CAU perorance. NoIn NoALU clocks NoCPU clocks ttau tcau TAU/ CAU ttau tcau TAU/ CAU ttau tcau TAU/ CAU Division o integer

9 coplex nubers Coparison o coplex nuber odules Functions o a coplex arguent ~20 1 ~20 ~900 ~80 11 ~110 0 ~90 12 NOTE. Based on CAU architecture it is possible to develop ath processors or atrix coputations and geoetric transorations. It is estiated that such processors will speed up perorance o FFT by at least 7 ties and o aine transors by at least 20 ties. Table 2 given below shows coparison o CAU and TAU perorance. It is based on the results o TAU and CAU siulation. In this table the ollowing notations are used: NoIn - nuber o instructions to ipleent operation. It is assued that ultiplications and aine transorations, as well as basic FFT operations are perored using array ultipliers NoALU - nuber o ALU clocks to execute operation NoCPU - nuber o CPU clocks to execute all instructions or given operation, including eory access, which is equivalent to 3 ALU clocks ttau - paraeters o traditional ALU or real nubers (TAU) tcau - paraeters o ALU or coplex nubers (CAU) TAU/CAU - ratio o TAU speed over CAU speed This coparison is based on nuber o operations instead o operation execution ties, because those depend largely on syste requency and processor technology, rather than on processor architecture. Assuing that algebraic operations are distributed uniorly across ath applications, one will conclude that each coplex operation in TAU requires in average 5 real operations. Considering also ipleentation o geoetrical and ast Fourier transorations as coplex operations, will result in 5-10 ties speedup o coplex nuber processing in CAU copared to TAU. This technology signiicantly reduces the nuber o required coputer operations at a sall cost o increased circuit coplexity. Such reduction o operations leads to a aster coputation tie and should cause power savings. 5. Conclusion At the current stage o developent the ollowing results were achieved: 1. sound theoretical oundation o coplex coputer arithetic and etheatics, based on proposed uniied code or coplex nuber presentation 2. design and developent o CAU hardware, ipleenting a vast class o ath operations and unctions on coplex nubers 3. developent o VHDL siulation odels o CAU blocks 9

10 4. synthesis o CAU operational and control blocks, targeted or dierent ASIC and FPGA technologies 5. siulation and testing o CAU unctional behavior and perorance in the syste environent, using behavioral and RTL odels In addition, the ollowing tools and odels were developed or CAU siulation, debugging and testing: 6. VHDL odel o virtual processor and eory, presented at Fig prograing language or this processor several application progras browsers or viewing the architecture and layout o design blocks, algoriths o CAU and unctional tests Based on results o design, siulation and synthesis the ollowing technical paraeters o CAU were established: nuber o operational blocks ~ 190 nuber o individual operations ~ 250 nuber o logic gates ~ 250,000 inial syste clock period ~ 30 gate delays The uture stages o CAU developent will include urther enhanceents in ath processor architecture and tools to support eective ipleentation o coputer applications with intensive coplex nuber processing. 10

11 Building ath processors, based on described technology, will ake possible to achieve the ollowing results in applications with coplex nubers: perorance o coplex nubers processing increased by ~ 5-10 ties data eory requireent reduced by ~ 15% labor-intensiveness o prograing reduced by ~ 2 ties 6. Reerences 1. D.E. Knuth. An Iaginary Nuber Syste, Counications o ACM 3, No. 4, S. Khelnik. A Specialized Coputer or Operations on Coplex Nubers. Questions o Radio Electronics XII, No. 2, 1962 (in Russian). 3. S. Khelnik. Adder o codes o coplex nubers. Questions o Radio Electronics XII, No. 3, Penney W., A Binary Syste or Coplex Nubers, Journal o ACM 12, No. 2, 1965, pp S. Khelnik. Positional Coding Systes or Coplex Nuber Presentation. Questions o Radio Electronics XII, No. 9, 1966 (in Russian). 6. S. Khelnik. Nuber syste with coplex bases, Part in Book: Pospelov D.A., Arithetic basis o digital Coputers, "Visshaja shkola", 1970, Moscow. 7. S. Khelnik. Solution o the navigation probles on a digital coputer using coplex nubers codes, "Proble special radio-electronic", series "Teleechanics and anageent Systes", 1971, No 6, Moscow. 8. S. Khelnik et al. Digital devices with icrochips, "Energia", 1975, Moscow. 9. S. Khelnik. Coputer Arithetic o Vectors, Figures and Functions, Matheatics in Coputers, 1995, Tel Aviv (in Russian). 10. Miller J. M., Eleentary Functions. Algoriths and Ipleentation. Birkhauser, 1997, Boston. 11. T. Aoki, H. Aada, and T. Higuchi: "Real/Coplex Reconigurable Arithetic Using Redundant Coplex Nuber Systes". In Proc. 13 th Syposiu on Coputer Arithetic, Y. Chang and K. Parhi. High Perorance Digit Serial Coplex Nuber Multiplier-Accuulator, Proc. Int. Con. on Coputer Design, A. M. Nielsen and P. Kornerup, Redundant Radix Representation o Rings, IEEE Transactions on Coputers, Vol. 48 (11), Noveber S. Khelnik, A Method and Syste or Processing Coplex Nubers. International Patent Application, WO 01/50332, United States Patent Application No. 10/189,195, S. Khelnik, A Method and Syste or Ipleenting Coprocessor. Canadian Patent Application, CA , S. Khelnik. Method and Syste or Processing Matrices o Coplex Nubers and FFT, Canadian Patent Application, CA , S. Khelnik, Method and Syste or Processing Matrices o Coplex Nubers and Coplex Fast Fourier Transoration. International Patent Application, PCT/CA02/00295,