A High-Speed Processor for Digital Sine/Cosine Generation and Angle Rotation*

Transcription

1 Copyright IEEE 998: Published the proceedgs of the nd Asiloar Conference on Signals, Systes and Coputers, Nov -4, 998, at Asiloar, California, USA A High-Speed Processor for Digital Se/Cose Generation and Angle Rotation* Dengwei Fu and Alan N Willson, Jr Electrical Engeerg Departent University of California, Los Angeles Abstract We present an architecture for high perforance se/ cose generation and angle rotation Unlike CORDIC-type ethods, which ipleent rotation usg a sequence of subrotation stages, each realized with a butterfly structure, the proposed approach ipleents the rotation with just two stages We perfor approxiately the sae nuber of arithetic operations our architecture as CORDICtype processors, but our architecture consolidates the operations to sall array-ultipliers, which can yield a saller and faster circuit usg well-known efficient ultiplier ipleentation techniques (such as Booth encodg Introduction The coputation of se and cose functions and perforg angle rotations are quite coon requireents digital signal processg and counication applications There are various hardware designs that accoplish these tasks, notably the CORDIC processors [], [] and, recently, an angle-rotation processor [] These algoriths accoplish the rotation through a sequence of subrotations, with the put to each subrotation stage dependg on the output of the previous stage In soe systes, such as frequency-hopped applications, a ial latency tie is desirable In view of this requireent, we now propose a different approach Here the rotation is partitioned to just two cascaded rotation stages: a coarse rotation and a fe rotation The two specific aounts of rotation are obtaed directly fro the origal angle without perforg iterations The critical path is therefore ade significantly shorter than that of the CORDIC-type ethods Background and otivation If we rotate a pot the plane havg coordates ( 0, 0 counterclockwise, around the orig, by the angle *This work was supported by the National Science Foundation under Grant MIP and by California MICRO Grant 98-7 φ, a new pot havg coordates (, is obtaed It is related to the origal pot ( 0, 0 as: = 0 cosφ 0 sφ ( = 0 cosφ + 0 sφ This operation is found any counication applications, notably digital ixers which translate a baseband signal to soe terediate frequency and vice versa In addition to accoplishg ( with CORDIC, a very coon ipleentation is to store pre-coputed se/cose values a ROM [4] Then, real-tie, the coputation ( is accoplished with a ROM access for each given φ followed by four real ultiplications This ethod avoids the excessive latency of the iterations perfored by CORDIC and can yield lower latency than the angle-rotation ethod [] Furtherore, a very fast circuit can be built, based on efficient ultiplier design techniques However, sce the size of the ROM grows exponentially with the precision of φ, a rather large ROM is required to achieve accurate results ROM copression can be achieved by exploitg the quarter-wave syetry of the se/cose functions and such trigonoetric identities as sθ = cos( π θ The angle φ the full range [ 0π, ] can be apped to an angle θ [ 0, This is accoplished by conditionally terchangg the put values 0 and 0, and conditionally terchangg and negatg the output and values [5] Thus, we will focus only on θ [ 0, and replace φ by θ ( Obviously, the se/cose ROM saples ust be quantized This produces an error the ROM output, which will subsequently be referred to as the ROM quantization error Next we exae how this error affects the output Let and sθ be quantized to N bits, to becoe [ ] and [ sθ], respectively We have cos θ = [ ] + ( s θ = [ sθ] + sθ where and sθ are the ROM quantization errors, which satisfy < N and sθ < N The error due to the ROM quantization is the difference between calculated usg fite-precision se/cose values and the quantized values, that is = ( 0 0 sθ ( 0 [ ] 0 [ sθ] = 0 0 s θ (

2 Its upper bound is < ( N ( 4 If the rotation angle happens to be so sall that θ < N ( 5 then its se/cose values can be approxiated as sθ θ ( 6 ( θ ( 7 For such θ no table is needed Next, we show how accurate (6 and (7 are by estiatg their approxiation errors The Taylor expansion of sθ near θ = 0 yields s ξ sθ = θ θ 6 ( 8 where ξ = hθ, 0 h Thus, sce s ξ = cosξ ( 9 and view of (5, an error bound on (6 is sθ = sθ θ θ 6 < N 6 ( 0 Siilarly, the Taylor expansion of yields θ cosξ = θ 4 ( 4 Thus, an error bound on (7 is = ( θ θ 4 4 ( which is negligible coparison to the bound on sθ While it is unlikely that (5 is satisfied for a given θ [ 0,, if we let B> N be the nuber of bits θ, then we can express θ = + where = d + + d N N ( = d N + N + + d B B ( 4 with d i { 0, } Clearly, satisfies (5 If we substitute θ = + for φ ( and expand cos( + and s( +, we obta: = cos s ( 5 = cos + s and = 0 cos 0 s ( 6 = 0 cos + 0 s Now the rotation ( is decoposed to two stages: a coarse rotation (6 by followed by a fe rotation (5 by With this partitiong (5 and (6 can be applied to the fe stage: = ( ( 7 = ( + A benefit of this partitiong is that the functions cos and s (6 depend only on the N ost significant bits of the angle θ They can be stored a sall look-up table This results a significant ROM size reduction However, the approxiation (6 troduces additional error We now seek to achieve an overall precision coparable to that the ipleentation havg one stage and a large ROM table Defg the approxiation errors s θl = s and cos θl = cos ( and neglectg ters that are products of error ters or products of an error ter and s, which is always sall, we calculate the total error as the difference between calculated usg (5 and (6 and calculated usg quantized s and cos (6 and usg (7 stead of (5 We obta: = 0 ( cos θm cos + cos θl cos s θl s 0 ( θm cos + θl s θl cos ( 8 s cos Coparg this error estiate with ( and (4 it is evident that, so long as the errors due to cos θl and s θl are sufficiently sall, the error (8 can be ade coparable to that of (4 by reducg the cos θm and s θm values, ie, by creasg the nuber of bits the se/cose saples stored the ROM For exaple, if we add one ore bit to the se/cose saples, then cos θm < N and < N Therefore, fro (8, we have s θm = ( N ( + 6+ ( 4 N ( 9 which is saller than (4 A siilar relationship can be found for This deonstrates that, if we add one ore bit of precision to the ROM for the coarse stage, we can achieve the sae precision as that the one-stage case, but with a significantly saller ROM A straightforward ipleentation of this ethod is illustrated Fig The three error sources cos θm, s θm and s θl are shown The uch saller error source cos θl has been neglected The thick le depicts the path along which the ROM quantization error cos θm propagates to The error cos θm is ultiplied by 0 and then by cos as it propagates along this path to becoe cos θm 0 cos when it reaches the output This atches the error ter (8 obtaed fro our calculation In subsequent discussions θ s 0 0 s < 0 ( N + 4N 4 + N ( N + 4N 4 + N 6 θm s cos N M word s ROM cos θm s Fig Preliary architecture θl cos

3 we will use this graphical approach to fd the error at the output due to various error sources The ROM table this preliary architecture contas any fewer se/cose saples coparison to the nuber of saples needed to ipleent ( usg a conventional (sgle stage table-lookup approach Although the approxiation (6 troduces additional error, so long as that error is saller than the conventional ROM quantization error, we can crease the precision of the saples our sall ROM table such that, overall, precision is not sacrificed In prciple, we can reduce the hardware coplexity significantly one block of our structure, with the correspondg accuracy loss copensated by higher precision fro another block, and at the cost of a slight crease the coplexity of that block As a result, the coplexity of the overall structure is reduced without loss of accuracy We will now exploit this idea aga to further reduce the coputational coplexity Siplification of the coarse stage We can factor out the cos ter (6 to obta = cos ( 0 0 tan ( 0 = cos ( tan Let tanθ be tan rounded upward at the ( N -rd bit In other words, writg tan as the bary nuber tan = 0b b N b N +, where b i { 0, } ( tanθ is obtaed fro tan accordg to tan θ = 0b b N ( + 00 Obviously, 0 tanθ tan N ( The N -bit nuber tanθ decreases the nuber of partial products needed coputg 0 tanθ and 0 tanθ to at ost a third of those needed for 0 tan and 0 tan The resultg fe-stage angle is θ l = θ θ Thus, as [5], a odified fe-stage angle copensates for a siplified coarse-stage angle If θ l satisfies θ l < N ( 4 then we have sθ l θ l < N 6 That is, the approxiations sθ l = θ l and l = θ l can be applied as discussed Section The proof that (4 holds is as follows: Proof: Accordg to the ean value theore ( tanθ tan ( θ = tan ξ ( 5 where ξ = + ( θ h, 0 h The derivative tan ξ satisfies tan ξ = + ( tanξ, for every ξ ( 6 Re-arrangg (5, and usg (6, we have θ = ( tanθ tan ( tan ξ tanθ tan ( 7 Hence, fro (, 0 θ < N ( 8 By defition, 0 < N ( 9 Therefore, subtractg (8 fro (9 yields N < ( θ < N ( 0 which is exactly (4 because θ l = θ θ = + θ = ( θ ( which concludes our proof This dicates that, stead of storg the tan values ROM, we ay store tanθ, which has N bits for each saple, and we ay store θ This results a reduction of the ultiplier size the coarse stage The difference between θ and can be copensated the followg fe rotation stage Furtherore, the approxiations (6 and (7 still apply to θ l, view of (4 We can now ipleent the coarse rotation stage as follows: = 0 0 tanθ ( = tanθ The factor can be applied to the output of the second stage because, of course, the two stages are perutable 4 Reduction of ultiplier size the fe stage In the fe rotation stage, the coputations volved generatg are = ( θ l θ l = ( θ l θ l ( Sce θ l < N it follows that θ l can be expressed as θ = l s s s θ N + θ N θ N + ( 4 where s is the sign bit The N MSBs do not fluence the result This property helps to reduce the size of the ultipliers that ipleent ( Even ore savgs hardware can be achieved by further reducg ultiplier size, with just a sall loss of accuracy Let [ ] represent the N MSBs of as = s y y N y N + = [ ] + ( 5 Then we ust have < N The error contributed to the product θ l by usg [ ] stead of is θ l [ ]θ l = θ < N ( 6 l Therefore, for N-bit precision, the ultiplication θ l can be accoplished with a ( N ( N ultiplier This ethod can be applied to the coputation of θ l Defg [ θ l ] as the N MSBs of θ l, and lettg θl denote the reag LSBs, we have [ θ l ] = s s s θ N + θ N ( 7 and = θl θ N + ( 8

4 The error calculatg θ l usg [ θl ] stead of θ l is ([ θ l ] + θl [ θ l ] [ θ l ] θl < N ( 9 Thus θ l can be ipleented with an ( N ( N ultiplier, sce the N MSBs of [ θ l ] are just sign-bits 5 Scalg-ultiplier siplification As entioned Section, the scale factor can be applied at the output of the fe stage A straightforward ipleentation would use the full wordlength of the product =, which would require a ultiplier of size N N But this ultiplier s size can be reduced as follows: By defg [ ] as the N + MSBs of the scale factor can be written as cos θ = [ ] + cos θ = [ ] ( 40 [ ] Let us defe δ = cos θ [ ] and, sce 0 θ π 4, we surely have [ ] > 05, and hence 0 δ < N ( 4 Movg the factor + δ to the fe stage, we have = ( θ l ( + δ θ ( + δ l cos θ ( 4 = + ( δ θ l θ l ( 4 The only significant error approxiatg (4 by (4 is the absence of the θ l δ ter the factor ultiplyg But this is tolerable sce, accordg to (4 and (4, θ l δ < N ( 44 In view of (4 we have 0 θ l < N which, cobed with (4, yields N δ θ l < ( 45 Thus, if we truncate δ θ l to N bits, only the least significant N bits the truncated result will be non-sign bits Therefore, our coputation of ( δ θ l (4, if we truncate to N bits, we can use an ( N ( N ultiplier, with the product s error bound beg N δ θ l < N ( 46 The factorization of (40 allows a reduction of the ultiplier to approxiately its origal size In this case, the values of [ ] and δ are stored the ROM stead of The fal architecture is shown Fig, where the size of the ultipliers is shown with parentheses 6 Coputational accuracy and wordlength In this section we study the effect of quantization errors on the fal output s coputational accuracy and the ost efficient way to quantize the data for a given accuracy In our algorith, the errors can be classified to three categories The first category is the quantization of the values the ROM table The second category is the error due to the truncation of data before ultiplications, to reduce ultiplier size The third type of error is that resultg fro approxiatg tanθ l by θ l Quantization errors are arked Fig with light arrows The total error can be obtaed by cobg the errors propagated fro each source To calculate the propagated error at the output with a given error at the source, we can first identify all paths by which the error reaches the output and then use the approach discussed Section Let us first exae all the error sources and detere their effects on Table I displays this foration (Siilar results apply to TABLE I Effect of errors at the output Error source Error at the output ε ε quantizg θ ROM quantizg δ ROM ε ε ε truncatg for θ l θ l ε ε 4 truncatg for ( δ θ l ε4 [ ( δ θ l ] ε 5 truncatg θ l for θ l θ l ε 5 ε 6 truncatg θ l for ε 6 [ ( δ θ l ] truncatg before its ε 7 ε 8 ε 9 scalg by [ ] approxiatg sθ l by θ l neglectg δ θ l (4 ( θ l 6 ( θ l δ The values stored the ROM are tanθ, [ ], θ and δ, where tanθ and [ ] are MSBs of tan and, respectively A loss of precision due to ROM quantization error depends only on the nuber of bits used representg θ and δ The total error can be obtaed by cobg all the ters the third colun of Table I: θ l ε 5 + ε 7 + θ l ( θ l 6 δ ( 47 Sce ε 6 Table I is a truncation error, we have ε 6 0 If we quantize δ by roundg it upward before storg it ROM, then ε 0 This way such errors tend to cancel each other Cancellg errors are grouped together (47 sce the agnitude of their cobed error is no greater than the larger of the two This yields seven ters (47, each contributg a axiu possible error of N If the ultiplier sizes are as dicated Fig, the total error is bounded by 7 N Fro the above analysis it can be seen that the coputation errors resultg fro hardware reduction have siilar ε + ( ε + ε 6 θ l ε +( δ θ l ε4

5 agnitudes and no particular source doates This sees to provide the best trade-off between the hardware coplexity and the accuracy of the entire syste Accordg to (47, the total output error can be reduced by creasg the ternal data wordlength and the wordlength of each saple the ROM For each bit crease, we get one ore bit of precision at the output Therefore, we can design the processor to have the iu hardware for a given precision requireent Next, we give a siulation exaple to illustrate this ethod Exaple: A cose wavefor with an error less than is specified Accordg to (47, we should add three bits to all data dicated Fig Fig a depicts [ ], ie the output of the coarse stage scaled by [ ] Fig b shows the fal error Notice that the axiu error is approxiately 5 0 5, which is considerably saller than θ cos(θ * [cos(θ ] θ (radians (a Output of the coarse stage x θ (radians (b Fal error N word ROM Fig Siulation result θ δ cos θ [ ] tanθ tanθ θ l ε 5 θl δ cos θ l θ N N ( ε 6 ε 9 7 Conclusion Based on the design ethod discussed, for a given accuracy requireent, an architecture with the least aount of hardware is produced by balancg the precision of terediate coputations and the coplexity of each arithetic block, while keepg the output error with the specified bound Furtherore, our architecture consolidates all operations to a sall nuber of reduced-size ultipliers This perits us to take advantage of any efficient techniques that have been developed for ultiplier ipleentation, such as Booth encodg, thereby yieldg a saller and faster circuit than those previously proposed References [] Ahn, S Nah, and W Sung, VLSI design of a CORDIC-based derotator, Proc 998 IEEE Int Syp Circuits Syst, vol II, pp 449-5, May 998 [] S Wang, V Piuri, and E Swartzlander, Jr, Hybrid CORDIC algoriths, IEEE Transactions on Coputers, vol 46, pp 0-7, Nov 997 [] A Madisetti, A Kwentus, and A N Willson, Jr, A se/ cose direct digital frequency synthesizer usg an angle rotation algorith, Proc 995 IEEE Int Solid-State Circuits Conf, pp 6-6, Feb 995 [4] L Tan and H Saueli, A 00-MHz quadrature frequency synthesizer/ixer 08 µ CMOS, IEEE J Solid-State Circuits, vol 0, pp 9-00, Mar 995 [5] A Madisetti, VLSI architectures and IC ipleentations for bandwidth efficient counications, PhD dissertation, University of California, Los Angeles, 996 ( N N [ ] 0 tanθ 0 δ cos θ l θ N N ( θ l ε N (--- N ultiplier (b Coarse stage ε 4 N N ( Details Fig b Details Fig c (a Overall architecture (c Fe stage Fig Angle-rotator architecture