Low complexity bit parallel multiplier for GF(2 m ) generated by equally-spaced trinomials

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1 Inforation Processing Letters Low coplexity bit parallel ultiplier for GF generated by equally-spaced trinoials Haibin Shen a,, Yier Jin a,b a Institute of VLSI Design, Zhejiang University, Hangzhou, China b Departent of Electrical Engineering, Yale University, 10 Hillhouse Avenue, New Haven, CT 0650, USA Received 0 February 007; received in revised for 14 May 007; accepted 3 January 008 Available online 16 March 008 Counicated by D. Pointcheval Abstract Based on the shifted polynoial basis SPB, a high efficient bit-parallel ultiplier for the field GF defined by an equallyspaced trinoial EST is proposed. The use of SPB significantly reduces tie delay of the proposed ultiplier and at the sae tie Karatsuba ethod is cobined with SPB to decrease space coplexity. As a result, with the sae tie coplexity, approxiately 3/4 gates of previous ultipliers are used in the proposed ultiplier. 008 Published by Elsevier B.V. Keywords: Shifted polynoial basis SPB; Equally-spaced trinoial EST; Karatsuba ethod; Bit-parallel ultiplier; Cryptography 1. Introduction Finite filed operations are used in any areas such as coding theory, coputers algebra, cobinatorial designs and cryptography [3,6,13]. Aong these operations, ultiplication is of the ost iportance because other coplex operations such as exponentiation, division, etc. can be carried out through iterative ultiplications. Based on the advanced design technology nowadays, ore and ore logic gates can be located on a single chip which akes the ipleentations of parallel architectures possible and reasonable. In order to iprove the efficiency of cryptographic syste and coding syste, any bit-parallel ultiplier archi- * Corresponding author. E-ail addresses: shb@vlsi.zju.edu.cn H. Shen, yier.jin@yale.edu Y. Jin. tectures have been proposed recently to achieve high coputation speed [,5,8,10 1,14,15]. Also, various basis except for polynoial basis PB, dual basis DB, and noral basis NB are developed in order to further reduce the critical path of ultipliers with even fewer logic gates. And certain types of irreducible polynoials are used to iprove the perforance of ultipliers in which trinoial is one of the best choices [1]. Although different architectures can be evaluated fro several points of view, tie coplexity and space coplexity are often the two ost iportant paraeters. The forer is defined as the elapsed tie between input and output of the circuit ipleenting the ultiplier, and it is usually expressed as the su of T A the delay of a two input AND gate and T X the delay of a two input XOR gate with corresponding coefficients. The latter is weighed by the nubers of AND gates and XOR gates used in ultiplier denoted as #AND /$ see front atter 008 Published by Elsevier B.V. doi: /j.ipl

2 1 H. Shen, Y. Jin / Inforation Processing Letters and #XOR. In the finite field generated by trinoials, the ost efficient ultiplier architecture nowadays contains AND gates and 1 XOR gates with tie delay of T A log T X [5]. If the trinoial is an equally-spaced trinoial EST in the for of fx x + x + 1is even, the best result is TieDelay T A log 1 T X, #AND, #XOR. As entioned above, although we can put uch ore logic gates in a single chip than ever before, the O coplexity of AND and XOR gates still costs considerable chip area. Many researchers are devoted to the reduction of ultipliers space coplexity without increasing their tie coplexity. M. Elia et al. [1] use Karatsuba Ofan ultiplication and achieve even lower space coplexity but their ethod requires two ore T X delays. In this paper, we propose a new bit-parallel ultiplier for GF defined by EST fx x + x + 1 using shifted polynoial basis which can significantly reduce the critical path. Also, we use the well-known Karatsuba Ofan ultiplication [4] to decrease the space coplexity of the proposed bit-parallel ultiplier. Based on these two ethods, an high efficient architecture is constructed. The space coplexity of the proposed ultiplier is about 3/4 of the previous result while the tie coplexity atches the best efficient ultipliers ever known of T A log 1 T X. The irreducible EST in the for of x + x + 1exist when 3 i where i is a non-negative integer. Although the nuber of irreducible EST is not that redundant, they can be used in source critical area, e.g., sartcard where field polynoials are often fixed for the sake of lowering chip area. The rest of paper is organized as follows: Section introduces the representation of shift polynoial basis SPB. Based on this representation a new bit-parallel ultiplier architecture is proposed in Section 3. Section 4 presents the coparison between the proposed ultiplier and soe others. Finally the conclusions are drawn in Section 5.. Shifted polynoial basis SPB Shifted polynoial basis SPB is first introduced by H. Fan and Y. Dai [5] which is derived fro polynoial basis PB by adding a shift variable into each field eleent in order to iprove the efficiency of ultiplier. In PB representation, each eleent of GF is represented by a different binary polynoial of degree less than. More explicitly, a bit string a 1, a,...,a 1,a 0 is taken to represent binary polynoial as 1 ax a i x i a 1 x 1 + a x + + a 1 x + a 0,a i GF. Here the set M {x 1,x,...,x,1} represents a polynoial basis. The addition of bit strings corresponds to addition of binary polynoials. Multiplication is defined in ters of an irreducible binary polynoial fx of degree, called the field polynoial for the representation. The product of two eleents is siply the product of the corresponding polynoials, reduced odulo fx. Here goes the definition of SPB over GF in GF. Definition 1. See [5]. Let v be an integer and the ordered set M {x i 0 i 1} be a polynoial basis of GF over GF. The ordered set x v M : {x i+v 0 i 1} is called the shifted polynoial basis SPB with respect to M. In reality, let fx x + x k + 1 be an irreducible trinoial over GF, M {x i 0 i 1} be a PB and x v M : {x i v 0 i 1} be an SPB, where 0 v 1 and x is a root of fx 0. It has been proved that the best value of v is k or k 1 with which the ultiplier has lowest coplexities [5]. Fro now on, we denote that v equals to k and x k M : {x i k 0 i 1} is the SPB. A field eleent ax can be uniquely represented as ax a 1,a,...,a 1,a 0 x k 1 a ix i with respect to SPB. It is easy to transfor the eleents between PB and SPB representations. Let dx 1 d ix i and ax 1 v i v a v+i x i be two eleents represented in PB and SPB. The conversions between these two representations are showed by the following two forulae: 1 dx d i x i 1 v 1 v d i x i + d i x i + 1 i v 1 i v d i x v+i + x i v 1 d +i x i + d +i v x i,

3 H. Shen, Y. Jin / Inforation Processing Letters v 1 v ax a v+i x i a v+i x i i v + 1 i v 1 v a v+i x +i + x v+i a i x i + 1 i v v 1 a v +i x i + a i x i. According to the above forulae, the conversion between these two representations only needs v XOR gates and 1T X delay with parallel coputing. Multiplication on SPB is the sae as that on PB except that reduction step abides by two forulae: x i x k+i + x i, where v i v, x i x +i + x k+i, where v i v + 1. If the irreducible trinoial is fx x + x + 1 where k v,wehave: x i x i + x i, where i, x i x +i + x +i, where i Multiplier based on SPB Karatsuba ethod has been used to iprove the efficiency of bit-parallel ultiplier for GF generated by an AOP All-One Polynoial and a trinoial in [1,7,9]. This ethod can reduce the space coplexity by approxiately a factor of 3/4 because it replaces the ultiplication by three half-sized integers ultiplications. This ethod, however, will increase the tie delay which akes the decrease of space coplexity less attractive. Here, by using SPB representation, we odify the Karatsuba ethod and propose a new ultiplier architecture with significantly low space coplexity and tie delay in the fields generated by EST. Assue that ax x 1 a ix i, bx x 1 b ix i are two eleents in SPB representation. We partition ax A x + B and bx C x + D, where A C 1 1 a i x i, B b i x i, D 1 1 a i+ x i, b i+ x i. Then, we ultiply ax and bx with Karatsuba ethod and do soe transforations as follows: S ax bx A x + B C x + D AC x + BD + AC + BDx + A + BC + Dx AC x + BD x + AC x + BD + A + BC + Dx. 1 The right side of 1 can be divided into two parts: S re, which needs further reductions odulo fx and S nore, which does not need any reductions because the exponents of all eleents in S nore are located in the interval of [, 1]. These two parts are listed separately as follow: S re AC x + BD x + AC x + BD, S nore A + BC + Dx. i We consider S re in detail first. Let 1 1 AC a i x i b i x i p i x i. These p i s can be coputed as follows: ij0 a j b i j, 0 i 1, p i 1 ji +1 a j b i j, i. Siilarly, we get the coefficients q i sofbd q ix i as: q i ij0 a j+ b i j+, 0 i 1, 1 ji +1 a j+ b i j+, i. 3 According to and 3, the result of the expression AC x + BD can be coputed quickly. AC x + BD p i+, i 1, z i x i p i+ + q i, 0 i 1, 4 q i, i. Fro 4, we can find that, for i 1, z i contains i eleents, for 0 i 1, z i contains eleents and for i, z i contains 1 i eleents. Thus, circuit ipleentation of AC x + BD requires + XOR gates. The calculations of AC and BD both need

4 14 H. Shen, Y. Jin / Inforation Processing Letters Table 1 The space and tie coplexities of S re AC x + BD + AC x + BDx od fx Operation #AND #XOR Tie delay T A + log T X AC x + BD AC x + BD + AC x + BDx 1T X Total T A + log T X 4 AND gates. As a result, AC x + BD totally requires AND gates, XOR gates and the tie delay is T A + log T X. Note that S re needs to be reduced odulo fx and we partition AC x + BD into three parts naed r 1, r, r 3. AC x + BD r1 x + r + r 3 x, where r 1 1 i i z i x i+, r 1 z ix i, r 3 z i x i. Sequentially we have AC x + BD x r 1 x + r x + r3. Because the exponents of r 3 x in AC x + BD and r 1 x in AC x + BD x are beyond the range [, 1], they need to be reduced as follows: S re od fx r 1 x + r + r 3 x + r 1 x + r x + r3 od fx r 1 x + r + r 3 + r 3 x + r 1 + r 1 x + r x + r3 r 1 + r + r + r 3 x. 5 In 5, identical parts are reoved under the addition law in GF. Therefore 5 needs XOR gates and require 1T X delay. In conclusion, the generation of S re needs AND gates and + XOR gates with tie delay of T A log T X T A + log T X. The space and tie coplexity on coputing S re are suarized in Table 1. ii Here we consider S nore in detail. Because S nore A + BC + Dx needs no further reduction, it can be carried out by an -fold left shift of A+BC +D. The shift operation can be realized by a siple rewiring without any logic gates. The space and tie coplexity on coputing S nore are suarized in Table. Fro Tables 1 and, the coputations of S re and S nore have the sae tie delay so they can be calculated in parallel siultaneously. Since C S od fx S re od fx+ S nore, another XOR gates and 1T X delay should be added Table The space and tie coplexities of S nore A + BC + Dx Operation #AND #XOR Tie delay A + C,B + D 1T X A + CB + Dx 4 1 T A + log T X Total T A + log T X Table 3 Coparison of bit-parallel ultipliers when fx x + x + 1 Proposals #AND #XOR Tie delay Wu [8] T A log 1 T X Sunar [1] T A log 1 T X Iana [15] T A log T X Our proposal T A log 1 T X when coputing the final result. The total space coplexity and tie coplexity of the proposed architecture can be calculated fro Tables 1, and extra gates on adding S re and S nore together: #AND , #XOR , Tie delay T A log T X. Because is even, log log 1, the tie coplexity can be rewritten as T A log 1 T X. 4. Coparison In the fields generated by trinoials, low coplexity ultipliers ainly use polynoial basis. Table 3 gives a coparison of four different ipleentations of bit-parallel ultipliers in the class of fields generated by an equally-spaced trinoial x + x + 1 according to space coplexity and tie coplexity. Fro Table 3, the proposed ultiplier requires about 5 percent fewer circuit gates than the previous best architectures while with the sae tie coplexity of T A +1+ log 1 T X. This erit enables the pro-

5 H. Shen, Y. Jin / Inforation Processing Letters posed ultiplier to be used in space critical area such as sartcard, RFID tags, etc. 5. Conclusion In this paper, a new bit-parallel ultiplier architecture is proposed. In this architecture, SPB and Karatsuba ethod are cobined which can reduce the tie coplexity and space coplexity, respectively. This ultiplier can be used in area-critical occasion because of its low space coplexity in GF defined by EST. To find ore efficient polynoials which can use the ethod proposed in this paper should be the future work. References [1] M. Elia, M. Leone, C. Visentin, Low coplexity bit-parallel ultipliers for GF with generator polynoial x + x k + 1, Electronic Letters [] A. R-Masoleh, M.A. Hasan, A new construction of Massey Oura parallel ultiplier over GF, IEEE Transactions on Coputers [3] R. Lidl, H. Niederreiter, Introduction to Finite Fields and Their Applications, Cabridge Univ. Press, New York, [4] D.E. Knuth, The Art of Coputer Prograing, vol., Addison-Wesley, [5] H. Fan, Y. Dai, Fast bit-parallel GF n ultiplier for all trinoials, IEEE Transactions on Coputers [6] A.J. Menezes, I.F. Blake, X. Gao, R.C. Mullin, S.A. Vanstone, T. Yaghoobian, Applications of Finite Fields, Kluwer Acadeic, [7] M. Leone, A new low coplexity parallel ultiplier for a class of finite fields, in: Cryptographic Hardware and Ebedded Systes CHES 001, 001, pp [8] H. Wu, Montgoery ultiplier and squarer for a class of finite fields, IEEE Transactions on Coputers [9] K.-Y. Chang, D. Hong, H.-S. Cho, Low coplexity bit-parallel ultiplier for GF n defined by all-one polynoials using redundant representation, IEEE Transactions on Coputers [10] H. Wu, M.A. Hasan, I.F. Blake, S. Gao, Finite field ultiplier using redundant representation, IEEE Transactions on Coputers [11] Ç.K. Koç, B. Sunar, Low-coplexity bit-parallel canonical and noral basis ultipliers for a class of finite fields, IEEE Transactions on Coputers [1] B. Sunar, Ç.K. Koç, Mastrovito ultiplier for all trinoials, IEEE Transactions on Coputers [13] D. Hankerson, A. Menezes, S. Vanstone, Guide to Elliptic Curve Cryptography, Springer-Verlag, 004. [14] H. Wu, M.A. Hasan, I.F. Blake, New low-coplexity bit-parallel finite field ultipliers using weakly dual bases, IEEE Transactions on Coputers [15] J.L. Iana, J.M. Sanchez, F. Tirado, Bit-parallel finite field ultipliers for irreducible trinoials, IEEE Transactions on Coputers