Short Papers. Efficient Thermal Simulation for 3-D IC With Thermal Through-Silicon Vias

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1 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 31, NO. 11, NOVEMBER Short Papers Efficient Theral Siulation for 3-D IC With Theral Through-Silicon Vias Dongkeun Oh, Charlie Chung Ping Chen, and Yu Hen Hu Abstract A novel virtual power source (VPS ethod is proposed that can significantly speedup 3-D integrated circuit (IC theral siulation with sparely deployed theral TSVs leveraging Green function-based analytical spectral ethod. Specifically, it is shown that the ipact of TSVs with nonhoogeneous theral conductivity on theral siulation ay be odeled as VPSs located at esh grids inside the theral TSVs. Using this VPS odel, the teperature distribution over the entire 3- D IC ay be obtained by solving for the theral distribution of a therally hoogeneous substrate in the presence of these VPSs. As such, the fast spectral ethod ay be applied to accelerate the siulation. Significant (3 100 ties speedup over a baseline finite difference ethod ipleentation has been observed in preliinary siulations. Index Ters Analytical ethod, Green function, theral siulation, through-silicon via, virtual power source. I. Introduction Heat dissipation is a key design consideration of odern 3-D integrated circuits (ICs [1]. One effective solution is to incorporate theral through-silicon vias (TSV that act as heat vents for inner-layer circuitry to release heat generated during coputation to the abient [2], [3]. Strategically placed theral TSVs helps alleviating internal hot-spots and prolongs the life-span of the 3-D IC chips [4], [5]. If a ediu has hoogeneous theral conductivity, analytical Poisson equation solvers [1], [6], [7] can be applied to provide accurate theral ap. Specifically, for a point power source, the corresponding steady-state teperature distribution can be described analytically by a Green s function. Due to the specific forat of the Green function, convolution ay be carried out using spectral transforation [such as discrete cosine transfor (DCT] to achieve order of agnitude speedup [7] copared to traditional finite difference ethod (FDM- based theral siulators [8], [9]. However, this fast analytical spectral theral siulation ethod is applicable only to a hoogeneous ediu. With the presence of TSVs, this ethod is not applicable. In this paper, a novel virtual power source (VPS ethod is proposed to resolve this proble. Specifically, it is shown that the ipacts of nonhoogeneous theral conductivity of TSVs on teperature distribution can Manuscript received August 16, 2011; revised Noveber 16, 2011 and February 14, 2012; accepted March 25, Date of current version October 19, This paper was recoended by Associate Editor P. Saxena. D. Oh and Y. H. Hu are with the Departent of Electrical and Coputer Engineering, University of Wisconsin-Madison, Madison, WI USA (eail: doh2@wisc.edu; hu@engr.wisc.edu. C. C.-P. Chen is with the Departent of Electrical Engineering, National Taiwan University, Taipei 10617, Taiwan (e-ail: cchen@cc.ee.ntu.edu.tw. Color versions of one or ore of the figures in this paper are available online at Digital Object Identifier /TCAD /$31.00 c 2012 IEEE be odeled by a set of (equivalent VPSs at the TSV locations, while the theral conductivities at the TSVs will be reset to the hoogeneous value of its surrounding substrates. As such, the fast spectral analytical theral siulation ethod can be applied with these VPSs taken into account. This ethod can be applied to any situation when the locations of esh grids with nonhoogeneous theral conductivity is relatively sparse, and hence proises significant speedup of 3-D IC theral siulation with TSVs. Matheatically, the VPS leverages the low rank property of the theral resistance variations due to sparseness of the theral via. This is siilar to the approach taken in [10], which, however, is in the field of clock network. Below, preliinaries of 3-D theral siulation will be reviewed in Section II. The VPS ethod will be derived in Section III. Siulation results will be presented in Section IV. II. Background The steady-state teperature T (r at location r inside the substrate can be described by the Fourier Kirchhoff heat conduction equation without tie-dependent ters as follows: (κ(r T (r g(r (1 where κ(r is the theral conductivity and g(r is the power density of the heat source. After partitioning the substrate coordinates into esh grids, a FDM approxiation of (1 leads to a theral conductance equation as follows: Gt g (2 where G is a theral conductance atrix whose eleents also depend on κ(r at each esh grid, t is the steady-state teperature at each esh grid, and g is the power eitted by sources at each esh grid. Thus, (2 is applicable to situations when theral conductivity is nonhoogeneous over the substrate. Note that the inus sign in (1 is erged into coefficient of the G atrix, and both t and g will have nonnegative eleents in practice. In a therally hoogeneous substrate, where κ(r κ is a constant through each esh grid, (1 reduces to the Poisson equation 2 T (r g(r/κ (3 which is a linear shift invariant syste. As such, its solution ay be represented by an integral equation T (r G(r, r g(r dr (4 V where G(r, r, called the Green function is the solution to the Poisson equation when the power source is an ipulse function δ(r r at position r as follows: 2 G(r, r δ(r r. (5 κ

2 1768 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 31, NO. 11, NOVEMBER 2012 TSVs, the conductance atrix G in (2 ay be decoposed into two parts as follows: G het G ho + G via (8 Fig. 1. Cross section of a three-layer 3-D IC with TSVs (odel A, therally hoogeneous layers without TSVs (odel B, and the difference theral conductivity in TSV region (odels C and D (upper row fro left. Corresponding G het, G ho, and G via atrices (lower row fro left. A significant advantage of the Green function approach is that the Green function ay be expressed analytically. In particular, in the Cartesian coordinate, G(r, r ay be represented in the for [11] ( πx ( πx G(r, r C,n (z, z cos cos 1 n1 ( nπy cos b cos a ( nπy b a. (6 If the spatial coordinates are quantized into esh grids, (4 becoes a resistive theral equation Rg t. (7 Copared to (2, one has R G 1 (for κ(r κ. Since each eleent of the R atrix is a discretized version of (6, fast algoriths such as the spectral ethod using table lookup and DCT have been proposed [6], [1], [7] that significantly accelerated the speed of theral siulation. Let N be the nuber of esh grids in a layer of a 3-D IC, it is estiated that [6] the coputation coplexity of a L-layer 3-D IC fullchip siulation will be O(L 2 Nlog(N. III. VPS Theral Model A theral through-silicon via (TSV is a vertical therally highly conductive connector connecting different layers of a 3-D IC for rapid heat ventilation of inner layers. Since it occupies space over ultiple layers, it is often placed strategically and sparsely over the chip. A 3-D IC equipped with theral TSVs will have heterogeneous theral conductivity in layers containing TSVs. Consequently, such a 3-D IC cannot take advantage of the fast spectral theral siulation ethod [6], which is applicable only to hoogeneous theral conductance layers. In this paper, leveraging on the sparseness of the theral TSVs, a novel ethod is proposed that allows fast spectral analytical theral siulation ethod to be applied to 3-D IC with theral TSVs. Consider a substrate with hoogeneous theral conductivity and a few sparsely deployed TSVs. Due to the presence of where G het is the conductance atrix with the presence of theral TSVs (heterogeneous theral conductivity, and G ho is the conductance atrix in the absence of TSVs (hoogeneous theral conductivity. G via is the difference between the theral conductivity of the TSVs and that of the substrate. This relation is illustrated in Fig. 1. Exploiting the sparse presence of TSVs and relatively sall area each TSV occupies, the G via is a sparse atrix containing very few nonzero eleents. If one rearranges the ordering of esh grids of the teperature vector t and the corresponding power source vector g in (2, these nonzero eleents of G via ay be confined to a sall corner. Recall that N is the nuber of esh grids of a horizontal layer of substrate, one ay represent the N N atrix G via as follows: G via 0 G 0 G I UV T (9 where G is a dense atrix, N. Clearly, the rank of G is no larger than. To ephasize the difference between heterogeneous and hoogeneous theral conductance, one adds a subscript het to the theral resistance atrix in (7 to ephasize the presence of TSVs as follows: t het Ghet 1 g R hetg. (10 Our goal is to copute t het using R ho instead of R het because then the analytical spectral ethod ay be applied to expedite the coputation. This would be possible only if the power source vector g is replaced by g ho such that g ho g + g vir (11 t het R het g R ho g ho R ho (g + g vir. (12 In above, g vir is a VPS vector that encapsulates the ipact of heterogeneous theral conductance of TSVs. More specifically g vir Rho 1 (R het R ho g. (13 Now, recall a Woodbury atrix inversion identity [12] (A + UCV T 1 A 1 A 1 U(C 1 + V T A 1 U 1 V T A 1. Substituting A G ho, C I, and (8 and (9, one has R het Ghet 1 (G ho + UV T 1 (14 Gho 1 G 1 ho U(I + VT Gho 1 U 1 V T Gho 1 R ho R ho U(I + V T R ho U 1 V T R ho. To facilitate derivation, partition the hoogeneous resistance atrix as follows: R11 R R ho 12. (15 R 21 R

3 OH et al.: EFFICIENT THERMAL SIMULATION FOR 3-D IC 1769 Using (15 and (9, one ay siplify ters inside the parenthesis of (14 as follows: I + V T R ho U I + R 0 G 11 R 12 0 R 21 R I I + G R. (16 Therefore, fro (14 and above, one has R 1 ho (R het R ho U(I + V T R ho U 1 V T R ho 0 [I I + G R ] 1 0 G Rho (I + G R 1 R G ho. (17 Because there is no power sources inside the theral TSVs, one ay express the power source vector g as (0 is a 1 zero vector g1 g. 0 Substituting these relations into (13 where g vir Rho 1 (R het R ho g ( R11 g 0 (I + G R 1 1 G R 21 g 1 [ ] 0 (I + G R 1 G t ho, t ho, R 21 g 1 (19 is the teperature easured at the TSV locations assuing that the substrate has no TSVs and hence has hoogeneous theral conductivity. Equation (18 is significant in several ways. 1 It shows that the locations of the VPSs atch exactly as those coordinates of theral TSVs. 2 It shows that g vir ay be coputed efficiently given R, G, and t ho, with O( 2 log( operations. Suarizing the above derivations, the VPS ethod is listed below. [ VPS (Hybrid Method: Given R ho and G via, and g g T 1 0 ] T : 1 copute t ho, according to (19; 2 copute g vir according to (18; 3 copute teperature t het according to (12. A. Coputation Coplexity Analysis In the VPS algorith, t ho, ay be coputed using the fast spectral ethod since R 21 is a subatrix of the R ho atrix. However, for N, a hierarchical ethod [13] proposed recently ay yield even ore coputation savings. To copute g vir, it is required to solve a linear syste of equations as follows: (I + G R g vir, G t ho,. (20 In general, G in (18 is a block diagonal atrix of which a diagonal block corresponds to the esh grids occupied by a TSV (refer to Fig. 1. On the other hand, R is typically a dense atrix. Hence, the coputation coplexity is doinated by the size of the R atrix. In the worst case, the coputation coplexity is O( 3. In the last step of the VPS algorith, note that there is no coputation overhead to for the g ho power source vector since g 1 and g vir occupy nonoverlapping esh grids. The coputation cost in this step will be the sae as that of applying the spectral ethod, i.e., O(L 2 NlogN. B. Teperature-Dependent Theral Conductance The VPS hybrid steady-state theral siulation ethod is developed based on an assuption that the theral conductivity is teperature independent, i.e., κ(r, T κ(r. However, such an assuption ay be invalid when the teperature swing over too large range. If the teperature dependency is very significant (e.g., large theral conductivity variation for sall teperature change, then the VPS ethod will be of less use. On the other hand, if the conductivity variations due to teperature changes is only at hot-spots, then such conductivity variations at the hot-spots, which hopefully are sparsely distributed over the substrate, ay also be handled with the virtual power source ethod. Specifically, one would propose the following steps as an extension of the VPS ethod. Specifically, one ay odify (8 with inclusion of a teperature correction ter G het G ho + G via + G ther (21 where G ther is the change of theral conductivity due to teperature change. Initially, one would perfor the VPS hybrid algorith assuing that the theral conductivity is teperature independent, naely, G ther 0. Once the teperature profile is coputed, one ay regenerate G het based on the estiated teperature profile. Then G ther will be the difference between the initial teperature independent G het and the newly coputed, teperature corrected G het. If the su of G via +G ther reains to be a sparse atrix, then the VPS ethod ay be reapplied with a new G atrix. Since the hot-spots are unlikely to colocate with the theral TSVs, the structure of the g 1 vector and the t ho, vector will be different as well. The overall coputation overhead, then depends on the degree of sparseness of G via + G ther. IV. Experient The effectiveness of the proposed VPS ethod will be validated using siulation experients. In the first experient, the teperature profile coputed by VPS ethod is copared to that coputed using a ultiphysics coercial siulator COMSOL (available at In the second experient, the advantages of VPS over FDM siulators in ters of speed and eory footprint will be deonstrated. Our software packages run on the achine with Intel core-2- duo 2.0 GHz icroprocessor and 3 GB ain eory.

4 1770 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 31, NO. 11, NOVEMBER 2012 TABLE I Execution of FDM by MATLAB and SuperLU Mesh Source Method MATLAB SuperLU MATLAB SuperLU T G (s n/a T C (s n/a T t (s n/a Me (MB n/a Fig. 2. Design odel of TSV. TABLE II Execution of VPS Method by MATLAB and SuperLU Hybrid (VPS theral siulators are developed in MAT- LAB and C prograing environent. This siulator ipleents the VPS ethod as outlined above and include Green s function solution odule [6] using DCT and lookup table to expedite coputation. For the purpose of fair coparison, we developed FDM-based theral siulators in MATLAB and C as well. It uses unifor esh grid and just get a solution by inverting a conductance atrix and ultiplying it into a power vector. The left atrix division (MLDIVIDE MATLAB coand is used to solve the theral conductance equation (2. In C progras, we used SuperLU library (available at xiaoye/superlu/. Because FDM atrix is syetric positive definite, Cholesky decoposition can be applicable and faster than lower/upper triangular atrix decoposition (LU. However, it cannot be utilized to build virtual power vector in our ethod. Because different library uses different data structure and overall coplexity of Cholesky ethod is twice faster than LU ethod, we use LU ethod for FDM and assue that Cholesky ethod will be twice faster. For teperature coparison, the geoetric layout of the cross section of a three-layer 3-D IC substrate for the purpose of theral siulation is shown in Fig. 2. In this configuration, a TSV is placed in only the inner adhesive layer and two TSVs are placed in both layers. Power sources are laid out at the botto layer. The power sources at the botto layer eits 20 W uniforly. The conductivity of the silicon substrate is set to 100 W/K for the convenience and the conductivity of the adhesive inner layer is set to 1 W/K. The convection coefficients of the top and botto surface are set to and 200 W/K 2, respectively. Vertical walls are assued to be adiabatic. The first experient validates the accuracy of the proposed VPS ethod. With liited eory of our achine and huge eory consuption of COMSOL, a larger than usual TSV is used to highlight the ipact of TSVs and ease COMSOL siulation. In the experient of VPS ethod, ore practical TSV sizes and thicknesses of adhesive layer are used. In Fig. 3, the top surface teperature profile of the hybrid VPS ethod, unifor FDM, and COMSOL software are copared. Note that the teperature difference between these two ethods are well within the range of 0.5 C and 1 C [Fig. 3(c], which translates to a relative error of between 2% and 3%. A significant portion of this error is due to isatch Mesh Source N via L x,y &L z 250&60 μ 125&36 μ 62.5&18 μ By MATLAB T pre T via (s T C (s T t (s Me (MB By C With SuperLU T pre T via (s n/a T C (s n/a T t (s n/a Meory n/a of spatial esh grid between COMSOL and VPS ethod. COMSOL uses ultigrid ethod and the hybrid TSV ethod uses unifor esh grid sizes. As such, in the area of large teperature gradient, teperature of both ethods can differ uch ore than other sooth area. In the second experient, the execution speed and eory usage of the VPS ethod against the traditional FDM are exained. The sae generic 3-D structure as described in experient 1 is used, however, with different grid cell sizes and thickness of the adhesive layer. For the convenience, we assued that TSVs lie only in the adhesive layer but if we assue TSVs lie in the silicon layer as well, we can utilize siulation result with ore TSVs in the adhesive layer. For FDM siulation, we used saller esh grid due to the liit of eory and speed. In MATLAB ipleentation, the tie to build conductance atrix occupies ajority aount of coputation tie as the nuber of esh grid grows up. However, in C ipleentation with SuperLU library, atrix allocation is alost trivial but the coputation tie and eory consuption is rather huge. The power sources are confined to the botto substrate, evenly distributed at each grid cell. Thus, the nuber of grid cells at each layer, N 128 2, 256 2, and 512 2, respectively. Each TSV is a 3-D cylinder with its height equal to a single vertical esh grid and the diaeter of each TSV is equal to the size of three spatial esh grid. The nuber of TSVs varies at different grid sizes. Details are suarized in Table II.

5 OH et al.: EFFICIENT THERMAL SIMULATION FOR 3-D IC 1771 Fig. 3. With TSV (a 3-D plot of teperature distribution using COMSOL, (b teperature distribution coputed using VPS (hybrid ethod, and (c teperature difference between (a and (b. Note that it ranges between 0.5 C and 1 C. The experient includes several steps. Initially, the data table of the trigonoetric ters of Green s function (6 for each grid size will be built offline (Tpre. The power source vector g of different grid sizes are also built offline. Then, for the FDM, the conductance atrix Ghet will be built using a sparse atrix representation in MATLAB (TG. For the VPS ethod, the (I+G R in (20 will be built too in sparse atrix representation (Tvia. Note that the hoogeneous conductance atrix Gho is not required to be represented explicitly and hence will not be built. This results in the eory usage savings of the VPS ethod. Next, in the solution phase, the FDM will solve the conductance equation for thet G\g using the left atrix division (MLDIVIDE MATLAB coand (TC. Total coputation tie (Tt and eory consuption [Me (MB] are also illustrated for all ethods. On the other hand, the VPS ethod will execute three steps outlined in the last section. To be fair, the execution tie coparison will include both the conductance atrix building phase as well as the solution phase. The eory usage of the VPS ethod will also include coputation of the data table. Tables I and II enuerate speed and eory consuption coparison between an our FDM theral siulator against the VPS hybrid ethod. In tables, the nuber of power sources equal to the nuber of esh grids. Different fro the FDM, coplexity of the VPS algorith also depends on the nuber of esh grids occupied by TSVs. Hence, two different nuber of TSVs (20, 100, and 400 are used in the siulation. All siulations of Table II odeled Fig. 2, where TSVs are placed in adhesive layers. Different fro Fig. 2, there can be ultiple nuber of adhesive layers and TSVs can be placed in different adhesive layers. We assue that the nuber of grid cells for each TSV is constant. The coputation tie to build (I + G R depends on the total nuber of TSVs. Coputation tie of the teperature ap also increases as the nuber of adhesive layers increases but its coplexity increent is rather oderate than the coplexity increase by the nuber of TSVs. If TSVs are placed fro the top to the botto, DCT lookup table and teperature ap need to be built for all layers. According to Table II, the hybrid ethod deonstrated outstanding perforance advantage over the FDM. Overall speedup of the hybrid ethod over the FDM is around 100. V. Conclusion A novel theral analysis algorith was proposed that extended the applicability of the analytical Green functionbased spectral ethod to handle substrates containing theral vias with heterogeneous theral conductance. Experients indicated that the proposed hybrid VPS ethod yielded accurate theral aps that are coparable to a coercial FDMbased theral siulator while consuing considerable less coputing tie. References [1] D. Oh, C. C.-P. Chen, and Y. H. Hu, 3DFFT: Theral analysis of non-hoogeneous IC using 3D FFT Green function ethod, in Proc. ISQED, 2007, pp [2] E. Wong and S. K. Li, Whitespace redistribution for theral via insertion in 3D stacked ICs, in Proc. ICCD, 2007, pp [3] G. Singh and C. S. Tan, Theral itigation using theral through silicon via (TTSV in 3-D ICs, in Proc. IMPACT, Oct. 2009, pp [4] B. Goplen and S. S. Sapatnekar, Placeent of theral vias in 3D ICs using various theral objectives, IEEE Trans. Coput.-Aided Des., vol. 25, no. 4, pp , Apr [5] H. Yu, Y. Shi, L. He, and T. Karnik, Theral via allocation for 3D ICs considering teporally and spatially variant theral power, in Proc. ISLPED, 2006, pp [6] Y. Zhan and S. S. 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