In 1980, the yield = 48% and the Die Area = 0.16 from figure In 1992, the yield = 48% and the Die Area = 0.97 from figure 1.31.

Size: px
Start display at page:

Download "In 1980, the yield = 48% and the Die Area = 0.16 from figure In 1992, the yield = 48% and the Die Area = 0.97 from figure 1.31."

Transcription

1 CS152 Homework 1 Solutions Spring Yield = 1 / ((1 + (Defects per area * Die Area / 2))^2) Thus, if die area increases, defects per area must decrease Solving the yield equation for Defects per area, we get: Defects per area = (1 / (sqrt(yield) 1) * (2 / Die Area) 1.53 In 1980, the yield = 48% and the Die Area = 0.16 from figure In 1992, the yield = 48% and the Die Area = 0.97 from figure Thus, Defects per area in 1980 = (1 / (sqrt(0.48) 1) * (2 /.16) = 5.5 / unit area (in sq. cm) Defects per area in 1992 = (1 / (sqrt(0.48) 1) * (2 /.97) =.914 / unit area (in sq. cm) Improvement = 5.5 /.914 = 601.7% improvement. 2.3 If you get confused in these questions, just remember to do unit analysis. CPI M1 = 10 seconds * (200e6 cycles / sec) * (1 / 200e6 instructions) = 10 cycles per instruction CPI M2 = 5 seconds * (300e6 cycles / sec) * (1 / 160e6 instructions) = cycles per instruction 2.15 MIPS = Instruction Count / (Execution time * 10^6) Since Execution Time = Instruction Count * CPI * (1 / Clock Cycle) MIPS = Clock Cycle / (CPI * 10^6) First we need to find CPI of each machine.

2 CPI MFP =.1 * * * * 2 = 3.6 CPI MNFP =.1 * * * *2 = 18.4 Note that for CPI MNFP, we used 60, 40, and 100 rather than 30, 20, and 50. This is because it takes 30 integer instructions for a FP multiply, and each of those 30 integer instructions takes 2 clock cycles. Thus 30 * 2 = 60. This holds for FP add and divide as well. MIPS MFP = 1000e6 / (3.6 * 10^6) = MIPS MNFP = 1000e6(18.4*10^6) = Since 10% of the instructions are FP mults, we know that there are.1 * 300e6 number of floating point multiply instructions. We can similarily find the number of FP add, FP divide, and integer instructions. = (.1 * 300e6 * 30) + (.15 * 300e6 * 20) + (.05 * 300e6 * 40) + (.7 * 300e6) = 2.76e CPI a = (2 *.4) + (3 *.25) + (3 *.25) + (5 *.1) = 2.8 CPI CPI b = (2 *.4) + (2 *.25) + (3 *.25) + (4 *.1) = 2.45 CPI Note that CPI does not include clock cycles at all!! 2.24 Only calculated for the hardware improvement (2.18); Performance of Mbase = 500e6 / (2.8 * 10^6) = 178 MIPS Performance of Mopt = 600e6 / (2.45 * 10^6) = 245 MIPS This is a performance gain of 245 / 178 = 1.37, or 37% improvement in 6 months. In the 6 months necessary to optimize, CPI performance will increase by ^ 6 = 1.22, or 22%. Since the performance gain is more than the normal growth rate of performance, the optimizations should be done Performance = Inst Count * CPI * Cycle Time

3 In this case, Inst count is the same for both, so we can drop it. (Assume 1 instruction or 100 or any number so long as it s the same, since it ll cancel out anyway). It is easier to pick an arbitrary value for Clock Cycle. The easiest number would be 1 Hz, so the cycle time = 1. Performance(old) = (.1 * *4) * 1 = 4.8 seconds Performance(new) = (.1 * * 4) * 1.2 = 5.04 seconds Since performance is worse, we should not proceed with the modification Execution time after improvement = ( 5 sec / 5) + 5 sec = 6 sec. Speedup = 10 sec / 6 sec = Multiplication: (20 sec / 4) + 80 = 85 sec, Speedup = 100 sec / 85 sec = 1.18 Memory Access: (50 sec / 2) + 50 = 75 sec, Speedup = 100 sec / 75 sec= 1.33 Both: (20 sec / 4) + (50 sec / 2) + 30 = 60 sec, Speedup = 100 sec / 60 sec = 1.67 B.15 The even parity function will output a 1 whenever there are an even numbers of 1 in the input, and 0 otherwise. A B C D Out

4 B.21 Note that the machine simply changes state every clock cycle. Mid1State Middle =1 LeftState Left = 1 Middle =0 RightState Middle =0 Right = 1 Mid2State Middle =1 B.22 First, we do state assignments: LeftState = 00 Mid1State = 01 RightState = 11 Mid2State = 10 Note that we picked RightState to be 11. This makes it so that each transition only involves one of the 2 state bits to change. This will make our logic simpler later. If you picked 10 for RightState and 11 for Mid2State, your logic equations may be more complex (and require more gates). CS1 CS0 NS1 NS Solving for NS1 and NS0, we get as our next state equations: NS1 = CS0, and NS0 = ~CS1.

5 Our output table looks like this: CS1 CS0 Left Middle Right Thus (by inspection), Left = ~CS1 ~CS0 Middle = CS1 CS0 Right = CS1 CS0

Goals for Performance Lecture

Goals for Performance Lecture Goals for Performance Lecture Understand performance, speedup, throughput, latency Relationship between cycle time, cycles/instruction (CPI), number of instructions (the performance equation) Amdahl s

More information

Lecture 3, Performance

Lecture 3, Performance Repeating some definitions: Lecture 3, Performance CPI MHz MIPS MOPS Clocks Per Instruction megahertz, millions of cycles per second Millions of Instructions Per Second = MHz / CPI Millions of Operations

More information

Lecture 3, Performance

Lecture 3, Performance Lecture 3, Performance Repeating some definitions: CPI Clocks Per Instruction MHz megahertz, millions of cycles per second MIPS Millions of Instructions Per Second = MHz / CPI MOPS Millions of Operations

More information

PERFORMANCE METRICS. Mahdi Nazm Bojnordi. CS/ECE 6810: Computer Architecture. Assistant Professor School of Computing University of Utah

PERFORMANCE METRICS. Mahdi Nazm Bojnordi. CS/ECE 6810: Computer Architecture. Assistant Professor School of Computing University of Utah PERFORMANCE METRICS Mahdi Nazm Bojnordi Assistant Professor School of Computing University of Utah CS/ECE 6810: Computer Architecture Overview Announcement Jan. 17 th : Homework 1 release (due on Jan.

More information

TEST 1 REVIEW. Lectures 1-5

TEST 1 REVIEW. Lectures 1-5 TEST 1 REVIEW Lectures 1-5 REVIEW Test 1 will cover lectures 1-5. There are 10 questions in total with the last being a bonus question. The questions take the form of short answers (where you are expected

More information

2x 1 7. A linear congruence in modular arithmetic is an equation of the form. Why is the solution a set of integers rather than a unique integer?

2x 1 7. A linear congruence in modular arithmetic is an equation of the form. Why is the solution a set of integers rather than a unique integer? Chapter 3: Theory of Modular Arithmetic 25 SECTION C Solving Linear Congruences By the end of this section you will be able to solve congruence equations determine the number of solutions find the multiplicative

More information

INF2270 Spring Philipp Häfliger. Lecture 8: Superscalar CPUs, Course Summary/Repetition (1/2)

INF2270 Spring Philipp Häfliger. Lecture 8: Superscalar CPUs, Course Summary/Repetition (1/2) INF2270 Spring 2010 Philipp Häfliger Summary/Repetition (1/2) content From Scalar to Superscalar Lecture Summary and Brief Repetition Binary numbers Boolean Algebra Combinational Logic Circuits Encoder/Decoder

More information

2x 1 7. A linear congruence in modular arithmetic is an equation of the form. Why is the solution a set of integers rather than a unique integer?

2x 1 7. A linear congruence in modular arithmetic is an equation of the form. Why is the solution a set of integers rather than a unique integer? Chapter 3: Theory of Modular Arithmetic 25 SECTION C Solving Linear Congruences By the end of this section you will be able to solve congruence equations determine the number of solutions find the multiplicative

More information

CS 700: Quantitative Methods & Experimental Design in Computer Science

CS 700: Quantitative Methods & Experimental Design in Computer Science CS 700: Quantitative Methods & Experimental Design in Computer Science Sanjeev Setia Dept of Computer Science George Mason University Logistics Grade: 35% project, 25% Homework assignments 20% midterm,

More information

3.5 Solving Equations Involving Integers II

3.5 Solving Equations Involving Integers II 208 CHAPTER 3. THE FUNDAMENTALS OF ALGEBRA 3.5 Solving Equations Involving Integers II We return to solving equations involving integers, only this time the equations will be a bit more advanced, requiring

More information

Lecture 2: Metrics to Evaluate Systems

Lecture 2: Metrics to Evaluate Systems Lecture 2: Metrics to Evaluate Systems Topics: Metrics: power, reliability, cost, benchmark suites, performance equation, summarizing performance with AM, GM, HM Sign up for the class mailing list! Video

More information

Amdahl's Law. Execution time new = ((1 f) + f/s) Execution time. S. Then:

Amdahl's Law. Execution time new = ((1 f) + f/s) Execution time. S. Then: Amdahl's Law Useful for evaluating the impact of a change. (A general observation.) Insight: Improving a feature cannot improve performance beyond the use of the feature Suppose we introduce a particular

More information

CMP 334: Seventh Class

CMP 334: Seventh Class CMP 334: Seventh Class Performance HW 5 solution Averages and weighted averages (review) Amdahl's law Ripple-carry adder circuits Binary addition Half-adder circuits Full-adder circuits Subtraction, negative

More information

MA 1128: Lecture 08 03/02/2018. Linear Equations from Graphs And Linear Inequalities

MA 1128: Lecture 08 03/02/2018. Linear Equations from Graphs And Linear Inequalities MA 1128: Lecture 08 03/02/2018 Linear Equations from Graphs And Linear Inequalities Linear Equations from Graphs Given a line, we would like to be able to come up with an equation for it. I ll go over

More information

EECS150 - Digital Design Lecture 11 - Shifters & Counters. Register Summary

EECS150 - Digital Design Lecture 11 - Shifters & Counters. Register Summary EECS50 - Digital Design Lecture - Shifters & Counters February 24, 2003 John Wawrzynek Spring 2005 EECS50 - Lec-counters Page Register Summary All registers (this semester) based on Flip-flops: q 3 q 2

More information

Performance Metrics for Computer Systems. CASS 2018 Lavanya Ramapantulu

Performance Metrics for Computer Systems. CASS 2018 Lavanya Ramapantulu Performance Metrics for Computer Systems CASS 2018 Lavanya Ramapantulu Eight Great Ideas in Computer Architecture Design for Moore s Law Use abstraction to simplify design Make the common case fast Performance

More information

EECS Components and Design Techniques for Digital Systems. FSMs 9/11/2007

EECS Components and Design Techniques for Digital Systems. FSMs 9/11/2007 EECS 150 - Components and Design Techniques for Digital Systems FSMs 9/11/2007 Sarah Bird Electrical Engineering and Computer Sciences University of California, Berkeley Slides borrowed from David Culler

More information

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1>

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1> Chapter 5 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 5 Chapter 5 :: Topics Introduction Arithmetic Circuits umber Systems Sequential Building

More information

ICS 233 Computer Architecture & Assembly Language

ICS 233 Computer Architecture & Assembly Language ICS 233 Computer Architecture & Assembly Language Assignment 6 Solution 1. Identify all of the RAW data dependencies in the following code. Which dependencies are data hazards that will be resolved by

More information

The Design Procedure. Output Equation Determination - Derive output equations from the state table

The Design Procedure. Output Equation Determination - Derive output equations from the state table The Design Procedure Specification Formulation - Obtain a state diagram or state table State Assignment - Assign binary codes to the states Flip-Flop Input Equation Determination - Select flipflop types

More information

Section 7.4: Inverse Laplace Transform

Section 7.4: Inverse Laplace Transform Section 74: Inverse Laplace Transform A natural question to ask about any function is whether it has an inverse function We now ask this question about the Laplace transform: given a function F (s), will

More information

Measurement & Performance

Measurement & Performance Measurement & Performance Timers Performance measures Time-based metrics Rate-based metrics Benchmarking Amdahl s law Topics 2 Page The Nature of Time real (i.e. wall clock) time = User Time: time spent

More information

Measurement & Performance

Measurement & Performance Measurement & Performance Topics Timers Performance measures Time-based metrics Rate-based metrics Benchmarking Amdahl s law 2 The Nature of Time real (i.e. wall clock) time = User Time: time spent executing

More information

Binary addition example worked out

Binary addition example worked out Binary addition example worked out Some terms are given here Exercise: what are these numbers equivalent to in decimal? The initial carry in is implicitly 0 1 1 1 0 (Carries) 1 0 1 1 (Augend) + 1 1 1 0

More information

Counters. We ll look at different kinds of counters and discuss how to build them

Counters. We ll look at different kinds of counters and discuss how to build them Counters We ll look at different kinds of counters and discuss how to build them These are not only examples of sequential analysis and design, but also real devices used in larger circuits 1 Introducing

More information

COVER SHEET: Problem#: Points

COVER SHEET: Problem#: Points EEL 4712 Midterm 3 Spring 2017 VERSION 1 Name: UFID: Sign here to give permission for your test to be returned in class, where others might see your score: IMPORTANT: Please be neat and write (or draw)

More information

Discrete Mathematics for CS Spring 2005 Clancy/Wagner Notes 25. Minesweeper. Optimal play in Minesweeper

Discrete Mathematics for CS Spring 2005 Clancy/Wagner Notes 25. Minesweeper. Optimal play in Minesweeper CS 70 Discrete Mathematics for CS Spring 2005 Clancy/Wagner Notes 25 Minesweeper Our final application of probability is to Minesweeper. We begin by discussing how to play the game optimally; this is probably

More information

EECS150 - Digital Design Lecture 23 - FSMs & Counters

EECS150 - Digital Design Lecture 23 - FSMs & Counters EECS150 - Digital Design Lecture 23 - FSMs & Counters April 8, 2010 John Wawrzynek Spring 2010 EECS150 - Lec22-counters Page 1 One-hot encoding of states. One FF per state. State Encoding Why one-hot encoding?

More information

Unit 8A Computer Organization. Boolean Logic and Gates

Unit 8A Computer Organization. Boolean Logic and Gates Unit 8A Computer Organization Boolean Logic and Gates Announcements Bring ear buds or headphones to lab! 15110 Principles of Computing, Carnegie Mellon University - CORTINA 2 Representing and Manipulating

More information

Logic and Computer Design Fundamentals. Chapter 8 Sequencing and Control

Logic and Computer Design Fundamentals. Chapter 8 Sequencing and Control Logic and Computer Design Fundamentals Chapter 8 Sequencing and Control Datapath and Control Datapath - performs data transfer and processing operations Control Unit - Determines enabling and sequencing

More information

Definition: A "system" of equations is a set or collection of equations that you deal with all together at once.

Definition: A system of equations is a set or collection of equations that you deal with all together at once. System of Equations Definition: A "system" of equations is a set or collection of equations that you deal with all together at once. There is both an x and y value that needs to be solved for Systems

More information

Design at the Register Transfer Level

Design at the Register Transfer Level Week-7 Design at the Register Transfer Level Algorithmic State Machines Algorithmic State Machine (ASM) q Our design methodologies do not scale well to real-world problems. q 232 - Logic Design / Algorithmic

More information

Performance of Computers. Performance of Computers. Defining Performance. Forecast

Performance of Computers. Performance of Computers. Defining Performance. Forecast Performance of Computers Which computer is fastest? Not so simple scientific simulation - FP performance program development - Integer performance commercial work - I/O Performance of Computers Want to

More information

Let s now begin to formalize our analysis of sequential machines Powerful methods for designing machines for System control Pattern recognition Etc.

Let s now begin to formalize our analysis of sequential machines Powerful methods for designing machines for System control Pattern recognition Etc. Finite State Machines Introduction Let s now begin to formalize our analysis of sequential machines Powerful methods for designing machines for System control Pattern recognition Etc. Such devices form

More information

Performance, Power & Energy. ELEC8106/ELEC6102 Spring 2010 Hayden Kwok-Hay So

Performance, Power & Energy. ELEC8106/ELEC6102 Spring 2010 Hayden Kwok-Hay So Performance, Power & Energy ELEC8106/ELEC6102 Spring 2010 Hayden Kwok-Hay So Recall: Goal of this class Performance Reconfiguration Power/ Energy H. So, Sp10 Lecture 3 - ELEC8106/6102 2 PERFORMANCE EVALUATION

More information

Intro To Digital Logic

Intro To Digital Logic Intro To Digital Logic 1 Announcements... Project 2.2 out But delayed till after the midterm Midterm in a week Covers up to last lecture + next week's homework & lab Nick goes "H-Bomb of Justice" About

More information

Lesson 3-2: Solving Linear Systems Algebraically

Lesson 3-2: Solving Linear Systems Algebraically Yesterday we took our first look at solving a linear system. We learned that a linear system is two or more linear equations taken at the same time. Their solution is the point that all the lines have

More information

CMP 338: Third Class

CMP 338: Third Class CMP 338: Third Class HW 2 solution Conversion between bases The TINY processor Abstraction and separation of concerns Circuit design big picture Moore s law and chip fabrication cost Performance What does

More information

Department of Electrical and Computer Engineering University of Wisconsin Madison. Fall Final Examination

Department of Electrical and Computer Engineering University of Wisconsin Madison. Fall Final Examination Department of Electrical and Computer Engineering University of Wisconsin Madison ECE 553: Testing and Testable Design of Digital Systems Fall 2013-2014 Final Examination CLOSED BOOK Kewal K. Saluja Date:

More information

EECS150 - Digital Design Lecture 21 - Design Blocks

EECS150 - Digital Design Lecture 21 - Design Blocks EECS150 - Digital Design Lecture 21 - Design Blocks April 3, 2012 John Wawrzynek Spring 2012 EECS150 - Lec21-db3 Page 1 Fixed Shifters / Rotators fixed shifters hardwire the shift amount into the circuit.

More information

5 + 9(10) + 3(100) + 0(1000) + 2(10000) =

5 + 9(10) + 3(100) + 0(1000) + 2(10000) = Chapter 5 Analyzing Algorithms So far we have been proving statements about databases, mathematics and arithmetic, or sequences of numbers. Though these types of statements are common in computer science,

More information

Q: Examine the relationship between X and the Next state. How would you describe this circuit? A: An inverter which is synched with a clock signal.

Q: Examine the relationship between X and the Next state. How would you describe this circuit? A: An inverter which is synched with a clock signal. /2/2 OF 7 Next, let s reverse engineer a T-Flip flop Prob. (Pg 529) Note that whenever T is equal to, there is a state change, otherwise, there isn t. In this circuit, (x) determines whether the output

More information

Sequences & Functions

Sequences & Functions Ch. 5 Sec. 1 Sequences & Functions Skip Counting to Arithmetic Sequences When you skipped counted as a child, you were introduced to arithmetic sequences. Example 1: 2, 4, 6, 8, adding 2 Example 2: 10,

More information

EECS150 - Digital Design Lecture 25 Shifters and Counters. Recap

EECS150 - Digital Design Lecture 25 Shifters and Counters. Recap EECS150 - Digital Design Lecture 25 Shifters and Counters Nov. 21, 2013 Prof. Ronald Fearing Electrical Engineering and Computer Sciences University of California, Berkeley (slides courtesy of Prof. John

More information

Mathematical Induction

Mathematical Induction Mathematical Induction MAT231 Transition to Higher Mathematics Fall 2014 MAT231 (Transition to Higher Math) Mathematical Induction Fall 2014 1 / 21 Outline 1 Mathematical Induction 2 Strong Mathematical

More information

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department Page 1 of 13 COE 202: Digital Logic Design (3-0-3) Term 112 (Spring 2012) Final

More information

Performance Metrics & Architectural Adaptivity. ELEC8106/ELEC6102 Spring 2010 Hayden Kwok-Hay So

Performance Metrics & Architectural Adaptivity. ELEC8106/ELEC6102 Spring 2010 Hayden Kwok-Hay So Performance Metrics & Architectural Adaptivity ELEC8106/ELEC6102 Spring 2010 Hayden Kwok-Hay So What are the Options? Power Consumption Activity factor (amount of circuit switching) Load Capacitance (size

More information

3. (2) What is the difference between fixed and hybrid instructions?

3. (2) What is the difference between fixed and hybrid instructions? 1. (2 pts) What is a "balanced" pipeline? 2. (2 pts) What are the two main ways to define performance? 3. (2) What is the difference between fixed and hybrid instructions? 4. (2 pts) Clock rates have grown

More information

Digital Electronics II Mike Brookes Please pick up: Notes from the front desk

Digital Electronics II Mike Brookes Please pick up: Notes from the front desk NOTATION.PPT(10/8/2010) 1.1 Digital Electronics II Mike Brookes Please pick up: Notes from the front desk 1. What does Digital mean? 2. Where is it used? 3. Why is it used? 4. What are the important features

More information

Digital Circuit Engineering

Digital Circuit Engineering Digital Circuit Engineering 2nd Distributive ( A)( B) = AB Circuits that work in a sequence of steps Absorption A = A A= THESE CICUITS NEED STOAGE TO EMEMBE WHEE THEY AE STOAGE D MU G M MU G S CLK D Flip

More information

Parity Checker Example. EECS150 - Digital Design Lecture 9 - Finite State Machines 1. Formal Design Process. Formal Design Process

Parity Checker Example. EECS150 - Digital Design Lecture 9 - Finite State Machines 1. Formal Design Process. Formal Design Process Parity Checker Example A string of bits has even parity if the number of 1 s in the string is even. Design a circuit that accepts a bit-serial stream of bits and outputs a 0 if the parity thus far is even

More information

From Sequential Circuits to Real Computers

From Sequential Circuits to Real Computers 1 / 36 From Sequential Circuits to Real Computers Lecturer: Guillaume Beslon Original Author: Lionel Morel Computer Science and Information Technologies - INSA Lyon Fall 2017 2 / 36 Introduction What we

More information

EXPERIMENT Traffic Light Controller

EXPERIMENT Traffic Light Controller 11.1 Objectives EXPERIMENT 11 11. Traffic Light Controller Practice on the design of clocked sequential circuits. Applications of sequential circuits. 11.2 Overview In this lab you are going to develop

More information

Cost/Performance Tradeoff of n-select Square Root Implementations

Cost/Performance Tradeoff of n-select Square Root Implementations Australian Computer Science Communications, Vol.22, No.4, 2, pp.9 6, IEEE Comp. Society Press Cost/Performance Tradeoff of n-select Square Root Implementations Wanming Chu and Yamin Li Computer Architecture

More information

19. Fixed costs and variable bounds

19. Fixed costs and variable bounds CS/ECE/ISyE 524 Introduction to Optimization Spring 2017 18 19. Fixed costs and variable bounds ˆ Fixed cost example ˆ Logic and the Big M Method ˆ Example: facility location ˆ Variable lower bounds Laurent

More information

Memory Elements I. CS31 Pascal Van Hentenryck. CS031 Lecture 6 Page 1

Memory Elements I. CS31 Pascal Van Hentenryck. CS031 Lecture 6 Page 1 Memory Elements I CS31 Pascal Van Hentenryck CS031 Lecture 6 Page 1 Memory Elements (I) Combinational devices are good for computing Boolean functions pocket calculator Computers also need to remember

More information

Homework Assignment #1 Solutions EE 477 Spring 2017 Professor Parker

Homework Assignment #1 Solutions EE 477 Spring 2017 Professor Parker Homework Assignment #1 Solutions EE 477 Spring 2017 Professor Parker Note: + implies OR,. implies AND, ~ implies NOT Question 1: a) (4%) Use transmission gates to design a 3-input OR gate Note: There are

More information

Math 154 :: Elementary Algebra

Math 154 :: Elementary Algebra Math 4 :: Elementary Algebra Section. Additive Property of Equality Section. Multiplicative Property of Equality Section.3 Linear Equations in One-Variable Section.4 Linear Equations in One-Variable with

More information

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering TIMING ANALYSIS Overview Circuits do not respond instantaneously to input changes

More information

Shift Register Counters

Shift Register Counters Shift Register Counters Shift register counter: a shift register with the serial output connected back to the serial input. They are classified as counters because they give a specified sequence of states.

More information

CS264: Beyond Worst-Case Analysis Lecture #11: LP Decoding

CS264: Beyond Worst-Case Analysis Lecture #11: LP Decoding CS264: Beyond Worst-Case Analysis Lecture #11: LP Decoding Tim Roughgarden October 29, 2014 1 Preamble This lecture covers our final subtopic within the exact and approximate recovery part of the course.

More information

Logic and Computer Design Fundamentals. Chapter 5 Arithmetic Functions and Circuits

Logic and Computer Design Fundamentals. Chapter 5 Arithmetic Functions and Circuits Logic and Computer Design Fundamentals Chapter 5 Arithmetic Functions and Circuits Arithmetic functions Operate on binary vectors Use the same subfunction in each bit position Can design functional block

More information

XOR - XNOR Gates. The graphic symbol and truth table of XOR gate is shown in the figure.

XOR - XNOR Gates. The graphic symbol and truth table of XOR gate is shown in the figure. XOR - XNOR Gates Lesson Objectives: In addition to AND, OR, NOT, NAND and NOR gates, exclusive-or (XOR) and exclusive-nor (XNOR) gates are also used in the design of digital circuits. These have special

More information

Analysis of Algorithms [Reading: CLRS 2.2, 3] Laura Toma, csci2200, Bowdoin College

Analysis of Algorithms [Reading: CLRS 2.2, 3] Laura Toma, csci2200, Bowdoin College Analysis of Algorithms [Reading: CLRS 2.2, 3] Laura Toma, csci2200, Bowdoin College Why analysis? We want to predict how the algorithm will behave (e.g. running time) on arbitrary inputs, and how it will

More information

HOMEWORK 4 SOLUTIONS TO SELECTED PROBLEMS

HOMEWORK 4 SOLUTIONS TO SELECTED PROBLEMS HOMEWORK 4 SOLUTIONS TO SELECTED PROBLEMS 1. Chapter 3, Problem 18 (Graded) Let H and K be subgroups of G. Then e, the identity, must be in H and K, so it must be in H K. Thus, H K is nonempty, so we can

More information

Summarizing Measured Data

Summarizing Measured Data Summarizing Measured Data 12-1 Overview Basic Probability and Statistics Concepts: CDF, PDF, PMF, Mean, Variance, CoV, Normal Distribution Summarizing Data by a Single Number: Mean, Median, and Mode, Arithmetic,

More information

ECE/CS 250 Computer Architecture

ECE/CS 250 Computer Architecture ECE/CS 250 Computer Architecture Basics of Logic Design: Boolean Algebra, Logic Gates (Combinational Logic) Tyler Bletsch Duke University Slides are derived from work by Daniel J. Sorin (Duke), Alvy Lebeck

More information

CS264: Beyond Worst-Case Analysis Lecture #15: Smoothed Complexity and Pseudopolynomial-Time Algorithms

CS264: Beyond Worst-Case Analysis Lecture #15: Smoothed Complexity and Pseudopolynomial-Time Algorithms CS264: Beyond Worst-Case Analysis Lecture #15: Smoothed Complexity and Pseudopolynomial-Time Algorithms Tim Roughgarden November 5, 2014 1 Preamble Previous lectures on smoothed analysis sought a better

More information

Lecture: Pipelining Basics

Lecture: Pipelining Basics Lecture: Pipelining Basics Topics: Performance equations wrap-up, Basic pipelining implementation Video 1: What is pipelining? Video 2: Clocks and latches Video 3: An example 5-stage pipeline Video 4:

More information

EECS150 - Digital Design Lecture 27 - misc2

EECS150 - Digital Design Lecture 27 - misc2 EECS150 - Digital Design Lecture 27 - misc2 May 1, 2002 John Wawrzynek Spring 2002 EECS150 - Lec27-misc2 Page 1 Outline Linear Feedback Shift Registers Theory and practice Simple hardware division algorithms

More information

Discrete Mathematics for CS Spring 2006 Vazirani Lecture 22

Discrete Mathematics for CS Spring 2006 Vazirani Lecture 22 CS 70 Discrete Mathematics for CS Spring 2006 Vazirani Lecture 22 Random Variables and Expectation Question: The homeworks of 20 students are collected in, randomly shuffled and returned to the students.

More information

Adders, subtractors comparators, multipliers and other ALU elements

Adders, subtractors comparators, multipliers and other ALU elements CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Instructor: Mohsen Imani UC San Diego Slides from: Prof.Tajana Simunic Rosing

More information

SNAP Centre Workshop. Solving Systems of Equations

SNAP Centre Workshop. Solving Systems of Equations SNAP Centre Workshop Solving Systems of Equations 35 Introduction When presented with an equation containing one variable, finding a solution is usually done using basic algebraic manipulation. Example

More information

Digital Circuits, Binary Numbering, and Logic Gates Cornerstone Electronics Technology and Robotics II

Digital Circuits, Binary Numbering, and Logic Gates Cornerstone Electronics Technology and Robotics II Digital Circuits, Binary Numbering, and Logic Gates Cornerstone Electronics Technology and Robotics II Administration: o Prayer Electricity and Electronics, Section 20.1, Digital Fundamentals: o Fundamentals:

More information

Computing via boolean logic. COS 116: 3/8/2011 Sanjeev Arora

Computing via boolean logic. COS 116: 3/8/2011 Sanjeev Arora Computing via boolean logic. COS 116: 3/8/2011 Sanjeev Arora Recap: Boolean Logic Example Ed goes to the party if Dan does not and Stella does. Choose Boolean variables for 3 events: { Each E: Ed goes

More information

Lecture 13: Sequential Circuits, FSM

Lecture 13: Sequential Circuits, FSM Lecture 13: Sequential Circuits, FSM Today s topics: Sequential circuits Finite state machines Reminder: midterm on Tue 2/28 will cover Chapters 1-3, App A, B if you understand all slides, assignments,

More information

Digital Integrated Circuits A Design Perspective. Arithmetic Circuits. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.

Digital Integrated Circuits A Design Perspective. Arithmetic Circuits. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Arithmetic Circuits January, 2003 1 A Generic Digital Processor MEMORY INPUT-OUTPUT CONTROL DATAPATH

More information

ECE20B Final Exam, 200 Point Exam Closed Book, Closed Notes, Calculators Not Allowed June 12th, Name

ECE20B Final Exam, 200 Point Exam Closed Book, Closed Notes, Calculators Not Allowed June 12th, Name C20B Final xam, 200 Point xam Closed Book, Closed Notes, Calculators Not llowed June 2th, 2003 Name Guidelines: Please remember to write your name on your bluebook, and when finished, to staple your solutions

More information

UNIT 8A Computer Circuitry: Layers of Abstraction. Boolean Logic & Truth Tables

UNIT 8A Computer Circuitry: Layers of Abstraction. Boolean Logic & Truth Tables UNIT 8 Computer Circuitry: Layers of bstraction 1 oolean Logic & Truth Tables Computer circuitry works based on oolean logic: operations on true (1) and false (0) values. ( ND ) (Ruby: && ) 0 0 0 0 0 1

More information

15.1 Elimination of Redundant States

15.1 Elimination of Redundant States 15.1 Elimination of Redundant States In Ch. 14 we tried not to have unnecessary states What if we have extra states in the state graph/table? Complete the table then eliminate the redundant states Chapter

More information

Arithmetic and Logic Unit First Part

Arithmetic and Logic Unit First Part Arithmetic and Logic Unit First Part Arquitectura de Computadoras Arturo Díaz D PérezP Centro de Investigación n y de Estudios Avanzados del IPN adiaz@cinvestav.mx Arquitectura de Computadoras ALU1-1 Typical

More information

Week-5. Sequential Circuit Design. Acknowledgement: Most of the following slides are adapted from Prof. Kale's slides at UIUC, USA.

Week-5. Sequential Circuit Design. Acknowledgement: Most of the following slides are adapted from Prof. Kale's slides at UIUC, USA. Week-5 Sequential Circuit Design Acknowledgement: Most of the following slides are adapted from Prof. Kale's slides at UIUC, USA. Storing a value: SR = 00 What if S = 0 and R = 0? The equations on the

More information

CS 154, Lecture 3: DFA NFA, Regular Expressions

CS 154, Lecture 3: DFA NFA, Regular Expressions CS 154, Lecture 3: DFA NFA, Regular Expressions Homework 1 is coming out Deterministic Finite Automata Computation with finite memory Non-Deterministic Finite Automata Computation with finite memory and

More information

Partial Fractions. June 27, In this section, we will learn to integrate another class of functions: the rational functions.

Partial Fractions. June 27, In this section, we will learn to integrate another class of functions: the rational functions. Partial Fractions June 7, 04 In this section, we will learn to integrate another class of functions: the rational functions. Definition. A rational function is a fraction of two polynomials. For example,

More information

ELE2120 Digital Circuits and Systems. Tutorial Note 10

ELE2120 Digital Circuits and Systems. Tutorial Note 10 ELE2120 Digital Circuits and Systems Tutorial Note 10 Outline 1. 1. Sequential Circuit Design 2. 2. Design procedure: a complete example illustration Sequential circuit analysis & design In sequential

More information

CS/COE1541: Introduction to Computer Architecture. Logic Design Review. Sangyeun Cho. Computer Science Department University of Pittsburgh

CS/COE1541: Introduction to Computer Architecture. Logic Design Review. Sangyeun Cho. Computer Science Department University of Pittsburgh CS/COE54: Introduction to Computer Architecture Logic Design Review Sangyeun Cho Computer Science Department Logic design? Digital hardware is implemented by way of logic design Digital circuits process

More information

Chapter 7: Trigonometric Equations and Identities

Chapter 7: Trigonometric Equations and Identities Chapter 7: Trigonometric Equations and Identities In the last two chapters we have used basic definitions and relationships to simplify trigonometric expressions and equations. In this chapter we will

More information

Chapter 2. Mathematical Reasoning. 2.1 Mathematical Models

Chapter 2. Mathematical Reasoning. 2.1 Mathematical Models Contents Mathematical Reasoning 3.1 Mathematical Models........................... 3. Mathematical Proof............................ 4..1 Structure of Proofs........................ 4.. Direct Method..........................

More information

Chapter 7: Trigonometric Equations and Identities

Chapter 7: Trigonometric Equations and Identities Chapter 7: Trigonometric Equations and Identities In the last two chapters we have used basic definitions and relationships to simplify trigonometric expressions and equations. In this chapter we will

More information

CpE358/CS381. Switching Theory and Logical Design. Summer

CpE358/CS381. Switching Theory and Logical Design. Summer Switching Theory and Logical Design - Class Schedule Monday Tuesday Wednesday Thursday Friday May 7 8 9 - Class 2 - Class 2 2 24 - Class 3 25 26 - Class 4 27 28 Quiz Commencement 3 June 2 - Class 5 3 -

More information

Modern Computer Architecture

Modern Computer Architecture Modern Computer Architecture Lecture1 Fundamentals of Quantitative Design and Analysis (II) Hongbin Sun 国家集成电路人才培养基地 Xi an Jiaotong University 1.4 Trends in Technology Logic: transistor density 35%/year,

More information

Digital Circuit Engineering

Digital Circuit Engineering Digital Circuit Engineering 2nd Distributive ( + A)( + B) = + AB Circuits that work in a sequence of steps Absorption + A = + A A+= THESE CICUITS NEED STOAGE TO EMEMBE WHEE THEY AE STOAGE D MU G M MU S

More information

A Simple Architectural Enhancement for Fast and Flexible Elliptic Curve Cryptography over Binary Finite Fields GF(2 m )

A Simple Architectural Enhancement for Fast and Flexible Elliptic Curve Cryptography over Binary Finite Fields GF(2 m ) A Simple Architectural Enhancement for Fast and Flexible Elliptic Curve Cryptography over Binary Finite Fields GF(2 m ) Stefan Tillich, Johann Großschädl Institute for Applied Information Processing and

More information

5.2 Polynomial Operations

5.2 Polynomial Operations 5.2 Polynomial Operations At times we ll need to perform operations with polynomials. At this level we ll just be adding, subtracting, or multiplying polynomials. Dividing polynomials will happen in future

More information

EECS150 - Digital Design Lecture 23 - FFs revisited, FIFOs, ECCs, LSFRs. Cross-coupled NOR gates

EECS150 - Digital Design Lecture 23 - FFs revisited, FIFOs, ECCs, LSFRs. Cross-coupled NOR gates EECS150 - Digital Design Lecture 23 - FFs revisited, FIFOs, ECCs, LSFRs April 16, 2009 John Wawrzynek Spring 2009 EECS150 - Lec24-blocks Page 1 Cross-coupled NOR gates remember, If both R=0 & S=0, then

More information

EECS 150 Homework 8 Solutions Fall Problem 1: CLD2 Problem 8.2, showing BOTH methods (row matching and implication chart).

EECS 150 Homework 8 Solutions Fall Problem 1: CLD2 Problem 8.2, showing BOTH methods (row matching and implication chart). Problem 1: CLD2 Problem 8.2, showing BOTH methods (row matching and implication chart). Row matching: The state transition table (with one row per state) is: There are no two rows where the next states

More information

Negative Bit Representation Outline

Negative Bit Representation Outline Negative Bit Representation Outline 1. Negative Bit Representation Outline 2. Negative Integers 3. Representing Negativity 4. Which Bit for the Sign? 5. Sign-Value 6. Disadvantages of Sign-Value 7. One

More information

Models for representing sequential circuits

Models for representing sequential circuits Sequential Circuits Models for representing sequential circuits Finite-state machines (Moore and Mealy) Representation of memory (states) Changes in state (transitions) Design procedure State diagrams

More information

Logic design? Transistor as a switch. Layered design approach. CS/COE1541: Introduction to Computer Architecture. Logic Design Review.

Logic design? Transistor as a switch. Layered design approach. CS/COE1541: Introduction to Computer Architecture. Logic Design Review. Logic design? CS/COE54: Introduction to Computer rchitecture Digital hardware is implemented by way of logic design Digital circuits process and produce two discrete values: and Example: -bit full adder

More information

Sequential Circuit Analysis

Sequential Circuit Analysis Sequential Circuit Analysis Last time we started talking about latches and flip-flops, which are basic one-bit memory units. Today we ll talk about sequential circuit analysis and design. First, we ll

More information