Latch/Register Scheduling For Process Variation

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1 Latch/Register Scheduling For Process Variation Aaron P. Hurst Dept. of Electrical Engineering and Computer Sciences University of California, Berkeley Berkeley, CA Abstract Managing the effect of process variation is already a challenge, and may become more of one as device technology progresses. Because of the increasing burden of the overdesign necessary to meet overly strong timing guarantees, design flows need to be aware of the more subtle effects of particular design choices on yield. Statistical timing techniques offer exact this ability: to quantify the tradeoff between performance and yield for manufactured devices. Latch-based design offers a particularly ripe application for statistical analysis. Unlike edgetriggered registers, the variations across adjacent timing paths have the ability to interact, achieving a better yield than is possible with registers. Effects of this sort are not visible to a traditional timing analysis tool. The goal of this work is to explore the application of statistical techniques to latch-based design, both to analyze yield and to optimize it. In particular, the problem of clock scheduling for latches is examined in detail. The applicability of existing techniques is discussed, and several ideas are outlined for future work. I. INTRODUCTION With greater integration and decreasing feature sizes, managing process variation is becoming an increasing challenge. The traditional solution is to include enough conservatism in timing analysis to ensure proper device functionality in the presence of the most antagonistic variations. However, the size of this required timing margin is becoming an increasing burden. It is not uncommon for manufactured designs to reliably operate at much higher frequencies than their design specifications. This results in a significant waste of design effort to meet performance requirements that were never actually a problem and a very real cost associated with this overdesign. For designers to address this problem, two developments are necessary. They must first be able to predict the expected yield of a particular design before it has been manufactured. The degree to which the process has been characterized will clearly affect the precision of the prediction, but even coarse estimates can be made from logic structure and physical information alone. With the ability to explore the effects of different design decisions on yield, it becomes possible to optimize the tradeoffs between yield, power, performance, or cost to meet some set of specific criteria. However, even given a very limited set of transformations on a circuit, it can quickly become very difficult to evaluate and choose amongst them. In developing an optimization technique, it is desirable to consider the widest possible space in as little as possible time. This goal is particularly challenging in when considering statistical effects. Clock skew scheduling [1] offers a technique for balancing the computation by applying different non-zero delays on the clock inputs of each register. The timing of the design is then no longer limited by the single worst-case path but by the maximum average delay around any loop of register-toregister path segments. In contrast to retiming, clock skew scheduling also possesses the desirable feature of preserving circuit structure and functionality. In recent years, it has gained practical acceptance in multiple design tools, usually at the end of the flow after physical synthesis is nearly complete. The sequential elements in a design are typically one of two types: edge-triggered registers or level-sensitive latches. An edge-triggered element will propagate the value from its input to its output only at the instant during each clock cycle when the clock input is rising (or falling, depending on the implementation.) A level-sensitive device, on the other hand, will propagate the value from its input to its output whenever the clock input is high (or low.) When the level-sensitive latch is enabled to propagate transitions on its input, the latch is open or transparent. There are several advantages to utilizing each. Registerbased designs offer a simpler timing analysis, as the edge creates a well-defined sequential boundary between the logic on either side of the register. The time that a transition departs the output is entirely decoupled from the time that it arrived at the input. It is instead determined only by the timing of the clock, which is presumably regular and independent of the functionality of the circuit. The timing of a latch, however, does not possess this property. If the latch is currently transparent, a transition on its input will immediately stimulate one on its output; the timing of the logic after the latch is dependent on the timing of logic preceding the latch. Furthermore, these dependencies can be circular. Because of this difficultly, the analysis of latch-based timing is significantly more complicated than for register-based designs. Latch-based design has the advantage of being more tolerant to imbalances in the delays between adjacent paths. For two adjacent paths to operate at the mean of their delays, the arrival of the clock at a register between them must be scheduled at exactly the balancing point; the arrival of the clock at a latch between them must only be scheduled so that the balancing point falls somewhere within the transparent window. This tolerance to timing imbalance extends to the case where the imbalance is due to variations in the manufacturing process. Unlike timing imbalances that result from mispredic-

2 tions about subsequent steps in the design flow or globally mischaracterized delays, process variations impact individual manufactured instances differently. There may not be any single global correction that could compensate for all dieto-die variation. In this case, the tolerance of level-sensitive latches to timing variation offers a benefit that can not be matched with an improved design process using edge-triggered registers. It is not the scheduling but the operation of the latches that is fundamentally better. Furthermore, a purely nonstatistical static timing analysis can not quantify this effect. It is not captured by best, typical, or worst-case behavior, but by the interaction of variation across different timing paths. By examining a single worstcase value for every component, the information about the correlation between them is ignored. New analysis and optimization techniques are required. II. EXAMPLE A circuit that can achieve a better yield with a latch-based design is described in Figure 1. Due to manufacturing variations, there are four different instances of circuit timing that may be produced (as specified in the figure), each with equally likely probability. The timing diagram in Figure 2 illustrates their behaviors. If the circuit were built with registers, both the S/F and S/S cases would violate the setup condition of register R u, leading exactly half of the manufactured instances to fail. On the other hand, a latch-based design would only fail for the S/S case. In the S/F instance, the slow transition would immediately pass through the transparent window of latch R u without violating its setup condition, arriving before the clock at R v because of the subsequent fast path. The process variations would effectively cancel each other out. This sort of interaction will not be detected in the worst-case analysis; only the case where the design is most likely to fail is considered. The rate of failure will be overestimated, probably leading to some unnecessary cost to correct. R t d t u d u v Fig. 1. A basic example. The combinational logic d t u will be manufactured with a fast delay of 3 and a slow delay of 4 with equal probability. The logic d u v will be manufactured with a fast delay of 4 and a slow delay of 5 with equal probability. The period of the clock Θ is 4. R u III. STATISTICAL TIMING ANALYSIS As an alternative to costly Monte Carlo simulation, [2], [3], and [4] describe techniques for a block-based singlepass analysis. Le and Pileggi [5] propose approximating all statistical quantities as Gaussian (normal) distributions and conclude that this does not significantly affect the accuracy of the result. They also demonstrate a technique for controlling the number of pair-wise correlations stored by discarding information when no longer needed. R v Θ F/S F/F S/F S/S Fig. 2. A timing diagram. The timing of the four equally likely manufactured versions of the circuit in Figure 1 are illustrated. S and F represent the slow and fast cases, respectively, of each set of logic. Much of the complexity in block-based statistical timing analysis is in storing and manipulating the statistical quantities and their relation with each other. Propagating arbitrary probability distributions (e.g. piecewise linear) through the circuit can lead to exponential growth in the size of the representations with the size of the circuit. The degree and manner in which correlation is maintained also determines the complexity of storing the statistical relationships. Choosing the appropriate representation is critical. Any one of the techniques listed above can be used to calculate the distribution of maximum and minimum delays between every set of registers. We use a technique similar to Le and Pileggi because of its computation efficiency and demonstrated accuracy. Because scheduling techniques only modify the sequential boundaries of the circuit, the combinational delays will be constant over the course of the optimization. They need only be calculated once. The benefit to representing delays as statistical quantities is that it allows use to more exactly define the optimization space that meets the yield criteria. In the worst-case model, we fix ourselves to an unnecessarily small subset of the design space. The worst-case constraints guarantee that the timing will be met, but at the potential cost of a much overconservatism. IV. SCHEDULE VERIFICATION In the nonstatistical domain, the schedule verification problem is the test of whether a latch schedule results in a worstcase operation that is functionally correct and meets the setup and hold constraint on every latch. For registers, schedule verification is trivial; it involves nothing more than examining the setup and hold constraint on each path. For latches, the timing dependencies cross multiple adjacent paths, and the problem is more difficult. There are two existing classes of solution methods: iterative and structural. The iterative method, first proposed by [6], begins with the earliest possible arrival times and continues propagating the earliest and latest arrival times through the cyclic circuit until they both converge to fixpoints. The structural method, introduced by [7], operates on a graph of the latch timing constraints. The schedule is infeasible if and only if there exists a negative cycle in the constraint graph. The result of the nonstatistical verification problem is binary; a schedule either functions correctly or it does not. In the statistical domain, however, the result is a probability that the

3 circuit will function correctly. It s not immediately clear how either of the existing methods directly apply to the statistical problem. The proof of convergence for the iterative method is not readily extended to probability distributions, nor is the negative cycle detection required for the structural method directly applicable to graphs whose edges are probabilistic expressions. paths u v latches i B u + D u v T + τ v t setup b u + d u v τ v + t hold B v B u + D u v b v b u + D u v B i τ i b i τ i (1) A. Structural Chen and Zhou [8] describe a technique for extending the structural verification of [7] into the statistical domain. Because a schedule fails if and only if there is a negative cycle, the yield is exactly the probability that there exists a negative cycle. They propose a heuristic to approximate this quantity. Single backwards edges are randomly selected, and the distribution of the minimum acyclic path length between the ends of each edge is computed. There is a negative cycle through the selected graph edge when the sum of the forward and backwards components is negative. With enough coverage, the likelihood of a negative cycle occurring anywhere in the probabilistic constraint graph can be estimated. B. Iterative Chen and Zhou dismiss a statistical version of the iterative method because of the problems inherent in proving convergence. Assuming that the latch schedule is feasible, the nonstatistical iterative algorithm will reach a fixpoint after which any more iterations and the application of the max and min operators will not affect the result. In the statistical domain, however, the max and min operators do not have the same simple noncontinuous behavior that they do for single values. Assuming that the iterative method does converge for quantities that are statistical distributions, it appears to be equally applicable to the problem of schedule verification under process variation. Unlike the solution of [8], it is deterministic, and an error bound can be established and met with enough iteration. Once the distribution of the arrival times has been computed for each latch input, the overall yield is exactly the conjunction of the yield of each latch, that is, the probability that no transition violates any latch setup or hold constraint. V. SCHEDULE OPTIMIZATION The statistical clock scheduling problem is that for a given period T, find some clock schedule τ (T ), τ (T ) that maximizes the yield of the design. We need to define the intermediate values b i and B i, the latest and earliest departure times from the latch i. d u v and D u v are the longest and shortest delays along path u to v. Here, it is assumed that the number of clock cycles that are allotted a computation is equal to the number of sequential elements; while the scheduling problem can be extended to include cases where this isnt true, it is not relevant to the question under study. minimize T, s.t. While this is a most general formulation of the clock scheduling problem for latches, it will not necessary lead to solutions that can not be practically implemented. In particular, the requirement that each register is clocked with an oscillating signal of different duty cycle is difficult to realize. For this reason, well define a restricted scheduling problem, selecting only a single duty cycle for the whole circuit. A set of additional constraints, Equation 2, is added to the problem, where w is the single global duty cycle. A. Edge-Triggered t = t + w (2) In the edge-triggered case, we can add the additional constraint that the transparent window has zero width, Equation 3. w = 0 (3) Because the arrival and departure times are now decoupled, we can write the scheduling problem in the familiar form for registers. minimize T, s.t. paths u v Y (T, τ) = P ( paths u v τ u + D u v T + τ v t setup τ u + d u v τ v + t hold (4) (τ u + D u v τ v + t setup T ) (τ v d u v τ u + t hold 0) ) (5) The general procedure for scheduling registers is as follows. Let us consider a single vector in the input space of Y (T, τ), resulting in a one-variable function Y (t) where t is the distance along that vector. Because each timing constraint is a linear inequality of the single-valued variables T and τ and one normal random variable X (either a longest or shortest path delay), it reduces to a linear constraint of the form (X < at + b) along this vector. Because normal distributions remain normal under linear transformation, we can rewrite this linear constraint as the CDF of some normal variable X. However, since the standard deviation, σ, of the random variable X is defined to be a nonnegative real number, we must fix a to be nonnegative, possibly leading to a constraint of (X < t). Whether a constraint reduces to the form (X < t) or (X < t) depends on the original sign of t. Each variable X will be correspondingly placed into one of two subsets:

4 X +, those that result from a constraint that is a function of a t, and X, those that result from a constraint that is a function of t. There is one such partition for each direction, regardless of the choice of point. The probability that the conjunction of the simple constraints (X < t) is satisfied is equivalent to the probability that their maximum satisfies the simple constraints. Let M + and M be the maximum of the sets X + and X respectively. The expression of Y (t) in the form of Equation 6 was derived through a repeated application of the max operator. Y (t) = P(M + t) P(max(M +, M ) t) (6) In general, the random variables M + and M will be nonnormal because of the nature of this operation. However, if we instead use the approximated max operator described in [9], we can generate a normal approximation to these two quantities. If these approximation are substituted into Equation 6, let the resulting function be Y aprx and the corresponding gradient be ( Y ) aprx. For each gradient direction τ i, only the setup and hold constraints for paths adjacent to the register R i will be functions of τ i. The size of the resulting set X will typically be small, requiring only a few max operations and introducing minimal approximation error. As an optimization technique, the conjugate gradient method offers a robust and efficient procedure for the local maximization of differentiable functions. We use it to find the maximum of Y aprx. While non-linear optimization only guarantees a local maximum, we seek a global maximum. Fortunately, even though Y aprx is nonconvex, it has a single local maximum for each value of T. The proof is in [10]. B. Level-Sensitive The problem of level-sensitive scheduling, Equations 1 2, is more difficult. If it assumed that each transition departs the latch at the latest possible time (B i == τ downarrow ), the problem reduces to the scheduling problem described in the previous section, though the predicted yield will be only a lower-bound. Clearly, many of the signals will depart the latches at the middle or beginning of the transparent window and meet the subsequent setup conditions with much higher probability than predicted. If we instead consider the case of two adjacent paths (with the transition departing the originating latch at the latest possible time), we now have a double-path constraint as in Equation 7. The problem reduces to a similar scheduling problem, but with a set of constraints that arise from each double-path. The result will still be a lower bound, but a less conservative one. This process could be continued, unrolling loops into n-path constraints. The likelihood that the transition passes through n transparent windows will quickly fall towards to zero, and the predicted yield will approach the actual one. Cycles will converge at different rates. τ t + max(t + τ t, D t u ) + D u v 2T + τ t (7) An alternative strategy is to break all cyclic dependencies by replacing some minimal set of latches with edge-triggered devices, such that there is no cyclic path through the circuit that does not contain at least one edge-triggered device. While this greatly simplifies the problem of analysis and optimization, it leads to a solution that is less variation-tolerant than an all-latch design. However, by choosing a good subset of latches to replace with registers, it should be possible to produce a solution that is nearly equivalent. For each latch, one can compute the probability P(B i == τ ), the likelihood that transition arrived at the input before the latch became transparent (and thus the transition departed when the latch opened). From a timing standpoint, this is the probability that the latch will behave no differently than an edge-triggered register. By breaking cycles by greedily choosing the latches that maximize this probability, the solution should not be greatly perturbed. Because many paths in real designs have significant slack, there should be many such choices, and the solution should be minimally affected. VI. EXPERIMENTAL RESULTS We ran the following experiments on a subset of the ISCAS benchmark circuits, mapped to a standard technology library. Because the library lacked information about the statistical timing behavior of each gate, we arbitrarily assumed that the worst-case gate delays were 3σ values, i.e % of manufactured instances of each gate meet the worst-case timing. With this assumption, a normal delay distribution can be derived from the typical and worst-case values. We also assumed that half of the variation of each gate delay was globally correlated, and half was local. Register-to-register delay distributions were calculated using a combinational statistical timing analysis similar to [5]. In this method, all statistical quantities are approximated by normal distributions. The analysis required two operations to be defined for these quantities: sum and max. While the sum of two normal distributions is also normal, the maximum of two is not. Heavy use is made of the approximation described by [9]. For the benchmark circuits tested, the combinational portion of the analysis had negligible memory and runtime requirements. Our statistical timing tool was written in C++ and run on a 3.0 GHz Intel machine. A. Iterative Verification The first experiment seeks to empirically verify the convergence of the iterative approach to latch schedule verification with statistical quantities. Given a target clock period and a latch schedule (arbitrarily a zero skew schedule), the iterative algorithm was applied to several of the benchmarks and run until convergence was reached. Since all of the timing quantities are approximated by normal distributions, convergence was defined as a change of no more than 0.1% in either the mean or the standard deviation of any arrival time between two iterations. In all of the benchmark circuits tested, the iteration reached a fixpoint, and the total number of iterations is listed in

5 Fig. 3. (a) Exact (b) Approx. An example of the max approximation gone awry. Table I. The first column is the number of iterations required for a nonstatistical analysis, and the last three columns are statistical analyses under three different target clock periods: slightly above the maximum mean cycle, slightly below the maximum mean cycle, and significantly below the maximum mean cycle. It may seem surprising that the statistical analyses converge almost as quickly as the nonstatistical one, but this is probably due to the fact that the majority of paths in each of these circuits have significant timing slack. In almost all instances, the transition will arrive before the latch even opens, and the departure time will be fixed at the latch opening. The results also reflect the expected fact that the convergence takes longer under the tighter target period; the number of transitions that arrive late and inside the transparent window of the latch is increased as the period is shrunk. One potential problem with the iterative method lies in the error of the approximated max operator of [9]. In the course of combinational timing analysis, the quantities used as operands typically have standard deviations that are within the same order of magnitude (because the standard deviations of gate delays are fairly similar from gate to gate.) The error introduced by the max operator is minimal under these circumstances. This is not the case in the latch-based algorithm. Because the opening of the latch window is exactly defined, one of the operands will have zero deviation (σ = 0). An example of this situation is illustrated in Figure 3. An arbitrary arrival distribution is shown, and if the latch opens at time 0, the resulting departure distribution (max(0, t arrival )) is illustrated. The resulting PDF from the max approximation (on the right) visible differs from the exact version of the operator (on the left). A significant portion of distribution of the departure time even appears to lie before the point where the latch is opened; this does not match reality. Because of the degree of error in each max approximation, a more detailed exploration of the effect on the final result needs to be conducted before overall yield results for latches are presented. Alternatively, another method of approximating statistical distributions (i.e. one that is not strictly normal) may be required. B. Edge-Triggered Scheduling We applied the edge-triggered clock schedule optimization algorithm to compute a yield-aware clock schedule for each of these benchmarks, and then compared it against two alternatives: no clock schedule, and an optimal schedule under the linear formulation. To solve the linear clock scheduling problem, we used an implementation of Howard s algorithm [11]. This has been empirically verified [12] to be the fastest maximum mean cycle solver for VLSI applications. Along with the maximum mean cycle time, the algorithm returns a schedule that meets this optimal time, and we use this result as the point of comparison. A standard implementation of conjugate gradient minimization based on [13] was used. The results of these three scheduling techniques are compared using two different target metrics: reliability (Table II) and performance (Table III). For a set of target clock periods (arbitrarily selected to be the T 3σ points of the statistical schedules), Table II demonstrates that the statistical scheduling results in a (logarithmic) average 13x decrease in the failure rate, compared to the yield of the same design with optimal linear scheduling. Similar results are seen for other target clock periods. Equivalently, statistical scheduling can be used to improve performance under a yield constraint. In III, two types of performance results are presented: T wc and T 3σ. T wc is the worst-case delay along the longest path; this is the overconservative result of a traditional static timing analysis. T 3σ is the clock period that will result in failures for manufactured instances that fall outside of 3 standard deviations worse than the mean performance. Although this information results from a statistical timing analysis and is not part of a design flow built on the worst-case model, we wish to demonstrate that our optimization clock schedule is better under comparable analyses. The yield-aware schedule realizes a better yield that translates into a 4% gain in performance. If a purely nonstatistical design flow is used, our result is 19% better than the worst-case prediction of a linearly scheduled design. Since the problems with the linear model are even worse for complex designs, we expect the improvements to be greater for larger examples. VII. CONCLUSION Designing for yield offers clear advantages, and as advancing process technology incorporates more variation, yield will become an even more important design metric. It s not enough to make pre-manufacturing corrections. The synthesis process needs to fully incorporate the yield metric as a criterion in evaluating design choices. The possible payoff lies not only in fewer failures, but in other attributes that are currently being compromised to meet worst-case scenarios that may not reflect any actual manufactured instances. The goal of this project was twofold: to be able to estimate the yield of a latch-based design, and to be able schedule the clocks to optimize the yield-performance tradeoff. Current nonstatistical timing tools can not even account for the tolerance to timing variation that level-sensitive clocking allows, let alone optimize the schedule appropriately. The current results indicate some promise along both fronts, but the problem is significantly challenging, and more is definitely to be done.

6 Iterations Design Nonstatistical Statistical (T MMC + 1) (T MMC 1) (0.8T MMC) s s s s s s TABLE I ITERATIONS UNTIL CONVERGENCE OF LATCH ARRIVALS No Sched. Opt. Linear Sched. Statistical Sched. Size, # Setup Improv. f fail (v. Lin.) Design # Cells Constraints T target Yield Yield Runtime Yield Raw Log 10 Runtime s <0.001s x s s s x s s <0.001s x s s <0.001s x s s <0.001s x s s <0.001s x s s <0.001s x s s <0.001s x s s <0.001s x s s <0.001s x s TABLE II EXPERIMENTAL RESULTS, YIELD IMPROVEMENT No Scheduling Optimal Linear Schedule Statistical Schedule Design T W C T 3σ T W C T 3σ T 3σ % Improv. (v. Lin. T 3σ) s % s % s % s % s % s % s % s % s % s % TABLE III EXPERIMENTAL RESULTS, PERFORMANCE IMPROVEMENT ACKNOWLEDGMENT This work was funded in part by the MARCO Focus Center for Circuit & System Solutions (C2S2, under contract 2003-CT-888. REFERENCES [1] J. P. Fishburn, Clock skew optimization, IEEE Trans. on Computing, vol. 39, pp , July [2] J.-J. Liou, K.-T. Cheng, S. Kundu, and A. Krstic, Fast statistical timing analysis by probabilistic event propagation, in Proc. 38th Design Automation Conference, June [3] A. Devgan and C. Kashyap, Block-based static timing analysis with uncertainty, in Proceedings of the ICCAD, pp , [4] H. Chang and S. S. Sapatnekar, Statistical timing analysis considering spatial correlations using a single pert-like traversal, in Proceedings of the ICCAD, pp , [5] J. Le, X. Li, and L. T. Pileggi, Stac: Statistical timing analysis with correlation, in Proceedings of the 41st Annual Conference on Design Automation, pp , ACM Press, [6] K. Sakallah, T. Mudge, and O. Olukotun, Timing verification and optimal clocking of synchronous digital circuits, in Proceedings of the ICCAD, pp , [7] T. G. Szymanski and N. Shenoy, Verifying clock schedules, in Proceedings of the ICCAD, [8] R. Chen and H. Zhou, Clock schedule verification under process variations, in Proceedings of the International Conference on Computer- Aided Design, November [9] C. Clark, The greatest of a set of random variables, Operations Research, [10] A. Hurst and R. K. Brayton, Computing optimal clock skew schedules

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