1 TITLE PAGE NOTE: NOTES IN GREEN TEXT ARE GENERAL DESIGN OR SCHEMATIC NOTES

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1 - TITLE PGE TLE OF ONTENTS PGE ESRIPTION TITLE PGE R SRM NOR & NN FLSH ETHERNET PHY & RS- MSQG PROESSOR (R) oldfire MF PROESSOR POWER SUPPLY KEYP & ZIGEE INTERFES US L INTERFE OLOR LEGEN NOTE: NOTES IN GREEN TEXT RE GENERL ESIGN OR SHEMTI NOTES LYOUT NOTE: NOTES IN VIOLET TEXT RE P LYOUT REOMMENTIONS OR GUILINES NOTES IN LK TEXT INITE PRTIULR FUNTIONLITY OF SPEIFI PRT OF THE SHEMTI FOR LRIFITION OF THE FUNTIONLITY. NOTE: IS N ITION FOR "O NOT SSEMLE", WHIH PPLIES TO OMPONENTS THT RE NOT MENT TO E POPULTE ON THE OR. THIR NGLE PROJETION FETURES N IMENSIONS NOT SHOWN SHLL E VERIFIE IN THE TSE. RWING SHOUL NOT E SLE ENGR: RWN: J. P. KELL M. J. KI PROPRIETRY USE PURSUNT TO LL RIGHTS RESERVE OMPNY INSTRUTIONS RWING TITLE: / QG REFERENE ESIGN PROJET NME: FREESLE POS TERMINL TE RWING NO. -- E SLE: NO SLE OF P

2 - R SRM [,] up_[:] U up_[:] [] [] up_s_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ [,] up_[:] [] up_s_qs/ [] up_s_qs/ [] up_s_m [] up_s_m [] [] up_s_nlk up_s_lk R [] up_ske /P LQS UQS LM UM nk KE K Q Q Q Q Q N N N Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q ns nrs ns nwe VREF V V V VQ VQ VQ VQ VQ MTVMP-:F NU NU N N up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_nss [] up_nrs [] up_ns [] up_nswe [].V_R µf.v.µf.µf.v_r R.K R.K pf.µf NOTE: Keep R SRM close to PU, so that ddress, ata, and ontrol signal paths are very short, and the same length..v pf R.V_R NOTE: Locate bypasses between V & pin pairs..µf pf.µf pf.µf pf.µf pf.µf pf.µf pf M R SRM LL RIGHTS RESERVE TE -- SLE: NO SLE PROPRIETRY USE PURSUNT TO OMPNY INSTRUTIONS RWING NO. E P OF

3 .V R.V_NOR.µF pf.v.µf - NOR & NN FLSH up_m[:].v_nor.µf pf [] up_nreset up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m R K R K Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q/- VIO N N N RY/Y RESET YTE OE E N N V U SGLNT WE WP/ N M NOR FLSH up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_nmwr.v_nor up_m[:] NOTE: NOR Flash footprint should accomodate Meritec -- TSOP Socket w/ locator pins. Note: nwp is pulled high internally R U SOKET-TSOP R K up_nms up_nmr up_m[:].v up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m V V V V GN GN GN GN.µF.µF.µF U LV IR OE IR OE GN GN GN GN up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_.v R K R up_nr up_[:] [] µf.v UP_M up_m up_m[:].µf.µf.v up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m up_m.v V V V V Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y GN GN GN GN U OE OE OE OE GN GN GN GN LV.µF UFF_nOE up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ R up_ns R up_[:] [,].V.V_NN R up_m[:] up_m up_m up_m up_m up_m up_m up_m up_m M NN FLSH (OPTIONL).µF V VQ I/ I/O I/O I/O I/O I/O I/O I/O N N N N N N N N N N N N N N pf.µf U N N N N N RY/Y RE E N N N N LE LE WE WP N N N N N GN TVMTG pf NN_RYnY NN_nRE NN_nE up_ up_ NN_nWE.V_NN up_nreset [] R K up_[:] [,] T US LEVEL SHIFT U LVG.V.µF up_nms.v up_nmwr.v up_nmr R K U.µF NN_nGPIO [] LVG.V.V R K U.µF up_nwr LVG.V.V R K R K up_nr up_ns [] NN FLSH ENLE LOGI up_m up_m up_m up_m up_m up_m up_m up_m V V V V Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y GN GN GN GN.µF UFF_nOE up_ up_ up_ up_ up_ up_ up_ up_ RESS US LEVEL SHIFT LL RIGHTS RESERVE TE -- U OE OE OE OE GN GN GN GN LV SLE: NO SLE R.V RWING NO. up_ns [] up_nwr [] up_nr [] PROPRIETRY USE PURSUNT TO OMPNY INSTRUTIONS E R K R OF P

4 [,,] MSTR_nRESET [] up_mio [] up_m.v_phy R.K.V_PHY.V R.V_PHY - ETHERNET PHY & RS- PORT NOTE: Minimize trace lengths between crystal & P R.µF R R pf pf NOTE: PHY RESS = Y EFULT [] [] [] [] [] [] [] [] up_rx_lk up_rx_v up_rs up_rx_er up_ol up_rx[:] up_tx_lk up_tx_en Y.MHz P up_rx up_rx up_rx up_rx R (.K).V_PHY R (.K) R MII, LE, & MIX STRPPING OPTIONS (.K).V_PHY.µF IOGN X X PF PFIN RX_LK RX_V/MII_MOE RS/RS_V/LE_FG RX_ER/MIX_EN OL/PHY RX_/PHY RX_/PHY RX_/PHY RX_/PHY IOGN IOV µf.v.µf TX_LK TX_EN TX_ TX_ TX_ TX_/SNI_MOE PWR_OWN/INT TK TO TMS TRST# TI up_tx up_tx up_tx up_tx IOV M MIO RESET_N LE_LINK/N LE_SPEE/N LE_T/OL/N_EN MHz_OUT ETHERNET PHY U RIS PFOUT V RESERVE RESERVE GN PFIN T + T - GN R + R - PVV TEST PINS HVE INTERNL PULL UPS/OWNS R.K PF PF.µF µf.v.µf R.K R.K.V_PHY.V_PHY.µF R..µF R..V_PHY.µF R. R..V_PHY.µF.V_PHY R.µF NOTE: Place aps close to XFMR center taps. RJ- ETHERNET PORT.V_PHY U TP TN RP T R RN N P YEL_ YEL_ GR_ GR_ Mod P HSSIS HSSIS [] up_tx[:] [] PHY_nIRQ.V U pf.µf.µf RS- TRNSEIVER.µF.µF.µF REY + V V- TOUT RIN ROUT FOREOFF V GN TOUT RIN ROUT FOREON TIN TIN INVLI MXE R R R R R J -Sub -F RS- PORT (WIRE S E - USE STNR MOEM LE) [] [] [] [] up_urt_rx up_urt_tx up_urt_rts up_urt_ts LL RIGHTS RESERVE TE -- SLE: NO SLE PROPRIETRY USE PURSUNT TO OMPNY INSTRUTIONS RWING NO. E P OF

5 - MSQG PROESSOR.V.V R.V_QG R [,,] [] [,] [,] [] MSTR_nRESET up_spi_qg_ns up_miso up_mosi nmrst_qg nshut_own TEST_SWITH.V QG nreset TEST POINT NOTE: QG USES N INTERNL LOK SOURE J R K KG.V_QG J Header x-m R U PT/IRQ/TLK V PT/MPO PT/SL/EXTL PT/TPMH PT/S/XTL PT/KIP PT/TPMH/SS PT/KIP PT/MISO PT/KIP PT/KIP/MOSI PT/P PT/KIP PT/KIP/SPSK MSQG.V µf V.µF QG_WKEUP [] up_spi_lk [,] Red QG HERTET LE R R pf.v J Header x-m TO FRONT PNEL STTUS LEs NOTE: LE PORT SSIGNMENTS PT = GREEN STTUS LE ON FRONT PNEL (TIVE LOW) PT = RE OMM. STTE LE ON FRONT PNEL (TIVE LOW) PT = RE HERTET LE ON OR (TIVE LOW) S TT.V Header x-m QG M PORT R K.µF Schmitt uffer U N V GN Y LVG.V.µF VOLUME ONTROL / INPUT TEST_SWITH R K.µF.µF K V V_SPKR V_SPKR R R K K.µF R V_SPKR R K R.µF - + U Vo Vo µf LM J Header x-m SPEKER QG TEST SWITH nshut_own R K Q MMT PWM LOW PSS FILTER & POWER MPLIFIER LL RIGHTS RESERVE TE -- SLE: NO SLE PROPRIETRY USE PURSUNT TO OMPNY INSTRUTIONS RWING NO. E P OF

6 .V R.KHz REL TIME LOK RYSTL.MHz ORE RYSTL - OLFIRE MF PROESSOR K R R [] RESET INPUT FROM QG M PORT nmrst_qg NOTE: Keep M signal path lengths (T & PST) the same and less than " long..v MFP-PST MFP-PST MFP-T MFP-T.V R NOTE: R is normally populated up_ nmrst_.v.v.v up_.v PLL Mode up_ Mode LOW MHz/MHz HIGH MHz/MHz * up_.v R up_.v R up_.v_pll up_ US_.V.V OS_.V RESET UTTON S TT.V up_tms up_ntrst up_ti up_to MFP-PST MFP-PST MFP-T MFP-T up_nwit.v.v up_.v M/JTG PORT NOTE: Place near oard Edge with Pin on outside. onfirm that sufficient clearance exists for M Pod & able. J NOTE: ONLY.V M debugging cables can be used with MFx processors. Oscillator Mode up_ Mode LOW rystal oscillator * HIGH Oscillator bypass Encoded oot evice (Port Size) up_ up_ Mode LOW LOW -bit port LOW HIGH -bit port HIGH LOW -bit port* HIGH HIGH -bit port LVG.V up_tk up_ up_ up_ up_ RON_b.V SHMITT UFFER.V.V up_.v NOTE: R is normally populated and R is not. PU REGISTER ONFIGURTION SETTINGS UPON RESET R K R R µf V µf V µf V R R K Output Pad rive Strength up_ Mode LOW Low drive HIGH High drive * NOTE: Place US_.V filter circuit as close as possible to Pin L on the MF PU..µF Limp Mode Selection up_ Mode LOW Normal PLL mode * HIGH Limp mode NOTE: Place.V_PLL filter circuit as close as possible to Pins J (V PLL) and K (_PLL) on the MF PU..µF.µF.µF R K R R K Header x-m R R K R K R K R R K.µF R K R K NOTE: Place OS_.V filter circuit as close as possible to Pins K (V_OS) and L (_OS) on the MF PU..µF R U N V GN Y R R R R K U R R K up_.v RESET IRUIT.V V.V PU Register onfiguration RON_b Mode LOW Enabled* HIGH isabled Encoded ddress/hip Select onfiguration up_ up_ Mode LOW LOW [:] = [:]* LOW HIGH = F_S_b, = HIGH LOW Reserved HIGH HIGH [:] = F_S[:]_b pf.µf.µf LVG R R pf.µf R.K R.K % pf.µf RESET LE U MR RESET VRESET GN N PFO_nIRQ PFI PFO M Power Fail Interrupt is generated when V Supply decreases to V. IRQ SWITH TEST SWITH J J J J J J J J J.µF.µF S S pf.µf TT TT.V.V up_nreset MSTR_nRESET up_nwr up_nr up_nwit up_k F_LK up_ns up_ns HERTET LE R K.µF.V Schmitt uffer LVG Schmitt uffer U LVG TEST POINTS nle_re.v.v up_miso up_mosi.µf SWITH_nIRQ.µF TEST_SWITH up_spi_lk up_spi_zigee_ns up_spi_qg_ns [,,] [] MSTR_nRESET.V.V Note: Place Signal Names in silkscreen next to Test Point Pin. [] [] up_nreset TEST LES R TEST SWITHES pf R K.µF.µF Q MMT J J J J J U pf R R K R R N V GN Y.µF Red Red N V GN Y pf.µf R.K Green pf R Yellow KEYP_OL[:] [] [] [] [] [] M Y.kHz P KEYP_nIRQ PHY_nIRQ ZIGEE_nIRQ US_O_nIRQ US_O_nIRQ KEYP_ROW[:] pf R K up_.v up_.v [] [] [] [] [] [] [] [] [] [] pf [] [].µf [] [] [] [] up_nss up_ske up_nswe KEYP_OL KEYP_OL KEYP_OL KEYP_OL KEYP_OL SWITH_nIRQ PFO_nIRQ [] [] up_rx[:] up_tx[:] [] [] [] [] [] [] [] [] [] [] [] up_ns up_nrs up_s_nlk up_s_lk up_s_qs/ up_s_qs/ up_s_ [] [] up_.v KEYP_ROW KEYP_ROW KEYP_ROW KEYP_ROW up_nwr up_nr up_ns up_ns up_rx_er up_rx_v up_tx_lk up_tx_en up_rx_lk up_ol up_rs up_m up_mio PWM_KLIGHT QG_WKEUP US_EN US_EN up_s_m up_s_m [] [] [] [] [] [] [] [] [] up_nwit up_k F_LK R up_rx up_rx up_rx up_rx up_tx up_tx up_tx up_tx nle_re nle_yellow nle_green NOTE: Keep M signal path lengths (T & PST) the same and less than " long. pf.µf R K M Y.MHz P pf R K up_urt_ts up_urt_rts up_urt_tx up_urt_rx ZIGEE_RXTXEN ZIGEE_nTTN_IN ZIGEE_ILE ZIGEE_V_R NN_nGPIO pf.µf R K pf UP_S_M UP_S_M R R UP_NS UP_TX_ER pf R K.µF up_.v R.K S_R_QS R K MFP-T MFP-T MFP-T MFP-T MFP-PST MFP-PST MFP-PST MFP-PST TEST_SWITH pf.µf up_lk_ up_lk_ up_lk up_lk R R R K R K pf N P P R N P N R G H T L P L N H J H H H P R R R L T P P.µF E E H H H H G G F G G K K K J J J J P N P N T R T R E E E F R T T R E E E F F U XTL EXTL OS_KIN OS_KOUT RST_IN_b RST_OUT_b RW_b OE_b T_ TS_/K F_LK S_ S_ S_ S_ F_S_b F_S_b F_S_b F_S_b F_S_b F_S_b S_S_b S_S_b S_KE S_WE_b RMSEL S_S_ S_RS_ S_LK_b S_LK S_QS/ S_QS/ S_R_QS S_ FE_RX FE_RX FE_RX FEX_RX FE_TX FE_TX FE_TX FE_TX FE_RXER FEX_RXV FE_TXLK FE_TXEN FE_TXER FE_RXLK FE_OL FE_RS FE_M FE_MIO PWM PWM PWM PWM SSI_TX SSI_RX SSI_LK SSI_FS SSI_MLK IRQ_b IRQ_b IRQ_b IRQ_b IRQ_b IRQ_b IRQ_b T T T T PST PST PST PST TIN/TOUT TIN/TOUT TIN/TOUT TIN/TOUT TS RTS TX RX TS RTS TX RX SL S up_.v ORE_V E ORE_V M ORE_V G ORE/V_ M MFVM up_.v V G V G V E V F V F V F V F V H V H V J V K V L V L V L V M up_.v S_V E S_V F S_V F S_V F S_V G S_V H S_V J S_V J S_V K S_V K S_V L S_V L S_V L S_V L S_V M up_.v up_.v.v_pll US_.V (R) Freescale oldfire Microprocessor MF G G G G H H H H J J J J K K K K L pf.µf V_RT M pf.µf US_V L up_.v S_LK_VE M pf up_.v TLK_VE M.µF.V_PLL V PLL J V_OS K OS_.V _PLL _OS /F_S_ /F_S_ F_ F_ F_ F_ F_ F_ F_ F_ F_ F_ F_ F_ F_ F_ F_ F_ F_ F_ F_ F_ F_ F_ T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T L L L/FE_O L/FE_R L/FE_RX L/FE_RX L/FE_RX L/FE_RX L/FE_RX L/FE_RX L/FE_RX L/FE_TX L/FE_TX L/FE_TX L/FE_TX L/FE_TX L/FE_TX L/FE_TX LP/HSYN FLM/VSYN LSLK SPL_SPR PS LS ONTRST /OE QSPI_IN QSPI_OUT QSPI_LK QSPI_S QSPI_S QSPI_S US_MNS US_LPS USH_ USH_MNS USH_LPS TMS/KPT_b TLK/PSTLK TRST_b/SLK TO/SO TI/SI JTG_EN PLL_TEST TEST RON_b N N N N pf.µf K L E E E E F F F F G G G M M M M N N N N T P R T N P R T J J J K K K K L R N P R T P R T E N P R T T P L L M M M R T P N N M N M T F T pf.µf NOTE: please place the resistor packs below as close to PU as possible. R R R R R R R R R R L_HSYN L_VSYN R L_SPL L_PSVE L_LS L_MISP L_ R TEST POINTS US PORTS RON_b R R R R R R R R R L_LK [] L_OE [] R K R R R R R R G G G G G G up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_ up_miso [,] up_mosi [,] up_spi_lk [,] ZIGEE_NTTL [] up_spi_zigee_ns [] up_spi_qg_ns [] up_us_m [] up_us_p [] up_us_m [] up_us_p [] R K up_.v up_.v TE -- up_tms up_tk up_ntrst up_to up_ti JTG_EN up_[:] [,] up_[:] [] up_[:] [] R[:] [] G[:] [] [:] [] INTERFE TO SHRP LQSG." TFT SVG L R K R K SPI PORT TO QG & ZIGEE NOTE: there should be a ohm differential phase impedance between signals up_usx_- & up_usx_+. Please couple these traces as soon as they leave the PU through to the US jacks. J R K Header x-m R K R K JTG/M SELETION JUMPER JTG/M onfiguration Jumper Position Mode JTG - M LL RIGHTS RESERVE SLE: NO SLE TO JTG/M ONNETOR RWING NO. E PROPRIETRY USE PURSUNT TO OMPNY INSTRUTIONS P OF

7 J INPUT VOLTGE V +/- Power NOTE: Power connector is center tap positive, and input is V. Please show this in the silkscreen. Note: Place GN Test Points in four corners of board and add Silkscreen Labels. L lso add Silkscreen Labels for V, V,.V,.V, &.V Test Points. GN TEST POINTS E E ONNETOR TO PNEL SWITH E J Header x-m E pf.µf F V SMT V TP E R K Green V + µf V V Power + µf V Note: For heatsinking, connect LMES tab to approx. sq. in. of copper plane..µf +.µf V.V U up_.v R IN OUT + R µf µf MI.V µf V GN T-GN R K +.µf V +.µf V U VIN EN GN LM OOST.V TP E SW F MM-F.µF L µh V US SUPPLY.V PU & LOGI SUPPLY.V Note: Please follow layout and grounding guidelines in the LM datasheet..µf U INPUT ON/OFF SYN R K LMS GN R FEEK -OOST SWITH-OUT µf V.µF - POWER SUPPLIES V TP E R.K R.K L µh R R Green V Power.V TP E V Note: Please follow layout and grounding guidelines in the LMS datasheet..v R SRM SUPPLY + µf V + µf V R R + µf V.V up_.v R Green.V Power.V TP E R.V.V up_.v Note: For heatsinking, connect LMES tab to approx. sq. in. of copper plane. R K µf V U LPES INPUT OUTPUT S GN T-GN IS V.µF R + µf.v.v ORE SUPPLY LL RIGHTS RESERVE TE -- SLE: NO SLE PROPRIETRY USE PURSUNT TO OMPNY INSTRUTIONS RWING NO. E P OF

8 - KEYP & ZIGEE INTERFES.V.V [] KEYP_OL[:] KEYP_OL KEYP_OL KEYP_OL KEYP_OL KEYP_OL R K R K R K R K R K.µF U H NOTE: The processor scans the rows and reads the columns. When not scanning, the processor should hold the rows low, if Keypad Interrupt is being used. J Header x-m KEYP PINS P - N - M - L - K - J - H - G - F.V U H.V U H.V U H KEYP_nIRQ [] [] KEYP_ROW[:] KEYP_ROW KEYP_ROW KEYP_ROW KEYP_ROW T T T T TO GRYHILL J ROW x OLUMN KEYP KEYP INTERRUPT.V.V R J R R K K.µF ZIGEE_nIRQ [] [] ZIGEE_ILE [] ZIGEE_V_R [,,] MSTR_nRESET [] ZIGEE_nTTN_IN [,] up_mosi [,] up_miso ZIGEE_RXTXEN [] [,] up_spi_lk ZIGEE_NTTL [] [] up_spi_zigee_ns Header x-f TO FREESLE MU ZIGEE TRNSEIVER MOULE LL RIGHTS RESERVE TE -- SLE: NO SLE PROPRIETRY USE PURSUNT TO OMPNY INSTRUTIONS RWING NO. E P OF

9 US PORT POWER SWITH V - US HOST INTERFES.V.V [] [] [] US_EN [] US_EN US_O_nIRQ US_O_nIRQ.V U V N Y GN LVG U V N Y GN Schmitt uffers R K R + µf V R K R + µf V U EN OUT FLG IN FLG GN EN OUT MI + µf V + µf V.µF + µf V pf U N GN GN N SN TRNSIENT SUPPRESSION L Ohm J VUS - + GN SHIEL SHIEL US L Ohm ROE SNNER PORT (EXTERNLLY ESSILE).µF LVG [] [] up_us_m up_us_p R. pf R K pf R. R K L US_M US_P US-ML o o NOTE: The US differential pairs US_M, US_P, & US_M, US_P need to be routed such that they have a differential impedance of ohms. [] [] up_us_m up_us_p NOTE: Keep. ohm resistors and pf caps close to processor US pins. R. R. R R pf K pf K L o US-ML o US_M US_P Please route the US pairs on the top signal layer with a solid ground plane underneath. pf U N GN GN N SN L Ohm J VUS - + GN SHIEL SHIEL US L Ohm MG R / SMRT R PORT (INTERNLLY ESSILE) TRNSIENT SUPPRESSION LL RIGHTS RESERVE TE -- SLE: NO SLE PROPRIETRY USE PURSUNT TO OMPNY INSTRUTIONS RWING NO. E P OF

10 - L INTERFE V R V_L V_L V_L [] PWM_KLIGHT R K R.K R.K Q MMT Q MMT MM-F + µf V.µF J Header x-m POWER & PWM RIGHTNESS ONTROL FOR ERG m KLIGHT INVERTER NOTE: The "" Jumper needs to be removed from the ERG m oard, to enable the acklight PWM ontrol. PWM LEVEL SHIFT.V R [] L_OE [] [:] [] G[:] [] R[:] [] L_LK µf V.µF G G G G G G R R R R R R pf J INTERFE TO SHRP LQSG." TFT SVG L FG-P-H LL RIGHTS RESERVE TE -- SLE: NO SLE PROPRIETRY USE PURSUNT TO OMPNY INSTRUTIONS RWING NO. E P OF