CS221: Digital Design. Indian Institute of Technology Guwahati

Size: px

Start display at page:

Download "CS221: Digital Design. Indian Institute of Technology Guwahati"

Jayson Edwards
6 years ago
Views:

1 CS221: Digital Design FlipFlop&Register Flop Dr. A. Sahu DeptofComp.Sc.&Engg. Indian Institute of Technology Guwahati

2 Outline Level Sensitive (Latch) vsedge Sensitive (Flip Flop) Master Slave Flip Flop D Flip Flop, J K Flip Flop and T Flip Flop Combine that block to build multi bit storage a register FSMDesign:ExampleCounters

3 Level Sensitive D Latch SR latch requires careful design to ensure SR=11 never occurs D latch relieves designer of that burden Inserted inverter ensures R always opposite of S D C S R D latch Q D 1 0 C 1 0 D Q 1 S 0 1 R 0 Q 1 0 C Q D latch symbol

4 Solution: Ensure, Stabilize, Store X S Level-sensitive SR latch S1 Clk C Y Ensure Stage Never Happens SR=11 R Stabilize Stage WhenC=0 Stabilize SR and Use when C=1 R1 Store Stage Store bit Q

5 Problem with Level Sensitive D Latch D latch still has problem (as does SR latch) When C=1, through how many latches will a signal travel? Depends on for how long C=1 Clk_A signal may travel through multiple latches Clk_B signal may travel through fewer latches Hard to pick C that is just the right length Can we design bit storage that only stores a value on the rising edge of a clock signal? Y D1 Q1 D2 Q2 D3 Q3 D4 Q4 rising edges C1 C2 C3 C4 Clk Clk Clk_A Clk_B

6 FlipFlop Flop CoinFlip:Head/Tail (1/0) Latch have either one state 0 or 1 Flip Flop (Both Master/Slave) Flip State/Flop State

7 Master Slave D Flip Flop Flip flop:stores on clock edge, not level Two latches, output of first goes to input of second, master latch has inverted clock signal So master loaded when C=0, then servant when C=1 WhenCchangesfrom0to1 1, masterdisabled disabled, servantloadedwith value that was at D just before C changed i.e., value at D during rising edge of C D Dm Cm D latch master Qm Ds D flip-flop D latch Qs Q Cs Qs Q servant Clk D/Dm Cm Qm/Ds Cs Clk Qs

8 DFlip Flop Flop The triangle means clock input, edge triggered D Q D Q Q Symbol for rising-edge triggered D flip-flop Q Symbol for falling-edge triggered D flip-flop Internal design: Just invert servant clock rather than master rising edges falling edges Clk Clk

9 D Flip Flop Solves problem of not knowing through how many latches a signal travels when C=1 Signal travels through exactly one flip flop, for Clk_Aor Clk_B Why? Because on rising edge of Clk, all four flip flops are loaded simultaneously then all four no longer pay attention to their input, until the next rising edge. Doesn t matter how long Clkis 1. Y D1 Q1 D2 Q2 D3 Q3 D4 Q4 Clk Clk_A Clk_B Two latches inside each flip-flop

10 D Latch vs. D Flip Flop Latch is level sensitive: Stores D when C=1 Flip flop is edge triggered: Stores D when C changes from 0 to 1 Saying level sensitive latch, or edge triggered flipflop, is redundant Two types of flip flops rising or falling edge triggered. Comparing behavior of latch and flip flop: Clk 1 2 D Q (D latch) 7 8 Q (D flip-flop) 9 10

11 S R SR Latch S R Q Q S R Q *0* (Unpredictable) Q

12 Conventions The circuit is setmeans output = 1 The circuit is resetmeans output = 0 Flip flops flopshavetwooutputqandq output and Q Due to time related characteristic of the flip flop: Q t or Q: present state Q t+1 or Q + : next state

13 4TypeofFlipFlop Flop SRFlipFlop:Set/ResetFlipFlop Flop : Set/Reset Flop D Flip Flop : Data Flip Flop to store Bit J K Flip Flop: SR with use of the unavoidable SR=11 state to Toggle (All input values are useful) T Flip Flop: Toggle Flip Flop

14 J K Flip Flop The JKfli flip flop augments the behavior bh of fthe SR flip flop (J=Set, K=Reset) by interpreting the S = R = 1 condition as a "flip"" or toggle command. J C K JK FF from SR S R Q J K Q+ 0 0 Qt Qt Q + = K Q + JQ

15 Master Slave J K Flip Flop J S S Q C C K Q Q R R Q + = K Q + JQ

16 J K Flip Flop To synthesize a D flip flop, simply set K equal to the complement of J. The JK flip flop is a universal flip flop BecauseitcanbeconfiguredtoworkasanyFF can configured to as any T flip flop or D flip flop or SR flip flop. J=T K=T Q+ 0 0 Qt J=D K=D Q+ 0 0 Qt J=S K=R Q+ 0 0 Qt Qt 1 1 Qt 1 1 Qt

17 Toggle Flip Flop:TFFFlop: FF J=K=1, Q + =Q T J K Q JK FlipFlop T Q T FlipFlop C C

18 4 Types of Flip Flops S R Q+ J K Q+ 0 0 Qt 0 0 Qt U 1 1 Qt D Q T Q+ 0 Qt 1 Qt

19 CharacteristicEquations Adescriptionsofthenext of the next state statetabletable of a flip flop Constructing from the Karnaughmap forq t+1 intermsofthepresentstate the state and input

20 Characteristic tables The tables that we ve made so far are called characteristic tables. They show the next state Q(t+1) in terms of the current state Q(t) and the inputs. For simplicity, the control input C is not usually listed. Again, these tables don t indicate the positive edgetriggered behavior of the flip-flops that we ll be using. J K Q+ 0 0 Qt Qt D Q+ 0 0 T Q+ 0 Qt Qt

21 Characteristic equations We can also write characteristic equations, where the next state Q(t+1)is defined in terms of the current state Q(t) and inputs. J K Q+ 0 0 Qt Q + = K Q + JQ Q(t+1)=K Q(t)+JQ (t) KQ(t) + (t) Qt

22 Characteristic equations We can also write characteristic equations, where the next state Q(t+1) is defined in terms of the current state Q(t) and inputs. D Q T Q+ 0 Qt 1 Qt Q + =D Q(t+1) = D Q+= T Q+TQ = T Q Q(t+1) = T Q(t) + TQ (t) = T Q(t)

23 Characteristic equations Q SR Flip Flop Type SR JK Characteristic Equation Q + =S +R Q (SR=0) Q + =JQ +K Q +KQ D Q + =D Q + = S + R Q (SR=0) T Q + =TQ +T Q=T Q

24 Thanks

CS221: Digital Design. Dr. A. Sahu. Indian Institute of Technology Guwahati

CS221: Digital Design. Dr. A. Sahu. Indian Institute of Technology Guwahati CS221: Digital Design Counter&Registers Dr. A. Sahu DeptofComp.Sc.&Engg. Indian Institute of Technology Guwahati Outline Counter : Synchronous Vs Asynchronous Counter: Finite it State t Machine Mhi A register