Memorandum. Introduction. Design. Discussion. Contributions. Conclusion
|
|
- Darlene Flowers
- 6 years ago
- Views:
Transcription
1 Memorandum To: Dr. Randy Hoover From: Steffen Link Date: April 7, 2017 Subject: Lab 6: State Machine Stoplight Introduction The objective of the lab was to become more familair with a number of embedded programming concepts including timers, external interrupts, and state machines. To demonstrate this, a stoplight with a crosswalk was to be designed and implemented using the RedBoard and C. Design This lab involved using the Redboard GPIO pins, timer interrupt, and external interrupts 0 and 1 to drive a stoplight with a crosswalk. To implement this a state machine with eight states was used (see Appendix B). The first and fifth (where one light has just turned green) state both will not allow for a pedestrian to cause the stoplights to change to cross. If the light is in a state to let you cross, no change in state is issued. If the state is in state one or six (the light has been green for 2+ seconds), pressing one of the crosswalk buttons will cause the light to begin by stopping traffic and then allowing the pedestrian to cross the intersection. The light will either return to the previous state if less than 3 5 of the time allotted to the green light has passed or continue to let the other way go. When the light is in either state two or seven, a light is yellow and pressing the button to cross the street will trigger flashing lights after traffic has been brought to a full stop. When in state three (all red), the state machine will go to state four (flashing yellow / yeild to pedestrian) if an interrupt has been triggered and will either return to that state or not depending on a return flag set in the interrupt, elsewise it will continue to the other state. This was implemented using a packed struct for the state change variable, two external interrupts, a case statement and a timer interrupt. No data structure was used as it was not seen fit, along with previous expression of understanding of linked list (look at UART code in lab 4). Discussion This method used to implement the program works well, although it could be cleaned up to make the code more readable. The timing is not it was used for a simulation where the lights changed circa once every couple of seconds, so it would have no significant impact on accuracy. One of the important details of GCC discovered is that TIM0 OVF vect is a correct interrupt for Atmel Studio, but GCC does not recognize it. Finally this lab was a good chance to learn how to implement interrupts so that they do not need to be debounced. All together, the method of using state machines was shown to be a relativley easy way to implement a stoplight. Contributions Wrote Libraries Steffen Link Captures from lab Steffen Link State Machine Steffen Link Report - Design & Discussion Steffen Link - Introduction & Conclusion Steffen Link - Formatting & L A TEX Steffen Link Conclusion This lab helped demonstrate uses for interrupts related to timer and external interrupts, as well as how a well designed state machine can be simply implemented to make a simple process. 1
2 Appendices Appendix A Schematics Figure 1: Schematic for Stoplight circuit Appendix B State Machine Figure 2: State machine design for stoplight Table 1: State Transition Table for Stoplight State \ Inputs X000 X001 X010 X X Table 2: Where the inputs are Return N/S, timeout, interrupt 1, intterupt0 respectively 2
3 Appendix C Code C.1 main.c - Main Program 1 / // 2 F i l e : main. c 3 Author : S t e f f e n Link 4 Date : 2017/4/3 5 Lab : 5 6 D e s c r i p t i o n : Main f i l e running the program 7 / 8 // Define CPU freqeuncy 9 #d e f i n e F CPU UL // Inlcude block f o r data 12 #i n c l u d e <avr / i o. h> 13 #i n c l u d e <avr / i n t e r r u p t. h> 14 #i n c l u d e <u t i l / delay. h> 15 #i n c l u d e <s t d i o. h> 16 #i n c l u d e <s t d l i b. h> #d e f i n e rtime 1 / // 1 second f o r i n t e r s e c t i o n c l e a r 19 #d e f i n e ytime 2 / // 2 seconds 20 #d e f i n e gtime 3 / // 3 seconds // Struct f o r s e t t i n g the next s t a t e 23 typedef s t r u c t s t a t e 24 { 25 u i n t 8 t rets : 3 ; 26 u i n t 8 t i n t e r : 2 ; 27 u i n t 8 t nxts : 3 ; 28 u i n t 8 t l t S : 3 ; 29 } s t t e ; // A bunch o f g l o b a l v a r i a b l e s Yo 32 v o l a t i l e f l o a t seconds = gtime ; 33 v o l a t i l e f l o a t count = 0 ; 34 v o l a t i l e f l o a t oldcount = 0 ; 35 v o l a t i l e u i n t 8 t s t a t e = 0 ; 36 // Bit packed u i n t 8 t 37 // 0 b x x x x x x x x 38 // 0 b r s 2 r s 1 r s 0 i n t 0 i n t 1 s2 s1 s0 39 v o l a t i l e s t t e statechange = { 0, 0, 0, 0 } ; / 43 This f u n c t i o n i n i t i a l i z e d the i n t e r r u p t s and PORTD 44 / 45 void i n i t ( void ) 46 { 47 s e i ( ) ; 48 DDRD = 0 b ; 49 TCCR0B = 0x05 ; // Set timer1 p r e s c a l e to f o s c / TIMSK0 = 0x01 ; // Set i n t e r r u p t f o r overflow on Timer0 51 EIMSK = 0x03 ; 52 EICRA = 0x0F ; 53 PCMSK0 = 0x0C ; 54 3
4 55 } / 59 This f u n c t i o n i s the main f u n c t i o n f o r the program to be f l a s h e d 60 / 61 i n t main ( void ) 62 { 63 i n i t ( ) ; // While loop with s t a t e machine i n s i d e with corresponding s t a t e s 66 while ( 1 ) 67 { 68 switch ( s t a t e & 0x07 ) 69 { 70 case 0 : 71 PORTD = 0 b ; 72 seconds = rtime 2 ; 73 statechange. nxts = 1 ; 74 statechange. l t S = 3 ; 75 break ; 76 case 1 : 77 PORTD = 0 b ; 78 count = oldcount ; 79 oldcount = 0 ; 80 seconds = gtime ; 81 statechange. nxts = 2 ; 82 statechange. l t S = 0 ; 83 break ; 84 case 2 : 85 PORTD = 0 b ; 86 seconds = ytime ; 87 statechange. nxts = 3 ; 88 statechange. l t S = 1 ; 89 break ; 90 case 3 : // handles crosswalk and proper r e t u r n i n g 91 PORTD = 0 b ; 92 seconds = rtime ; 93 i f ( ( statechange. i n t e r )!= 0) // checking f o r i n t e r r u p t s 94 { 95 i f ( statechange. l t S!= 3) 96 statechange. nxts = 4 ; 97 e l s e 98 { // c l e a r s i n t e r r u p t s 99 statechange. i n t e r = 0 ; 100 statechange. nxts = statechange. rets ; 101 } 102 } e l s e // r e t u r n s to proper p l a c e 103 { 104 i f ( statechange. l t S == 1) 105 statechange. nxts = 5 ; 106 e l s e 107 statechange. nxts = 0 ; 108 } 109 break ; 110 case 5 : 4
5 111 PORTD = 0 b ; 112 seconds = rtime 2 ; 113 statechange. nxts = 6 ; 114 statechange. l t S = 3 ; 115 break ; 116 case 6 : 117 count = oldcount ; 118 oldcount = 0 ; 119 PORTD = 0 b ; 120 seconds = gtime ; 121 statechange. nxts = 7 ; 122 statechange. l t S = 5 ; 123 break ; 124 case 7 : 125 PORTD = 0 b ; 126 seconds = ytime ; 127 statechange. nxts = 3 ; 128 statechange. l t S = 6 ; 129 break ; 130 case 4 : 131 PORTD = 0 b ; 132 seconds = 0 ; 133 c l i ( ) ; 134 f o r ( i n t i = 0 ; i < 1 0 ; i ++) // Hard coded f l a s h i n g l i g h t s 135 { 136 delay ms (500) ; 137 PORTD ˆ= 0 b ; 138 } 139 s e i ( ) ; 140 seconds = 0 ; 141 PORTD = 0 b ; 142 seconds = rtime ; 143 statechange. nxts = 3 ; 144 statechange. l t S = 3 ; 145 break ; 146 d e f a u l t : 147 PORTD = 0xF9 ; 148 } 149 TCNT0 = 0 ; 150 while ( count < seconds ) ; 151 count = 0 ; 152 s t a t e = statechange. nxts ; 153 } 154 return 1 ; 155 } / 159 This f u n c t i o n increments count everytime TIMER0 r o l e s over ( every 61ms) 160 / 161 ISR ( TIMER0 OVF vect ) 162 { 163 count++; 164 } / 5
6 167 Handles one d i r e c t i o n o f i n t e r r u p t s 168 / 169 ISR ( INT0 vect ) 170 { 171 i f ( s t a t e < 8 && s t a t e > 5) // Checks i f i t s in a worth while s t a t e to do t h i n g s 172 { 173 i f ( s t a t e == 6 && count < 0. 6 ( gtime+rtime 2) ) 174 { 175 statechange. rets = 6 ; 176 statechange. nxts = 7 ; 177 statechange. i n t e r = 1 ; 178 oldcount = count ; 179 } e l s e 180 { 181 statechange. rets = 0 ; 182 statechange. nxts = statechange. l t S == 6? 3 : 6 ; 183 statechange. i n t e r = 1 ; 184 oldcount = 0 ; 185 } 186 i f ( s t a t e == 6) seconds = 0 ; 187 } e l s e i f ( s t a t e == 3) // a l l red s t a t e 188 { 189 statechange. rets = statechange. l t S == 1? 5 : 0 ; 190 statechange. nxts = 4 ; 191 statechange. i n t e r = 1 ; 192 } 193 } / 196 This f u n c t i o n handles the other d i r e c t i o n o f i n t e r r u p t 197 / 198 ISR ( INT1 vect ) 199 { 200 i f ( s t a t e < 3 && s t a t e > 0) // Checks i f i t s in a worth while s t a t e to do t h i n g s 201 { 202 i f ( s t a t e == 1 && count < 0. 6 ( gtime+rtime 2) ) 203 { 204 statechange. rets = 1 ; 205 statechange. nxts = 2 ; 206 statechange. i n t e r = 2 ; 207 oldcount = count ; 208 } e l s e 209 { 210 statechange. rets = 5 ; 211 statechange. nxts = s t a t e +1; 212 statechange. i n t e r = 2 ; 213 oldcount = 0 ; 214 } 215 i f ( s t a t e == 1) seconds = 0 ; 216 } e l s e i f ( s t a t e == 3) // a l l red s t a t e 217 { 218 statechange. rets = statechange. l t S == 1? 5 : 0 ; 219 statechange. nxts = 4 ; 220 statechange. i n t e r = 2 ; 221 } 222 } 6
7 Appendix D Makefile 1 # AVR Makefile 2 # 3 # Made by S t e f f e n Link 4 5 TRGT = main 6 7 #Source f i l e s 8 SRC = $ ( wildcard. c ) 9 10 # The OBJ macro i s b u i l t from the SRC macro 11 OBJ = $ (SRC :. c =.o ) # Macros f o r the compiler, l i n k e r, and compiler o p t i o n s 14 CC = avr gcc GCC = $ (CC) 16 LINK = $ (CC) 17 MCU = atmega328p 18 CFLAGS = mmcu=$ (MCU) O1 std=c11 #Optimization f o r the delay 19 CXXFLAGS = $ (CFLAGS) 20 DFLAGS = mmcu=$ (MCU) DDEBUG g Og s t d=c PHONY: c l e a n # A macro f o r compiling and f l a s h i n g 25 f u l l : a l l f l a s h # Basic compile 28 a l l : $ (OBJ) 29 $ (GCC) o $ (TRGT) $ (OBJ) $ (CFLAGS) # Add a c l e a n t a r g e t to allow r e b u i l d s 32 c l e a n : 33 rm r f $ (TRGT). o. d. hex $ (OBJ) # Debug compilation 36 debug : CXXFLAGS= $ (DFLAGS) 37 debug : CFLAGS = $ (DFLAGS) 38 debug : $ (OBJ) 39 $ (GCC) o TRGT $ (OBJ) $ (DFLAGS) 40 debug : f l a s h # Remake the p r o j e c t 43 remake : c l e a n 44 remake : a l l # Remake the p r o j e c t w/ debug f l a g s 47 dremake : c l e a n 48 dremake : debug # Flash the AVR 51 f l a s h : 52 avr objcopy $ (TRGT) $ (TRGT). hex 53 avrdude p m328p c arduino b P /dev/ttyusb0 U f l a s h :w: $ (TRGT). hex 7
Memorandum. Introduction. Design. Discussion. Conclusion
Memorandum To: Dr. Randy Hoover From: Steffen Link Date: May 1, 2017 Subject: Lab 7: Proportional Motor Control Introduction The objective of the lab was to become more familair with the rest of the core
More information1 SIMPLE PENDULUM 1 L (1.1)
1 SIMPLE PENDULUM 1 October 15, 2016 1 Simple Pendulum IMPORTANT: You must work through the derivation required for this assignment before you turn up to the laboratory. You are also expected to know what
More information1 SIMPLE PENDULUM 1 L (1.1)
1 SIMPLE PENDULUM 1 October 13, 2015 1 Simple Pendulum IMPORTANT: You must work through the derivation required for this assignment before you turn up to the laboratory. You are also expected to know what
More informationAssembly Programming through Arduino
1 Assembly Programming through Arduino G V V Sharma Contents 1 Components 1 2 Seven Segment Display 1 2.1 Hardware Setup....... 1 2.2 Software Setup........ 2 2.3 Controlling the Display... 2 3 Display
More informationLaboratory Exercise 4 SIMPLE PENDULUM
Simple Pendulum IMPORTANT: You must work through the derivation required for this assignment before you turn up to the laboratory. You are also expected to know what the arithmetic average and standard
More informationMicrocontroller VU
182.694 Microcontroller VU Martin Perner SS 2017 Featuring Today: Assembler Programming Weekly Training Objective Already done 1.2 Board test 2.1.1 Assembler demo program 2.1.2 Makefile 2.2.1 Logical operations
More informationENGG 1203 Tutorial _03 Laboratory 3 Build a ball counter. Lab 3. Lab 3 Gate Timing. Lab 3 Steps in designing a State Machine. Timing diagram of a DFF
ENGG 1203 Tutorial _03 Laboratory 3 Build a ball counter Timing diagram of a DFF Lab 3 Gate Timing difference timing for difference kind of gate, cost dependence (1) Setup Time = t2-t1 (2) Propagation
More informationEXPERIMENT Traffic Light Controller
11.1 Objectives EXPERIMENT 11 11. Traffic Light Controller Practice on the design of clocked sequential circuits. Applications of sequential circuits. 11.2 Overview In this lab you are going to develop
More informationLABORATORY MANUAL MICROPROCESSOR AND MICROCONTROLLER
LABORATORY MANUAL S u b j e c t : MICROPROCESSOR AND MICROCONTROLLER TE (E lectr onics) ( S e m V ) 1 I n d e x Serial No T i tl e P a g e N o M i c r o p r o c e s s o r 8 0 8 5 1 8 Bit Addition by Direct
More informationECE Final Exam: Name Solution
ECE 376 - Final Exam: Name Solution December 10, 2018 1) Binary Outputs: Design a circuit which allows a PIC to turn on and off a 40mW LED at 10mA: On = 10mA Off = 0mA Assume the LED characteristics are:
More informationLab #10: Design of Finite State Machines
Lab #10: Design of Finite State Machines ECE/COE 0501 Date of Experiment: 3/1/2017 Report Written: 3/4/2017 Submission Date: 3/15/2017 Nicholas Haver nicholas.haver@pitt.edu 1 H a v e r PURPOSE The purpose
More informationOperating systems and concurrency B03
Operating systems and concurrency B03 David Kendall Northumbria University David Kendall (Northumbria University) Operating systems and concurrency B03 1 / 13 Introduction A key function of OS is interrupt
More informationPART TEMP RANGE PIN-PACKAGE
9-0850; Rev 4; 6/0 Ω μ INT INT μ PART TEMP RANGE PIN-PACKAGE MAX7359ETG+ -40 C to +85 C 24 TQFN-EP* MAX7359EWA+ -40 C to +85 C 25 WLP * TOP VIEW AD0 GND IC COL0 8 7 6 5 4 3 INPUT +62V TO +36V V CC MAX7359
More informationAssignment 6: A/D-Converters and PID Controllers
Assignment 6: A/D-Converters and PID Controllers 1DT056: Programming Embedded Systems Uppsala University March 4th, 2012 You can achieve a maximum number of 20 points in this assignment. 12 out of the
More informationECE3510 Lab #5 PID Control
ECE3510 Lab #5 ID Control Objectives The objective of this lab is to study basic design issues for proportionalintegral-derivative control laws. Emphasis is placed on transient responses and steady-state
More informationSimplify the following Boolean expressions and minimize the number of literals:
Boolean Algebra Task 1 Simplify the following Boolean expressions and minimize the number of literals: 1.1 1.2 1.3 Task 2 Convert the following expressions into sum of products and product of sums: 2.1
More informationAppendix D Nomenclature. Abstract
Appendix D Abstract This appendix presents all the common used abbreviations and symbols. The items are listed in groups of units, e.g. [V], [A] and so forth. Instantaneous values are presented with lower
More informationELECTROMAGNETIC FAULT INJECTION: TOWARDS A FAULT MODEL ON A 32-BIT MICROCONTROLLER
ELECTROMAGNETIC FAULT INJECTION: TOWARDS A FAULT MODEL ON A 32-BIT MICROCONTROLLER Nicolas Moro 1,3, Amine Dehbaoui 2, Karine Heydemann 3, Bruno Robisson 1, Emmanuelle Encrenaz 3 1 CEA Commissariat à l
More informationSynchronous Sequential Circuit Design. Digital Computer Design
Synchronous Sequential Circuit Design Digital Computer Design Races and Instability Combinational logic has no cyclic paths and no races If inputs are applied to combinational logic, the outputs will always
More informationState Machines ELCTEC-131
State Machines ELCTEC-131 Switch Debouncer A digital circuit that is used to remove the mechanical bounce from a switch contact. When a switch is closed, the contacts bounce from open to closed to cause
More informationLab 3 Revisited. Zener diodes IAP 2008 Lecture 4 1
Lab 3 Revisited Zener diodes R C 6.091 IAP 2008 Lecture 4 1 Lab 3 Revisited +15 Voltage regulators 555 timers 270 1N758 0.1uf 5K pot V+ V- 2N2222 0.1uf V o. V CC V Vin s = 5 V Vc V c Vs 1 e t = RC Threshold
More informationConstruction of the Caltech Ch 6 CP-FTMW Spectrometer
Construction of the Caltech Ch 6 CP-FTMW Spectrometer P. Brandon Carroll Abstract This is meant to be a guide to the construction and implementation of Arduino control of an AD 9914 DDS evaluation board
More informationHowto make an Arduino fast enough to... Willem Maes
Howto make an Arduino fast enough to... Willem Maes May 1, 2018 0.1 Introduction Most problems student face when using the Arduino in their projects seems to be the speed. There seems to be a general opinion
More informationExperiment 8: Capacitance and the Oscilloscope
Experiment 8: Capacitance and the Oscilloscope Nate Saffold nas2173@columbia.edu Office Hour: Mondays, 5:30PM-6:30PM @ Pupin 1216 INTRO TO EXPERIMENTAL PHYS-LAB 1493/1494/2699 Outline Capacitance: Capacitor
More informationLatches. October 13, 2003 Latches 1
Latches The second part of CS231 focuses on sequential circuits, where we add memory to the hardware that we ve already seen. Our schedule will be very similar to before: We first show how primitive memory
More informationT4 TIMER - PROJECT DESCRIPTION - rev. 5.10
1. Display Logic A. When displaying in HH:MM, it will not be obvious from the display that the timer is counting, the 4 dots at the bottom of the display chase from left to right to indicate its counting
More informationEECS 579: Logic and Fault Simulation. Simulation
EECS 579: Logic and Fault Simulation Simulation: Use of computer software models to verify correctness Fault Simulation: Use of simulation for fault analysis and ATPG Circuit description Input data for
More informationDigital Design through Arduino
1 Digital Design through Arduino G V V Sharma Contents 1 Display Control through Hardware 1 1.1 Components......... 1 1.2 Powering the Display.... 1 1.3 Controlling the Display... 2 2 Display Control through
More informationProgramsystemkonstruktion med C++: Övning 1. Karl Palmskog Translated by: Siavash Soleimanifard. September 2011
Programsystemkonstruktion med C++: Övning 1 Karl Palmskog palmskog@kth.se Translated by: Siavash Soleimanifard September 2011 Programuppbyggnad Klassens uppbyggnad A C++ class consists of a declaration
More informationProgrammable Timer High-Performance Silicon-Gate CMOS
TECNICAL DATA Programmable Timer igh-performance Silicon-ate CMOS The IW1B programmable timer consists of a 16-stage binary counter, an oscillator that is controlled by external R-C components (2 resistors
More informationSynchronous Sequential Circuit Design. Dr. Ehab A. H. AL-Hialy Page 1
Synchronous Sequential Circuit Design Dr. Ehab A. H. AL-Hialy Page Motivation Analysis of a few simple circuits Generalizes to Synchronous Sequential Circuits (SSC) Outputs are Function of State (and Inputs)
More informationCONSERVATION OF ENERGY PHYSICS 221: CLASSICAL PHYSICS I. Part 1 Conservation of Kinetic Energy: Elastic Collisions Introduction
CONSERVATION OF ENERGY PHYSICS 221: CLASSICAL PHYSICS I Name: Lab Date: Due Date: Lab Partner(s): Part 1 Conservation of Kinetic Energy: Elastic Collisions Introduction Momentum is always conserved in
More informationBCD-TO-DECIMAL DECODER HIGH-VOLTAGE SILICON-GATE CMOS IW4028B TECHNICAL DATA
TECHNICAL DATA BCD-TO-DECIMAL DECODER HIGH-OLTAGE SILICON-GATE CMOS IW4028B The IW4028B types are BCD-to-decimal or binary-tooctal decoders consisting of buffering on all 4 inputs, decoding-logic gates,
More informationCSCI 2150 Intro to State Machines
CSCI 2150 Intro to State Machines Topic: Now that we've created flip-flops, let's make stuff with them Reading: igital Fundamentals sections 6.11 and 9.4 (ignore the JK flip-flop stuff) States Up until
More informationEE 354 Fall 2013 Lecture 10 The Sampling Process and Evaluation of Difference Equations
EE 354 Fall 203 Lecture 0 The Sampling Process and Evaluation of Difference Equations Digital Signal Processing (DSP) is centered around the idea that you can convert an analog signal to a digital signal
More information,- # (%& ( = 0,% % <,( #, $ <<,( > 0,% #% ( - + % ,'3-% & '% #% <,( #, $ <<,(,9 (% +('$ %(- $'$ & " ( (- +' $%(& 2,#. = '%% ($ (- +' $ '%("
FEATURES!" #$$ % %&' % '( $ %( )$*++$ '(% $ *++$ %(%,- *(% (./ *( #'% # *( 0% ( *( % #$$ *( '( + 2' %( $ '( 2! '3 ((&!( *( 4 '3.%" / '3 3.% 7" 28" 9' 9,*: $ 9,*: $% (+'( / *(.( # ( 2(- %3 # $((% # ;' '3$-,(
More informationComputer Architecture
Computer Architecture QtSpim, a Mips simulator S. Coudert and R. Pacalet January 4, 2018..................... Memory Mapping 0xFFFF000C 0xFFFF0008 0xFFFF0004 0xffff0000 0x90000000 0x80000000 0x7ffff4d4
More informationImplementing Absolute Addressing in a Motorola Processor (DRAFT)
Implementing Absolute Addressing in a Motorola 68000 Processor (DRAFT) Dylan Leigh (s3017239) 2009 This project involved the further development of a limited 68000 processor core, developed by Dylan Leigh
More informationENGG 1203 Tutorial_9 - Review. Boolean Algebra. Simplifying Logic Circuits. Combinational Logic. 1. Combinational & Sequential Logic
ENGG 1203 Tutorial_9 - Review Boolean Algebra 1. Combinational & Sequential Logic 2. Computer Systems 3. Electronic Circuits 4. Signals, Systems, and Control Remark : Multiple Choice Questions : ** Check
More informationwith Manual Reset and Watchdog Timer
General Description The MAX6821 MAX6825 are low-voltage microprocessor (µp) supervisory circuits that combine voltage monitoring, watchdog timer, and manual reset input functions in a 5-pin SOT23 package.
More information74LS195 SN74LS195AD LOW POWER SCHOTTKY
The SN74LS95A is a high speed 4-Bit Shift Register offering typical shift frequencies of 39 MHz. It is useful for a wide variety of register and counting applications. It utilizes the Schottky diode clamped
More informationEnumeration and generation of all constitutional alkane isomers of methane to icosane using recursive generation and a modified Morgan s algorithm
The C n H 2n+2 challenge Zürich, November 21st 2015 Enumeration and generation of all constitutional alkane isomers of methane to icosane using recursive generation and a modified Morgan s algorithm Andreas
More informationFinite State Machine (FSM)
Finite State Machine (FSM) Consists of: State register Stores current state Loads next state at clock edge Combinational logic Computes the next state Computes the outputs S S Next State CLK Current State
More informationSN74LS151D LOW POWER SCHOTTKY
The TTL/MSI SN74LS5 is a high speed 8-input Digital Multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. The LS5 can be used as a universal function
More informationEmbedded Systems 2. REVIEW: Actor models. A system is a function that accepts an input signal and yields an output signal.
Embedded Systems 2 REVIEW: Actor models A system is a function that accepts an input signal and yields an output signal. The domain and range of the system function are sets of signals, which themselves
More informationLABORATORY MANUAL MICROPROCESSORS AND MICROCONTROLLERS. S.E (I.T) ( S e m. IV)
LABORATORY MANUAL MICROPROCESSORS AND MICROCONTROLLERS S.E (I.T) ( S e m. IV) 1 I n d e x Serial No. T i tl e P a g e N o. 1 8 bit addition with carry 3 2 16 bit addition with carry 5 3 8 bit multiplication
More information! BASCO CO AVR AVR " #$
ASCOM AVR AVR BA 10.. www.eca.ir 1 4... 5... 7... 9... 9... avr AVR.1-2 11... atmega16.1-1-2 14... ATMEGA8.2-2 15... bascom avr 15... bascom.1-3 16... file.1-1-3 1. 2. 3. 16... edit.2-1-3 17...program.3-1-3
More informationLogic Design II (17.342) Spring Lecture Outline
Logic Design II (17.342) Spring 2012 Lecture Outline Class # 10 April 12, 2012 Dohn Bowden 1 Today s Lecture First half of the class Circuits for Arithmetic Operations Chapter 18 Should finish at least
More informationLearning to work with SPS Structured Beam. (June 14-21, 2004) Lev Uvarov
Learning to work with SPS Structured Beam (June 14-21, 2004) Lev Uvarov Structured Test Beam at SPS From Minutes of SPS Users Meeting, Thursday, 17-Jun-2004: Beam conditions for SPS 25ns run (Monday, June
More informationFPGA Resource Utilization Estimates for NI crio LabVIEW FPGA Version: 8.6 NI-RIO Version: 3.0 Date: 8/5/2008
FPGA Resource Utilization Estimates for NI crio-9104 LabVIEW FPGA Version: 8.6 NI-RIO Version: 3.0 Date: 8/5/2008 Note: The numbers presented in this document are estimates. Actual resource usage for your
More informationNumbers and Arithmetic
Numbers and Arithmetic See: P&H Chapter 2.4 2.6, 3.2, C.5 C.6 Hakim Weatherspoon CS 3410, Spring 2013 Computer Science Cornell University Big Picture: Building a Processor memory inst register file alu
More informationSignalized Intersections
Signalized Intersections Kelly Pitera October 23, 2009 Topics to be Covered Introduction/Definitions D/D/1 Queueing Phasing and Timing Plan Level of Service (LOS) Signal Optimization Conflicting Operational
More informationEXPERIMENT Bit Binary Sequential Multiplier
12.1 Objectives EXPERIMENT 12 12. -Bit Binary Sequential Multiplier Introduction of large digital system design, i.e. data path and control path. To apply the above concepts to the design of a sequential
More informationTopics for Lecture #9. Button input processor
opics for Lecture # Reminder: midterm examination # next uesday starting at :0am. Examples of small state machines simultaneous button push detector (continued) button push processor pulse stretcher General
More informationFrom Sequential Circuits to Real Computers
1 / 36 From Sequential Circuits to Real Computers Lecturer: Guillaume Beslon Original Author: Lionel Morel Computer Science and Information Technologies - INSA Lyon Fall 2017 2 / 36 Introduction What we
More information14.1. Unit 14. State Machine Design
4. Unit 4 State Machine Design 4.2 Outcomes I can create a state diagram to solve a sequential problem I can implement a working state machine given a state diagram STATE MACHINES OVERVIEW 4.3 4.4 Review
More informationExperiment 81 - Design of a Feedback Control System
Experiment 81 - Design of a Feedback Control System 201139030 (Group 44) ELEC273 May 9, 2016 Abstract This report discussed the establishment of open-loop system using FOPDT medel which is usually used
More informationMM74C922 MM74C Key Encoder 20-Key Encoder
MM74C922 MM74C923 16-Key Encoder 20-Key Encoder General Description The MM74C922 and MM74C923 CMOS key encoders provide all the necessary logic to fully encode an array of SPST switches. The keyboard scan
More informationFPGA Resource Utilization Estimates for NI PXI-7854R. LabVIEW FPGA Version: 8.6 NI-RIO Version: 3.0 Date: 8/5/2008
FPGA Resource Utilization Estimates for NI PXI-7854R LabVIEW FPGA Version: 8.6 NI-RIO Version: 3.0 Date: 8/5/2008 Note: The numbers presented in this document are estimates. Actual resource usage for your
More informationNumbers and Arithmetic
Numbers and Arithmetic See: P&H Chapter 2.4 2.6, 3.2, C.5 C.6 Hakim Weatherspoon CS 3410, Spring 2013 Computer Science Cornell University Big Picture: Building a Processor memory inst register file alu
More informationOverview. Multiplexor. cs281: Introduction to Computer Systems Lab02 Basic Combinational Circuits: The Mux and the Adder
cs281: Introduction to Computer Systems Lab02 Basic Combinational Circuits: The Mux and the Adder Overview The objective of this lab is to understand two basic combinational circuits the multiplexor and
More informationWEBER ROAD RESIDENTIAL DEVELOPMENT Single Family Residential Project
WEBER ROAD RESIDENTIAL DEVELOPMENT Single Family Residential Project WEBER ROAD RESIDENTIAL DEVELOPMENT TRAFFIC IMPACT STUDY TABLE OF CONTENTS 1.0 Executive Summary Page 2.0 Introduction 2.1 DEVELOPMENT
More informationWTR-S4 Module User Manual WTR-S4 MODULE
WTR-S MODULE.PRODUCT FEATURES....FUTION DESCRIPTIONS....RELATIONSHIP OF FLASH MEMORY CAPACITY AND RECORDING DURATION....APPLICATION DIAGRAM....PACKAGE SKETCH MAP....PIN DESCRIPTIONS.... SAMPLING RATE SETTINGS....PARAMETERS...
More informationCh 9. Sequential Logic Technologies. IX - Sequential Logic Technology Contemporary Logic Design 1
Ch 9. Sequential Logic Technologies Technology Contemporary Logic Design Overview Basic Sequential Logic Components FSM Design with Counters FSM Design with Programmable Logic FSM Design with More Sophisticated
More informationSynchronous 4 Bit Counters; Binary, Direct Reset
Synchronous 4 Bit Counters; Binary, Direct Reset This synchronous, presettable counter features an internal carry look-ahead for application in high-speed counting designs. Synchronous operation is provided
More informationPhotosynthesis: Limiting Factors
Name: Date: Period: Photosynthesis: Limiting Factors Purpose: 1. To determine the effect of temperature, light intensity, and light color on the rate of photosynthesis. 2. To calculate the rate of photosynthesis
More information(d) describe the action of a 555 monostable timer and then use the equation T = 1.1 RC, where T is the pulse duration
Chapter 1 - Timing Circuits GCSE Electronics Component 2: Application of Electronics Timing Circuits Learners should be able to: (a) describe how a RC network can produce a time delay (b) describe how
More informationPotential Issues with Advance Preemption. Roelof Engelbrecht Texas Transportation Institute
1 Potential Issues with Advance Preemption Roelof Engelbrecht Texas Transportation Institute 2 Rail Preemption Designed to transfer right-of-way to the track movement and clear vehicles off the track(s)
More informationStop Watch (System Controller Approach)
Stop Watch (System Controller Approach) Problem Design a stop watch that can measure times taken for two events Inputs CLK = 6 Hz RESET: Asynchronously reset everything X: comes from push button First
More information74F193 Up/Down Binary Counter with Separate Up/Down Clocks
April 1988 Revised September 2000 Up/Down Binary Counter with Separate Up/Down Clocks General Description The is an up/down modulo-16 binary counter. Separate Count Up and Count Down Clocks are used, and
More information74F174 Hex D-Type Flip-Flop with Master Reset
74F174 Hex D-Type Flip-Flop with Master Reset General Description The 74F174 is a high-speed hex D-type flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information
More informationDeep Algebra Projects: Algebra 1 / Algebra 2 Go with the Flow
Deep Algebra Projects: Algebra 1 / Algebra 2 Go with the Flow Topics Solving systems of linear equations (numerically and algebraically) Dependent and independent systems of equations; free variables Mathematical
More informationExperiment 4. RC Circuits. Observe and qualitatively describe the charging and discharging (decay) of the voltage on a capacitor.
Experiment 4 RC Circuits 4.1 Objectives Observe and qualitatively describe the charging and discharging (decay) of the voltage on a capacitor. Graphically determine the time constant τ for the decay. 4.2
More informationChapter 3. Chapter 3 :: Topics. Introduction. Sequential Circuits
Chapter 3 Chapter 3 :: Topics igital esign and Computer Architecture, 2 nd Edition avid Money Harris and Sarah L. Harris Introduction Latches and Flip Flops Synchronous Logic esign Finite State Machines
More informationWhere, τ is in seconds, R is in ohms and C in Farads. Objective of The Experiment
Introduction The famous multivibrator circuit was first introduced in a publication by Henri Abraham and Eugene Bloch in 1919. Multivibrators are electronic circuits designed for the purpose of applying
More informationOutline Fault Simulation
K.T. Tim Cheng, 4_fault_sim, v. Outline Fault Simulation Applications of fault simulation Fault coverage vs product quality Fault simulation scenarios Fault simulation algorithms Fault sampling K.T. Tim
More informationLinear Momentum and Kinetic Energy
Linear Momentum and Kinetic Energy Introduction The object of this experiment is to investigate the conservation of linear momentum and the conservation of kinetic energy in elastic collisions. We will
More informationDigital Design through Pi
1 Digital Design through Pi G V V Sharma Contents 1 Display Control through Hardware 1 1.1 Components......... 1 1.2 Software Setup........ 1 1.3 Powering the Display.... 1 1.4 Controlling the Display...
More informationCSE370: Introduction to Digital Design
CSE370: Introduction to Digital Design Course staff Gaetano Borriello, Brian DeRenzi, Firat Kiyak Course web www.cs.washington.edu/370/ Make sure to subscribe to class mailing list (cse370@cs) Course text
More informationCHAPTER 3. CAPACITY OF SIGNALIZED INTERSECTIONS
CHAPTER 3. CAPACITY OF SIGNALIZED INTERSECTIONS 1. Overview In this chapter we explore the models on which the HCM capacity analysis method for signalized intersections are based. While the method has
More informationS Sapling INSTALLATION MANUAL FOR FIELD SELECTABLE ANALOG CLOCKS SAA SERIES SPECIFICATIONS. advanced time and control systems
INSTALLATION MANUAL FOR FIELD SELECTABLE ANALOG CLOCKS SAA SERIES SPECIFICATIONS Time base: 60 Hz (3-wire system) Quartz (2-wire system) Power input: 85 135 VAC / 60 Hz 7 28 VAC / 60 Hz Current consumption:
More informationSecured Series Front End Reader Installation Instructions Proximity Reader (ProxPro, ProxPro w/keypad, MiniPro, Thinline II)
Secured Series Front End Reader Installation Instructions Proximity Reader (ProxPro, ProxPro w/keypad, MiniPro, Thinline II) Installation Procedure: Step 1: Check the Packing List Step 2: Mount the Proximity
More informationFundamentals of Computer Systems
Fundamentals of Computer Systems Sequential Logic Stephen A. Edwards Columbia University Summer 2017 State-Holding Elements Bistable Elements S Latch Latch Positive-Edge-Triggered Flip-Flop Flip-Flop with
More informationRC Circuits. 1. Designing a time delay circuit. Introduction. In this lab you will explore RC circuits. Introduction
Name Date Time to Complete h m Partner Course/ Section / Grade RC Circuits Introduction In this lab you will explore RC circuits. 1. Designing a time delay circuit Introduction You will begin your exploration
More informationCOE 202: Digital Logic Design Sequential Circuits Part 3. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:
COE 202: Digital Logic Design Sequential Circuits Part 3 Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324 Objectives State Reduction and Assignment Design of Synchronous Sequential
More informationWritten reexam with solutions for IE1204/5 Digital Design Monday 14/
Written reexam with solutions for IE204/5 Digital Design Monday 4/3 206 4.-8. General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 08-7904487 Exam text does not have to be returned
More informationSN74LS153D 74LS153 LOW POWER SCHOTTKY
74LS153 The LSTTL/MSI SN74LS153 is a very high speed Dual 4-Input Multiplexer with common select inputs and individual enable inputs for each section. It can select two bits of data from four sources.
More informationChapter 3. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 3 <1>
Chapter 3 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 3 Chapter 3 :: Topics Introduction Latches and Flip-Flops Synchronous Logic Design Finite
More informationINTRODUCTION. This is not a full c-programming course. It is not even a full 'Java to c' programming course.
C PROGRAMMING 1 INTRODUCTION This is not a full c-programming course. It is not even a full 'Java to c' programming course. 2 LITTERATURE 3. 1 FOR C-PROGRAMMING The C Programming Language (Kernighan and
More informationWhat are binary numbers and why do we use them? BINARY NUMBERS. Converting decimal numbers to binary numbers
What are binary numbers and why do we use them? BINARY NUMBERS Converting decimal numbers to binary numbers The number system we commonly use is decimal numbers, also known as Base 10. Ones, tens, hundreds,
More informationAN1755 APPLICATION NOTE
AN1755 APPLICATION NOTE A HIGH RESOLUTION / PRECISION THERMOMETER USING ST7 AND NE555 INTRODUCTION The goal of this application note is to present a realistic example of a thermometer using an ST7 and
More informationMEDE3500 Lab Guide Lab session: Electromagnetic Field
MEDE3500 Lab Guide Lab session: Electromagnetic Field 2016-2017 Department of Electrical and Electronic Engineering The University of Hong Kong Location: CYC-102/CB-102 Course Lecturer: Dr. Philip W. T.
More informationMOSIS REPORT. Spring MOSIS Report 1. MOSIS Report 2. MOSIS Report 3
MOSIS REPORT Spring 2010 MOSIS Report 1 MOSIS Report 2 MOSIS Report 3 MOSIS Report 1 Design of 4-bit counter using J-K flip flop I. Objective The purpose of this project is to design one 4-bit counter
More informationTFT Proto 5 TFT. 262K colors
TFT Proto TFT K colors Introduction to TFT Proto Figure : TFT Proto board TFT Proto enables you to easily add a touchscreen display to your design, whether it s a prototype or a final product. It carries
More informationNTE74HC299 Integrated Circuit TTL High Speed CMOS, 8 Bit Universal Shift Register with 3 State Output
NTE74HC299 Integrated Circuit TTL High Speed CMOS, 8 Bit Universal Shift Register with 3 State Output Description: The NTE74HC299 is an 8 bit shift/storage register with three state bus interface capability
More informationQuiz 2 Solutions Room 10 Evans Hall, 2:10pm Tuesday April 2 (Open Katz only, Calculators OK, 1hr 20mins)
UNIVERSITY OF CALIFORNIA AT BERKELEY ERKELEY DAVIS IRVINE LOS ANGELES RIVERSIDE SAN DIEGO SAN FRANCISCO SANTA BARBARA SANTA CRUZ Department of Electrical Engineering and Computer Sciences Quiz 2 Solutions
More informationSystem Specification of a DES Cipher Chip
Center for Embedded Computer Systems University of California, Irvine System Specification of a DES Cipher Chip Weiwei Chen, Rainer Dömer Technical Report CECS-08-01 January 28, 2008 Center for Embedded
More informationFormal Verification of Mobile Network Protocols
Dipartimento di Informatica, Università di Pisa, Italy milazzo@di.unipi.it Pisa April 26, 2005 Introduction Modelling Systems Specifications Examples Algorithms Introduction Design validation ensuring
More informationmith College Computer Science CSC270 Spring 16 Circuits and Systems Lecture Notes Week 2 Dominique Thiébaut
mith College Computer Science CSC270 Spring 16 Circuits and Systems Lecture Notes Week 2 Dominique Thiébaut dthiebaut@smith.edu Lab 1: Lessons Learned a0 b0 adder c0 S0 a1 b1 a0 b0 adder adder S1 S0 a31
More informationINTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC6 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC6 74HC/HCT/HCU/HCMOS Logic Package Information The IC6 74HC/HCT/HCU/HCMOS
More information