EECS150 - Digital Design Lecture 2 - Combinational Logic Review and FPGAs. General Model for Synchronous Systems

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1 EECS150 - igital esign Lecture 2 - Combinational Logic Review and FPGAs January 19, 2012 John Wawrzynek Electrical Engineering and Computer Sciences University of California, Berkeley Spring 2012 EECS150 lec02-logic-review-fpgas Page 1 General Model for Synchronous Systems All synchronous digital systems fit this model: Collections of combinational logic blocks and state elements connected by signal wires. These form a directed graph with only two types of nodes (although the graph need not be bi-partite.) Instead of simple registers, sometimes the state elements are large memory blocks. Spring 2012 EECS150 lec02-logic-review-fpgas Page 2

Outline Review of three representations for combinational logic: truth tables, gate diagrams, algebraic equations Laws of Boolean Algebra Canonical Forms Boolean Simplification multi-level logic

2 Outline Review of three representations for combinational logic: truth tables, gate diagrams, algebraic equations Laws of Boolean Algebra Canonical Forms Boolean Simplification multi-level logic NAN/NOR Networks Field Programmable Gate Arrays (FPGAs) Introduction Spring 2012 EECS150 - Lec02-logic-FPGA Page 3 Combinational Logic (CL) efined y i = f i (x0,...., xn-1), where x, y are {0,1}. Y is a function of only X. If we change X, Y will change immediately (well almost!). There is an implementation dependent delay from X to Y. Spring 2012 EECS150 - Lec02-logic-FPGA Page 4

CL Block Example #1 Boolean Equation: y 0 = (x 0 AN not(x 1 )) OR (not(x 0 ) AN x 1 ) y 0 = x

called logic circuits? Logic: The study of the principles of reasoning.

system (algebra) involving logic, Boolean Algebra.

3 CL Block Example #1 Boolean Equation: y 0 = (x 0 AN not(x 1 )) OR (not(x 0 ) AN x 1 ) y 0 = x 0 x 1 ' + x 0 'x 1 Truth Table escription: Gate Representation: How would we prove that all three representations are equivalent? Spring 2012 EECS150 - Lec02-logic-FPGA Page 5 Boolean Algebra/Logic Circuits Why are they called logic circuits? Logic: The study of the principles of reasoning. The 19th Century Mathematician, George Boole, developed a math. system (algebra) involving logic, Boolean Algebra. His variables took on TRUE, FALSE Later Claude Shannon (father of information theory) showed (in his Master s thesis!) how to map Boolean Algebra to digital circuits: Primitive functions of Boolean Algebra: Spring 2012 EECS150 - Lec02-logic-FPGA Page

Spring 2012 EECS150 - Lec02-logic-FPGA Page 7 CL Block Example #2 4-bit adder: Truth Table Representation: R = A + B, c is

4 Relationship Among Representations * Theorem: Any Boolean function that can be expressed as a truth table can be written as an expression in Boolean Algebra using AN, OR, NOT. How do we convert from one to the other? Spring 2012 EECS150 - Lec02-logic-FPGA Page 7 CL Block Example #2 4-bit adder: Truth Table Representation: R = A + B, c is carry out In general: 2 n rows for n inputs. 25 rows! Is there a more efficient (compact) way to specify this function? Spring 2012 EECS150 - Lec02-logic-FPGA Page 8

4-bit Adder Example Motivate the adder circuit design by

follows: carry to next stage r = a XOR b = a b c = a AN b =

Lec02-logic-FPGA Page 9 In general: r i = a i b i c in

c in (a i + b i ) + a i b i Now, the 4-bit adder: Full

5 4-bit Adder Example Motivate the adder circuit design by hand addition: Add a1 and b1 as follows: Add a0 and b0 as follows: carry to next stage r = a XOR b = a b c = a AN b = ab r = a b c i co = ab + ac i + bc i Spring 2012 EECS150 - Lec02-logic-FPGA Page 9 In general: r i = a i b i c in 4-bit Adder Example c out = a i c in + a i b i + b i c in = c in (a i + b i ) + a i b i Now, the 4-bit adder: Full adder cell ripple adder Spring 2012 EECS150 - Lec02-logic-FPGA Page 10

(a i b i ) c in c out = c in (a i + b i ) + a i b i Spring 2012 EECS150 -

6 4-bit Adder Example Graphical Representation of FAcell r i = a i b i c in c out = a i c in + a i b i + b i c in Alternative Implementation (with 2-input gates): r i = (a i b i ) c in c out = c in (a i + b i ) + a i b i Spring 2012 EECS150 - Lec02-logic-FPGA Page 11 efined as: Boolean Algebra Spring 2012 EECS150 - Lec02-logic-FPGA Page 12

7 Logic Functions o the axioms hold? Ex: communitive law: a+b = b+a? Spring 2012 EECS150 - Lec02-logic-FPGA Page 13 Some Laws of Boolean Algebra uality: A dual of a Boolean expression is derived by interchanging OR and AN operations, and 0s and 1s (literals are left unchanged). Any law that is true for an expression is also true for its dual. Operations with 0 and 1: 1. x + 0 = x x * 1 = x 2. x + 1 = 1 x * 0 = 0 Idempotent Law: 3. x + x = x x x = x Involution Law: 4. (x ) = x Laws of Complementarity: 5. x + x = 1 x x = 0 Commutative Law:. x + y = y + x x y = y x Spring 2012 EECS150 - Lec02-logic-FPGA Page 14

8 Laws of Boolean Algebra (cont.) Associative Laws: (x + y) + z = x + (y + z) x y z = x (y z) istributive Laws: x (y + z) = (x y) + (x z) x +(y z) = (x + y)(x + z) Simplification Theorems: x y + x y = x x + x y = x (x + y) (x + y ) = x x (x + y) = x emorgan s Law: (x + y + z + ) = x y z (x y z ) = x + y +z Theorem for Multiplying and Factoring: (x + y) (x + z) = x z + x y Consensus Theorem: x y + y z + x z = (x + y) (y + z) (x + z) x y + x z = (x + y) (x + z) Spring 2012 EECS150 - Lec02-logic-FPGA Page 15 Proving Theorems via axioms of Boolean Algebra Ex: prove the theorem: x y + x y = x x y + x y = x (y + y ) distributive law x (y + y ) = x (1) x (1) = x identity complementary law Ex: prove the theorem: x + x y = x x + x y = x 1 + x y identity x 1 + x y = x (1 + y) distributive law x (1 + y) = x (1) identity x (1) = x identity Spring 2012 EECS150 - Lec02-logic-FPGA Page 1

9 emorgan s Law (x + y) = x y Exhaustive Proof (x y) = x + y Exhaustive Proof Spring 2012 EECS150 - Lec02-logic-FPGA Page 17 Relationship Among Representations * Theorem: Any Boolean function that can be expressed as a truth table can be written as an expression in Boolean Algebra using AN, OR, NOT. How do we convert from one to the other? Spring 2012 EECS150 - Lec02-logic-FPGA Page 18

10 Canonical Forms Standard form for a Boolean expression - unique algebraic expression directly from a true table (TT) description. Two Types: * Sum of Products (SOP) * Product of Sums (POS) Sum of Products (disjunctive normal form, minterm expansion). Example: minterms a b c f f a b c a b c a bc a bc ab c ab c abc abc One product (and) term for each 1 in f: f = a bc + ab c + ab c +abc +abc f = a b c + a b c + a bc Spring 2012 EECS150 - Lec02-logic-FPGA Page 19 Canonical Forms Product of Sums (conjunctive normal form, maxterm expansion). Example: maxterms a b c f f a+b+c a+b+c a+b +c a+b +c a +b+c a +b+c a +b +c a +b +c One sum (or) term for each 0 in f: f = (a+b+c)(a+b+c )(a+b +c) f = (a+b +c )(a +b+c)(a +b+c ) (a +b +c)(a+b+c ) Mapping from SOP to POS (or POS to SOP): erive truth table then proceed. Spring 2012 EECS150 - Lec02-logic-FPGA Page 20

11 Algebraic Simplification Example Ex: full adder (FA) carry out function (in canonical form): Cout = a bc + ab c + abc + abc Spring 2012 EECS150 - Lec02-logic-FPGA Page 21 Algebraic Simplification Cout = a bc + ab c + abc + abc = a bc + ab c + abc + abc + abc = a bc + abc + ab c + abc + abc = (a + a)bc + ab c + abc + abc = (1)bc + ab c + abc + abc = bc + ab c + abc + abc + abc = bc + ab c + abc + abc + abc = bc + a(b +b)c + abc +abc = bc + a(1)c + abc + abc = bc + ac + ab(c + c) = bc + ac + ab(1) = bc + ac + ab Spring 2012 EECS150 - Lec02-logic-FPGA Page 22

12 Multi-level Combinational Logic Example: reduced sum-of-products form x = adf + aef + bdf + bef + cdf + cef + g Implementation in 2-levels with gates: cost: 1 7-input OR, 3-input AN => 50 transistors delay: 3-input AN gate delay + 7-input OR gate delay Factored form: x = (a + b +c)(d + e)f + g cost: 1 3-input OR, 2 2-input OR, 1 3-input AN => 20 transistors delay: 3-input OR + 3-input AN + 2-input OR Footnote: NAN would be used in place of all ANs and ORs. Which is faster? In general: Using multiple levels (more than 2) will reduce the cost. Sometimes also delay. Sometimes a tradeoff between cost and delay. Spring 2012 EECS150 - Lec02-logic-FPGA Page 23 Multi-level Combinational Logic Another Example: F = abc + abd +a c d + b c d let x = ab y = c+d f = xy + x y Incorporates fanout. No convenient hand methods exist for multi-level logic simplification: a) CA Tools use sophisticated algorithms and heuristics b) Humans and tools often exploit some special structure (example adder) Spring 2012 EECS150 - Lec02-logic-FPGA Page 24

x y xor xnor 0 0 0 1 0 1 1 0 1 0 1 0 EXOR Function Parity, addition mod 2 x y = x y + xy 1 1 0 1 Another approach:

13 x y xor xnor EXOR Function Parity, addition mod 2 x y = x y + xy Another approach: Spring 2012 EECS150 - Lec02-logic-FPGA Page 25 Project platform: Xilinx ML Spring 2012 EECS150 - Lec02-logic-FPGA Page 2

.. Copper Heatspreader Thermal Interface Material Underfill Epoxy Adhesive Epoxy* Flip Chip Solder

14 FPGA: Xilinx Virtex-5 XC5VLX110T Virtex-5 die photo Spring 2012 EECS150 - Lec02-logic-FPGA Page 27 A die is an unpackaged part Serial () Ball Grid Array (BGA) Flip-Chip Package From die to PC board... Copper Heatspreader Thermal Interface Material Underfill Epoxy Adhesive Epoxy* Flip Chip Solder Bump Silicon ie Solder Ball Organic Build-Up Substrate Spring 2012 EECS150 - Lec02-logic-FPGA Page 28 Serial ()

15 FPGA Overview Basic idea: two-dimensional array of logic blocks and flip-flops with a means for the user to configure (program): 1. the interconnection between the logic blocks, 2. the function of each block. Simplified version of FPGA internal architecture: Spring 2012 EECS150 - Lec02-logic-FPGA Page 29 Why are FPGAs Interesting? Technical viewpoint: For hardware/system-designers, like ASICs only better! Tape-out new design every few minutes/hours. oes the reconfigurability or reprogrammability offer other advantages over fixed logic? ynamic reconfiguration? In-field reprogramming? Self-modifying hardware, evolvable hardware? Spring 2012 EECS150 lec02-logic-review-fpgas Page 30

16 Why are FPGAs Interesting? Staggering logic capacity growth (10000x): Year Introduced evice Logic Cells logic gate equivalents 1985 XC XC7V2000T 1,954,50 15,3,480 FPGAs have tracked Moore s Law better than any other programmable device. Spring 2012 EECS150 lec02-logic-review-fpgas Page 31 Why are FPGAs Interesting? Logic capacity now only part of the story: on-chip RAM, high-speed I/Os, hard function blocks,... Modern FPGAs are reconfigurable systems Xilinx Virtex-5 LX110T 10GBps Serdes Ethernet MACs PCI express Phy But, the heterogeneity erodes the purity argument. Mapping is more difficult. Introduces uncertainty in efficiency of solution Kb SRAM Blocks Spring 2012 EECS150 lec02-logic-review-fpgas Page 32

FPGAs are in widespread use FPGAs Power Net-Centric Battlefield on Many Fronts Far more designs are implemented in FPGA than in custom

INSIE Make MicroBlaze Processing Roar With Hardware Acceleration FPGAs Help CERN Track Particles Approaching Speed of Light Xcell

Taming Power raw in Consumer MPUs Plugging into High-Volume Consumer Products INSIE Algorithm evelopers Power New A System on Xilinx

for Automotive at Guitar Hero Using Xilinx FPGA SP Algorithms Tips and Tricks for ESIGN TOOLS Using FPGA Editor New ISE 7.

Programmability Latch-based (Xilinx, Altera, ) + reconfigurable volatile relatively large. Latches are used to: 1.

17 FPGAs are in widespread use FPGAs Power Net-Centric Battlefield on Many Fronts Far more designs are implemented in FPGA than in custom chips. INSIE Make MicroBlaze Processing Roar With Hardware Acceleration FPGAs Help CERN Track Particles Approaching Speed of Light Xcell Automotive Innovators Hit Hit High Top Gear in river Assistance with FPGA Platforms Hardware Trumps Software in Medical evice esign Taming Power raw in Consumer MPUs Plugging into High-Volume Consumer Products INSIE Algorithm evelopers Power New A System on Xilinx Automotive FPGA Platform Engineer Turns Blown HIGH VOLUME Engine into Hot Startup Spartan-3E: A New Era How to Beat Your Son Multimedia for Automotive at Guitar Hero Using Xilinx FPGA SP Algorithms Tips and Tricks for ESIGN TOOLS Using FPGA Editor New ISE 7.1i Software and SystemVerilog Control Your esigns SERIAL I/O Spring 2012 CS Lec02-logic-FPGA Page 33 Extend Your Reach SUBS User Programmability Latch-based (Xilinx, Altera, ) + reconfigurable volatile relatively large. Latches are used to: 1. control a switch to make or break cross-point connections in the interconnect 2. define the function of the logic blocks 3. set user options: within the logic blocks in the input/output blocks global reset/clock Configuration bit stream is loaded under user control Spring 2012 CS Lec02-logic-FPGA Page 34

18 Background (review) for upcoming A MUX or multiplexor is a combinational logic circuit that chooses between 2 N inputs under the control of N control signals. A latch is a 1-bit memory (similar to a flip-flop). Spring 2012 EECS150 - Lec02-logic-FPGA Page 35 Idealized FPGA Logic Block 4-input look up table () implements combinational logic functions Register optionally stores output of Spring 2012 CS Lec02-logic-FPGA Page 3

19 4- Implementation n-bit is implemented as a 2 n x 1 memory: inputs choose one of 2 n memory locations. memory locations (latches) are normally loaded with values from user s configuration bit stream. Inputs to mux control are the CLB inputs. Result is a general purpose logic gate. n- can implement any function of n inputs! Spring 2012 CS Lec02-logic-FPGA Page 37 as general logic gate An n-lut as a direct implementation of a function truth-table. Each latch location holds the value of the function corresponding to one input combination. Example: 4-lut Example: 2-lut Implements any function of 2 inputs. How many of these are there? How many functions of n inputs? Spring 2012 CS Lec02-logic-FPGA Page 38

FPGA Generic esign Flow esign Entry: Create your design files using: schematic editor or HL (hardware description languages: Verilog, VHL) esign Implementation: Logic synthesis (in case of using HL

20 FPGA Generic esign Flow esign Entry: Create your design files using: schematic editor or HL (hardware description languages: Verilog, VHL) esign Implementation: Logic synthesis (in case of using HL entry) followed by, Partition, place, and route to create configuration bit-stream file esign verification: Optionally use simulator to check function, Load design onto FPGA device (cable connects PC to development board), optional logic scope on FPGA check operation at full speed in real environment. Spring 2012 CS Lec02-logic-FPGA Page 39 Example Partition, Placement, and Route Idealized FPGA structure: Example Circuit: collection of gates and flip-flops Circuit combinational logic must be covered by 4-input 1-output s. Flip-flops from circuit must map to FPGA flip-flops. (Best to preserve closeness to CL to minimize wiring.) Best placement in general attempts to minimize wiring. Vdd, GN, clock, and global resets are all prewired. Spring 2012 CS Lec02-logic-FPGA Page 40

21 Example Partition, Placement, and Route OUT IN Example Circuit: collection of gates and flip-flops A A B B Two partitions. Each has single output, no more than 4 inputs, and no more than 1 flip-flop. In this case, inverter goes in both partitions. Note: the partition can be arbitrarily large as long as it has not more than 4 inputs and 1 output, and no more than 1 flip-flop. Spring 2012 CS Lec02-logic-FPGA Page 41 Xilinx FPGAs (interconnect detail) Spring 2012 CS Lec02-logic-FPGA Page 42

22 Colors represent different types of resources: Logic Block RAM SP (ALUs) Clocking I/O Serial I/O + PCI A routing fabric runs throughout the chip to wire everything together. Spring 2012 EECS150 - Lec02-logic-FPGA Page 43 Configurable Logic Blocks (CLBs) Slices define regular connections to the switching fabric, and to slices in CLBs above and below it on the die. CLB COUT COUT Serial () Slice(1) Switch Matrix Slice(0) CIN CIN UG190_5_01_12205 The LX110T has 17,280 slices. Spring 2012 EECS150 - Lec02-logic-FPGA Page 44

23 X-Y naming convention for slices X0, X2,... are lower CLB slices. X1, X3,... are upper CLB slices. Y0, Y1,... are CLB column positions. COUT COUT COUT COUT CLB Slice X1Y1 CLB Slice X3Y1 Slice X0Y1 Slice X2Y1 CIN CIN CIN CIN CLB COUT Slice X1Y0 COUT CLB COUT Slice X3Y0 COUT Slice X0Y0 Slice X2Y0 Lower-left corner of the die. UG190_5_02_12205 Spring 2012 EECS150 - Lec02-logic-FPGA Page 45 Atoms: 5-input Look Up Tables (s) A2 A3 A4 A5 A 5 A[:2] (1) (0) (1). (0) A[:2]. Computes any 5- input logic function. Timing is independent of function (0) (1) Latches set during configuration. 4 Spring 2012 EECS150 - Lec02-logic-FPGA Page

24 A1 A2 A3 A4 A5 A Virtex-5 -s: Composition of 5-s May be used A2 A3 A4 A5 A A2 A3 A4 A5 A as one -input ( out) or as two 5-input S ( and 5) Figure 3: Block iagram of a Virtex-5 -Input WP245_03_05100 The LX110T has 9,120 -s - delay is 0.9 ns Combinational logic (post configuration) Spring 2012 EECS150 - Lec02-logic-FPGA Page 47 ([:1]) (C[:1]) (B[:1]) A[:1] A[:1] A[:1] The simplest view of a slice SLICE (Optional) (Optional) () () (C) (C) (B) (B) Four -s Four Flip-Flops Switching fabric may see combinational and registered outputs. (A[:1]) (CLK) A[:1] (Optional) (Optional) (A) (A) An actual Virtex-5 slice adds many small features to this simplified diagram. We show them one by one... Spring 2012 EECS150 - Lec02-logic-FPGA Page 48

25 SLICE Two 7-s per slice... ([:1]) A[:1] F7BMUX (C[:1]) (CX) A[:1] (CMUX) (C) (Optional) Extra multiplexers(f7amux, F7BMUX) (CLK) (B[:1]) A[:1] F7AMUX Extra inputs (AX and CX) (AMUX) (A[:1]) A[:1] (A) (Optional) (AX) Spring 2012 EECS150 - Lec02-logic-FPGA Page 49 Or one 8-s per slice... SLICE ([:1]) A[:1] F7BMUX (C[:1]) A[:1] F8MUX Third multiplexer(f8mux) (CX) (BMUX) (B[:1]) A[:1] F7AMUX (Optional) (B) Third input (BX) (A[:1]) (AX) (BX) (CLK) A[:1] Configuring the n of an n-... Spring 2012 EECS150 - Lec02-logic-FPGA UG Page 50

26 Extra muxes to chose option... Inputs X O5 FE/LAT CE MUX From eight 5-s... to one 8-. CLK SR REV C Inputs CX O5 F7BMUX F8MUX FE/LAT CE C CMUX C Combinational or registered outs. CLK B Inputs BX O5 SR REV FE/LAT CE CLK SR REV B BMUX B Flip-flops unused by s can be used standalone. A Inputs AX CE CLK SR REV (X) F7AMUX A AMUX O5 FE/LAT A CE CLK SR REV Spring 2012 EECS150 - Lec02-logic-FPGA Page 51 UG190_5_25_05050 From O5 From X S3 COUT (To Next Slice) I3 MUXCY Virtex 5 Verical Logic Carry Chain Block (CARRY4) CO3 O3 MUX/* MUX We can map ripple-carry addition onto carry-chain block. (Optional) From C S2 MUXCY CO2 CMUX/C* O5 From C CX I2 O2 CMUX C (Optional) From B S1 MUXCY CO1 BMUX/B* O5 From B BX I1 O1 BMUX B From A O5 From A AX S0 I0 CYINIT 0 1 MUXCY CIN CO0 O0 (Optional) AMUX/A* AMUX A (Optional) * Can be used if unregistered/registered outputs are free. Spring 2012 CIN (From Previous Slice) EECS150 - Lec02-logic-FPGA Page 52 UG190_5_24_05050 The carry-chain block also useful for speeding up other adder structures and counters.

27 Putting it all together... a SLICEL X A A5 A4 A3 A2 A1 ROM O5 COUT X CE CK Reset Type Sync Async FF LATCH INIT1 INIT0 SRHIGH SRLOW SR REV MUX The previous slides explain all SLICEL features. CMUX C C5 C4 C3 C2 C1 CX B B5 B4 B3 B2 B1 BX A A5 A4 A3 A2 A1 AX SR CE CLK A A5 A4 A3 A2 A1 A A5 A4 A3 A2 A1 A A5 A4 A3 A2 A1 ROM ROM ROM O5 O5 O5 0/1 C CX B BX A AX CE CK CE CK CE CK Spring 2012 EECS150 - Lec02-logic-FPGA Page FF LATCH INIT1 INIT0 SRHIGH SRLOW SR FF LATCH INIT1 INIT0 SRHIGH SRLOW SR FF LATCH INIT1 INIT0 SRHIGH SRLOW SR REV REV REV C C BMUX B B AMUX A A About 50% of the 17,280 slices in an LX110T are SLICELs. The other slices are SLICEMs, and have extra features. 53 CIN UG190_5_04_0320 A2 A3 A4 A5 A 5 A[:2] Recall: 5- architecture... (1) (0) (1). (0) (0) (1). A[:2] 32 Latches. Configured to 1 or 0. Some parts of a logic design need many state elements. SLICEMs replace normal 5-s with circuits that can act like 5-s, but can alternatively use the 32 latches as RAM, ROM, shift registers. Spring 2012 EECS150 - Lec02-logic-FPGA Page 54

28 Virtex-5 SP48E Slice Efficient implementation of multiply, add, bit-wise logical. LX110T has 4 in a single column. Spring 2012 EECS150 - Lec02-logic-FPGA Page 55 Spring 2012 EECS150 - Lec02-logic-FPGA Page 5

29 To be continued... Throughout the semester, we will look at different Virtex-5 features in-depth. Switch fabric Block RAM SP48 (ALUs) Clocking I/O Serial I/O + PCI Spring 2012 EECS150 - Lec02-logic-FPGA Page 57 Serial ()

EECS150 - Digital Design Lecture 19 - Combinational Logic Circuits : A Deep Dive

EECS150 - Digital Design Lecture 19 - Combinational Logic Circuits : A Deep Dive March 30, 2010 John Wawrzynek Spring 2010 EECS150 - Lec19-cl1 Page 1 Boolean Algebra I (Representations of Combinational