The Inverter. References:

Transcription

1 The Iverer Refereces: Adaped from: Digial Iegraed Circuis: A Desig Perspecive, J. Rabaey UCB Priciples of CMOS LSI Desig: A Sysems Perspecive, d Ed., N. H. E. Wese ad K. Eshraghia

2 Regios of Operaio Cuoff No-sauraed Sauraed p-device gsp > p gsp < p i < p + gsp = p i < p + i > p + dsp > gsp - p ou > i - p dsp < gsp - p ou < i - p -device gs < gs > i > gs > i > i < ds < gs - ou < i - ds > gs - ou > i -

3 Digial Gaes - Fudameal Parameers Area ad Complexiy Robusess ad Reliabiliy Performace Power Cosumpio

4 Noise i digial Iegraed Circuis uwaed variaios of volages ad curres a he logic odes i ( v( (a Iducive couplig (b Capaciive couplig (c Power ad groud oise

5 DC Operaio : olage Trasfer Characerisic(TC ou OH f ou = i M Swichig Threshold olage ( Trasisor Threshold olage OL OL OH i Nomial olage Levels

6 Mappig bewee aalog ad digial sigals (y 1 OH 1H OH Slope = -1 = d d ou i (gai 0 Udefied Regio IL Slope = -1 = d d ou i OL OL IL IH (x Udefied Regio (Trasiio widh TW

7 Defiiaio of Noise Margis 1 NM H = OH - IH OH OL 0 NM H NM L IH I L Udefied Regio NM L = IL - OL Gae Oupu Sage M Gae Ipu Sage M+1

8 The Regeeraive Propery A chai of iverers

9 Codiios for Regeeraio ou ou 3 f(v fiv(v 1 f( 0 1 fiv(v 3 f(v 0 i 0 i (a Regeeraive gae (b No-regeeraive gae

10 Fa-i ad Fa-ou (a Fa-ou N M N (b Fa-i M

11 The Ideal Gae ou R i = g = - R o = 0 i

12 ou ( TC of Real Iverer NM L M 1.0 NM H i (

13 Delay Defiiios i 50% ou phl plh 90% 50% 10% f r

14 Rig Oscillaor T = x p x N N p >> f + r

15 Power Dissipaio P( = isaaeous power P peak = i peak supply = max (p( P av 1 T T 0 p( d supply T T i ply 0 sup ( d Power-Delay Produc PDP = p x P av = Eergy dissipaed per operaio

16 Saic Load MOS Iverers

17 Saic Load MOS Iverers R load I bias ou ou i i

18 Basic Iverer ou i i < h ; NMOS off; ou pulled o i > h ; NMOS o, curre flows hrough R o groud If R is sufficiely large, ou could be pulled dow well below h ;

19 Saic Load MOS Iverer I ds R ou ou = ds I ds.r = - ds

20 TC of Resisive Load

21 Resisive Load Device R load oh = 5.0 ol =??? i ou I = ( dd - ol /R I =.(( dd - ol -0.5 ol R.(( dd ( dd ol ol 0.5 ol

22 Sizig for OL R.(( dd ( dd ol ol 0.5 ol Assume: dd = 5.0 = 1.0 = 10-4 A/ Proper desig: ol < Le: ol = 0.5 R = 4kW

23 Resisor ad Curre-Source Loads Resisace/legh of miimum-widh lies of various coecig elemes is far less ha effecive resisace of he swiched o MOSFET I some memory processes, resisors are implemeed by highly resisive udoped polysilico Normally use rasisors i CMOS o impleme resisor ad curre-source loads If biased for use as a resisor, called a usauraed load iverer If load rasisor operaes i sauraio as a cosa curre source, called a sauraed load iverer

24 Pseudo NMOS Iverer ou L = 1 i + dsp = ou dsp = ou - dsp = ou + gsp dsp > gsp - p or ou > - p No-sauraed regio

25 DC Trasfer Characerisics

26 Pseudo-NMOS Iverer ou i DC curre flows whe he iverer is ured o ulike CMOS iverer CMOS is grea for low power ulike his circui (e.g. wach eeds low power lap-ops ec Need o be ured off durig IQ ( Supply Curre Quiesce esig

27 PMOST Load wih Cosa GS oh = 5.0 ol =??? I = 0.5 p.( dd - p ou I =.(( dd - ol -0.5 ol i p (( dd 0.5( dd ol p 0.5 ol

28 Sizig for OL p (( dd 0.5( dd ol p 0.5 ol Assume: dd = 5.0 = p = 1.0 Proper desig: ol < h Le: ol = 0.5 p 4.6

29 Sizig for Gae Threshold olage (Trip Poi N-device: sauraed I ds ( ( P-device: o-sauraed I gsp dsp i ou [( p i p ( Equaig he wo curres we obai, ou ( ou ] ( i [( ( ( ou p p ou ]

30 Sizig for Gae Threshold olage Solvig for ou ou p ( p C Where C = k ( i - k p ( p ( Also, ( p i ou p To make gae hreshold volage = p

31 Noise Margi / p IL IH OL OH NM L NM H

32 TC of Pseudo-NMOS Iverer

33 Usauraed Load Iverer ou i High is hreshold dow from Used whe depleio mode rasisors were o available Low oise margi Migh be used i I/O srucures where p-rasisors were o waed

34 TC of Usauraed Load Iverers For k = 4 OL = 0.4 IH =. OH = 3.8 IL = 0.56

35 Curre Source Load I bias ou ou i i

36 Sauraed Load Iverer i ou ou > i - driver rasisor i sauraio Whe i is small Load rasisor permaely i sauraio dsp = gsp dsp < gsp - p or 0 < - p Sauraed regio

37 Whe i is Small I driver ds, driver ( i Load i sauraio: I load ds, load ( ou p Equaig he curres: ou p k ( i where k drive load

38 TC of Sauraed Load Iverer For k = 4 OL = 0.4 IH =.1 OH = 4.4 IL = 0.5

39 NMOS Iverer Use depleio mode rasisor as pull-up dep rasisor is < 0 diffusio depleio mode rasisor (poly ou i ehaceme mode rasisor i ou The depleio mode rasisor is always ON: gae ad source coeced gs = 0 i = 0 rasisor pull dow is off ou is high

40 ou vs i usig Graphical Mehod I ds (dep I ds (eh gs = 0.0 gs = -0. I ds ds (dep gs (dep = 0 I ds I ds gs (eh ds (dep - ds (dep - ds(dep = ds(eh = ou I a seady sae, I ds of boh rasisors are equal ds (eh = - ds (dep ds (eh = ou Therefore ou = - ds (dep

41 Gae Threshold olage Gae hreshold volage = iv = Ipu volage a which i = ou Assume ha boh driver ad load are i sauraio wih ipu iv Hece, I DS ( sa iv driver ( driver iv dep ( gs load driver If driver is icreased relaive o load he, iv decreases load ( dep i ou

42 TC of NMOS iverer Slope G icreases, iv decreases icreasig driver load

43 CMOS INERTER

44 CMOS Iverers

45 The CMOS Iverer: A Firs Glace D D S i D ou C L S

46 Swich Model of MOS Trasisor GS GS < T GS > T

47 CMOS Iverer: Seady Sae Respose R o OH = OL = 0 ou M = f(r o, R op i = i = 0

48 PMOS Load Lies i = - GSp I d = -I DP ou = - DSp I D ou I Dp I D I D i = 0 i = 0 i = 3 i = 3 GSp = - DSp DSp ou GSp = -5 i = + GSp I D = - I Dp ou = - DSp

49 Cosrucio Of Iverer Curves I ds ds

50 Cosrucio Of Iverer Curves I ds ds

51 Cosrucio Of Iverer Curves I ds ds

52 CMOS Iverer Load Characerisics I,p i = 0 i = 5 PMOS NMOS i = 1 i = 4 i = 3 i = 4 i = 5 i = i = 3 i = 3 i = i = i = 1 i = 0

53 CMOS Iverer TC ou i 5.0

54 Iverer Supply Curre I d =I dp =I supply

55 Small Sigal Model for a MOS Trasisor sb = 0 volage-corolled curre source (g m oupu coducace (g ds ierelecrode capaciace G C gd D C gs + C gb g m gs g ds C db S

56 Oupu Coducace By differeiaig I ds w.r.. ds I liear regio I g ds ds [( gs ds ds [( gs ds] ] R liear ( gs 1 I sauraio, device behaves like a curre source: he curre beig almos idepede of ds Ids [ ( gs ] d[ ( gs dids d d ds ds ] 0 I realiy, secodary effecs resul i a slope gds I ds ds

57 Trascoducace Expresses relaioship bewee oupu curre ad ipu volage g m ( liear g m g m ( sa. di d ds gs ds ( gs ds cosa

58 MOS Trasisor Small Sigal Model G + v gs - g m v gs r 0 S g m r o Liear k DS [k( GS - T - DS ] -1 Sauraio k( GS - T 1/I D

59 CMOS Iverer s d d ou = - sdp = + dsp i = - sgp = + gsp i ou s i = gs, ou = ds

60 Regios of Operaio Cuoff No-sauraed Sauraed p-device gsp > p gsp < p i < p + gsp = p i < p + i > p + dsp > gsp - p ou > i - p dsp < gsp - p ou < i - p -device gs < gs > i > gs > i > i < ds < gs - ou < i - ds > gs - ou > i -

61 Iverer Operaig Regios A: mos off pmos liear reg B: mos sauraed pmos liear reg. ou C: mos sauraed pmos sauraed D: mos liear reg. pmos sauraed 0.0 i 5.0 E: mos liear reg. pmos off

62 Iverer Operaig Regios A: mos off pmos liear regio B: mos sauraed pmos liear regio ou ou ou ou ou C: mos sauraed pmos sauraed D: mos liear regio pmos sauraed E: mos liear regio pmos off A B C D E Assume ifiie r o whe a device is i sauraio

63 Regio A (0 i I ds = 0 -device is cu-off p-device i liear regio I ds = - I dsp = 0, as I ds = 0 dsp = ou - i ou Wih dsp = 0, ou =

64 Regio B ( i p-device i o-sauraed regio ( ds 0 -device is i sauraio I dsp i = gs I ds ou

65 Regio B I ds [ i ] ; W ( L ox gsp = ( i - & dsp = ( ou - I p dsp [( ox p p W ( L p p i p ( ou ( ou ] Equaig I dsp = -I ds ou ( i p ( i p ( i p ( i c p

66 Regio D ( i p p : sauraio : o-sauraed I dsp I I I dsp ds dsp [( 1 p ( I ds i i ou p ou ] I ds ou ou ( i ( i p ( i p

67 Deermiig IH ad IL

68 Regio E ( i >= - p p: cu-off I dsp = 0 : liear mode gsp = i - more posiive ha p ou = 0

69 Regio C (Boh devices i Sauraio I I dsp ds p ( i ( i p Equaig I dsp = -I ds i p 1 p p

70 Gae Threshold olage If = p & = - p i Regio C exiss for oe value of i Possible values of ou i regio C -chael p-chael i - ou < ou > i - i - ou > p ou < i - p sauraio codiios i - < ou < i - p I realiy, regio C has a fiie slope - because i realiy I ds icreases slighly wih ds i sauraio

71 Typical Parameer alues (1mm process 3 500cm ox p 00A p 180cm p W 31.9 L.8 W ( L ox / / sec 14 sec A/ F / cm W 88.5 A/ L 14 W L (The raio varies from -3

72 / p Raio ou icreasig p i icreasig W W p ou i

73 Effec of / p Raio m depede o p wih chage i rasiio sill remais sharp ad hece p swichig performace does o deeriorae I is desirable o have p = 1 allows capaciace load o chage ad discharge i equal imes by providig equal curre source & sik capabiliy

74 Gae Swichig Threshold M k p /k M r( p wih r 1 r p p

75 Effec of Temperaure Temperaure similarly affecs mobiliy of holes ad elecros Temperaure icreases decreases decreases 1.5 T Raio / p is idepede of emperaure o a good approximaio Temperaure, however, reduces hreshold volages Exe of regio A reduces ad exe of regio E icreases TC shifs o he lef as he emperaure icreases

76 Swichig Characerisics Swichig speed - limied by ime ake o charge ad discharge, C L Rise ime, r : waveform o rise from 10% o 90% of is seady sae value Fall ime, f : 90% o 10% of seady sae value Delay ime, d : ime differece bewee ipu rasiio (50% ad 50% oupu level

77 CMOS Iverer: Trasie Respose phl = f(r o C L = 0.69 R o C L ou C L 1 R o i = R o C L

78 CMOS Iverer Propagaio Delay phl C L swig I av / I av ou C L I av I( ou 7 8 I( ou 3 / i =

79 Iverer Propagaio Delay Assume -device sill i sauraio a ou = / Iav ( phl plh L ( C p C L C L p C L 1 p 1

80 Aalysis of Fall Time i ( ou ( C L I ds o-sauraed x sauraed ( ds = gs - x3 ou ( x1 Applicaio of sep ipu

81 Compoes of Fall Time f = f1 + f ou drops from dd - o 0.1 ou drops from 0.9 dd o dd i ou f

82 Fall Time for Sauraed Regio P Sauraed, Ipu risig ou - I c ou C L d d ou ( 0 I ds C L Iegraig from = 1 (correspodig o ou = 0.9 o = (correspodig o ou = ( - f 1 ( CL 0.9 d ou CL ( ( 0.1

83 Fall Time for No-Sauraed Regio p ou C L No-sauraed : 0 ou - C L f dou [( d CL ( 0.1. ou d ou ( ou ] 0 ou ou

84 Fall Time for No-Sauraed Regio f C ( L C ( l( ( CL l(19 0 (1 L d ou 0 ou ou where =

85 Fall Time Compuaio f f 1 f CL ( 0.1 (1 (1 1 l(19 0 f k C L k 3 ~ 4 for 3 ~ 5 ad 0.5 ~ 1

86 Rise Time r CL ( p l(19 0 (1 p (1 p p p wih r p k C p p L For equally sized - ad p rasisors p f r

87 Sizig for Ideical Rise/Fall Time For same f ad r p 1 Icrease he widh of p-device o Wp 3W

88 Delay Time: Firs Order Approximaio Gae delay is domiaed by he oupu rise ad fall ime dr df r f

89 Geeral Delay Time Compuaio Similar o he compuaio of rise/fall imes Sauraio regio from = 1 (correspodig o ou = o = (correspodig o ou = ( - Liear regio from = (correspodig o ou = ( - o = 3 CL 1 ( d ou C ( L (

90 Delay Time Compuaio ou ou ou ou L d C ' ' ' 3 ( ( (1 l( (1 l( ( O O L ou ou L C C where ou O,

91 Delay Time D 3 1 A C L Delay C L (opimize C L o decrease delay 1 1 (decrease icreases delay (if W or L, delay decreases Three major parameers for opimizig speed of CMOS

92 Compoes of C L C w = wirig capaciace C g = gae capaciace = C ox WL

93 Miller Effec Effecive volage chage over he gae-drai capacior is acually wice he oupu volage swig Coribuio of gae-drai capacior should be coued wice

94 Jucio Capaciace No-liear capacior modeled by liear capacior wih he same chage i charge for he volage rage of ieres C K eq eq K eq ( C high j0 m 0 (1 m low ( 0 high 1m ( Liearize over he ierval {5,.5} for he high-olow rasiio ad {0,.5} for he low-o-high rasiio Correspod o { high =-5, low =-.5} ad { high =0, low =-.5} for NMOS 0 low 1m

95 Delay i fucio of

96 Sizig of Iverer Loaded by a Ideical Gae Load cap. of firs gae: C L = (C dp1 + C d1 + (C gp + C g + C W where C dp1, C d1 diffusio capaciace of firs gae C gp, C g gae capaciace of secod gae C w wirig capaciace If PMOS devices are a imes larger ha he NMOS oes, a ( W / L p ( W / L all rasisor capaciaces will scale i approximaely he same way

97 Sizig of Iverer f r p (. / ( / (. (. (. ( a p p L p p p L p p L p p L A A C L W L W A A C A A C A A C w g d L g gp d dp C C C C C C C C ( 1 ( a a a

98 Sizig of Iverer p C L. (1 a( C ( A d1. Ap a g p Le 0 oge opimal a a A p aop (1 A C C p p C W ( A Ap. a p CW C d1 g If C W << C d1 + C g, A p = A a op p 1.73 Coras o 3 which is ormally used i he o-cascaded case

99 Impac of Rise Time o Delay PHL ( acual phl( sep ( r / Miimum-size iverer wih faou of a sigle gae

100 elociy Sauraio Uder log chael model, sauraio curre I small-geomery devices, his o loger holds: I av Therefore, for >> T we have, p C L 1 ( k p 1 k k, p Ruig velociy sauraed devices a high is o beeficial Lowerig below T sharply icreases delay v SAT C ox W, p

101 Source/Drai Resisace I small-geomery devices, source ad drai resisace affecs swichig curres Source of he rasisor is o loger grouded, body effec icreases hreshold volage gs is also reduced Curre is reduced

102 Power Cosumpio Saic Power Leakage curre Sub-hreshold coducace Dyamic Power Capaciive Power due o chargig/dischargig of capaciive load Shor-circui power due o direc pah curres whe here is a emporary coecio bewee power ad groud

103 Saic Power Cosumpio ou = I D Sub-hreshold curre K e Diode leakage ( q/ kt q/ kt gs I O (1 e i ds s ( e q / kt 1 P saic = I leakage.

104 Saic Cosumpio Leakage curre hrough he reverse biased diode jucios For ypical devices i is bewee 0.1A - 0.5A a room emperaure For a die wih 1 millio devices operaed a 5, his resuls i 0.5mW power cosumpio o much Jucio leakage curre is caused by hermally geeraed carriers -> herefore is a srog fucio of emperaure More impora is sub-hreshold leakage whe hreshold volage is close o 0

105 Dyamic Cosumpio due o C L ou - low-o-high rasiio - Assume 0 rise ad fall imes

106 Dyamic Power due o C L ou i i C L charge discharge Defie: E : eergy ake from supply durig a rasiio E C : eergy sored o capacior a he ed of rasiio

107 Eergy Cosumed ad Sored dou E i ( d CL. d 0 0 d C L C L 0 d ( Q ou 0 0 EC i ( oud C C L L. 0 ou d ou C L d d Half he eergy is sored i Capacior! Oher half is dissipaed i he PMOS rasisor!! For each swichig cycle ( L H & H L, amou of eergy dissipaed i C L. ou ou d

108 P dyamic = C L..f Example 1. CMOS chip 100 MHz clock rae Average load capaciace of 30 ff/gae 5 power supply Power cosumpio/gae = 75 W Desig wih 00,000 gaes: 15W! Pessimisic evaluaio: o all gaes swich a he full rae Have o cosider he aciviy facor a: Effecive swichig capaciace = ac L Reducig has a quadraic effec o P dyamic

109 Direc Pah Curre ipus have fiie rise ad fall imes Direc curre pah from o GND while PMOS ad NMOS are ON simulaeously for a shor period P sc = I mea. + p r f T I max I mea 1 3

110 Symmerical Iverer Wihou Load 3 1 ( 1 ( 1 mea d I T d I T I d T I i mea ( ( 1 wih rf f r r r r i. ( 1 If = - p = T ad = p = ad ha he behavior aroud is symmerical

111 Symmerical Iverer Wihou Load 3 3 / / 3 / / ( 1 ( 3 ( 3 ( rf rf rf rf rf mea T T T d T I rf T rf rf T rf T P rf sc 3 ( 1

112 Shor Circui Curre wih Loads

113 Oupu Trasiios uder Differe Loads

114 C L Power vs. SC Power uder Differe Loads

115 C L Power vs. SC Power uder Differe Ipus

116 Impac of Load Capaciace o SC Curre Large capaciace Fas ipu rasiio, slow oupu rasiio Ipu moves hrough he rasie regio before oupu begis o chage Shor-circui curre close o zero Small capaciace Relaively slower ipu rasiio, fas oupu rasiio Boh devices i sauraio durig mos of he rasiio Maximum shor-circui curre [eedrick84]: rise/fall imes of all sigals should be kep cosa wihi a rage o keep SC power miimal, 10%~0% of oal dyamic power

117 Techology Evoluio

118 Techology Scalig Miimum Feaure Size

119 Compoes/Chip Techology Scalig ehaceme mosfe bipolar Trasisor IC mosfe bipolar rasisor mesfe YEAR Number of compoes per chip

120 Gae Delay: Dd (sec/sage Propagaio Delay Scalig 1 500p F/O = 1 R.T. Operaio 00p Ref.[4] p 50p.5 Ref.[7] Ref.[5] Prese Resuls Repored Resuls 0p Scalig =5 10p Chael Legh : Lef (m

121 Techology Scalig Models Full Scalig (Cosa Elecrical Field ideal model dimesios ad volage scale ogeher by he same facor S Fixed olage Scalig mos commo model uil recely oly dimesios scale, volages remai cosa Geeral Scalig mos realisic for odays siuaio volages ad dimesios scale wih differe facors

122 Scalig Relaioships for Log chael Devices

123 Scalig of Shor Chael Devices

124 Homework Problem (due ex Thursday Desig a saic CMOS iverer wih 0.4pF load capaciace. Make sure ha you have equal rise ad fall imes. Layou he iverer usig he Meor ools, exrac parasiics, ad simulae he exraced circui o HSPICE o make sure ha your desig coforms o he specificaio. Do he same aalysis for a hree ipu NAND gae.