CHAP.4 Circuit Characteristics and Performance Estimation

Transcription

1 HAP.4 ircui haracerisics ad Performace Esimaio 4. Resisace esimaio ρ l R w (ohms) where ρ resisiviy hickess l coducor legh w coducor widh l R Rs w where Rs shee resisace (Ω/square) i 0.5µm o.0µm MOS processes

2 * hael resisace R c k W gs ( ) W µ ox gs k, k,000~30,000ω/square µ ( ) Typical shee resisace for coducors (Table 4.) hael resisace + 0.5% per Meal ad poly % per Well diffusio +.00% per Resisace for orecagular regios (Fig 4.) 4.3 apaciace esimaio ox gs Parasiic capaciace of Ruig/Swichig speed of MOS MOS ad Ruers + coducor resisace Toal load capaciace. Gae capaciace (of oher ipu). Diffusio capaciace (of he drai regios) 3. Rouig capaciace (of coecios bewee O/P & I/P) To esimae he speed of he device ( R ad iformaio) 4.3. MOS-apacior haracerisics (**w/o Source & Drai) Accumulaio g < 0 Gae volage depleio g 0 Iversio g > 0

3 (a) accumulaio layer is direcly coeced o subsrae. Gae capaciace ca be approximaed by o ε ε SiO 0 ox A (4.4) where A Area of gae usio Dielecric cosa u0 Permiiviy of free space Relaive permiiviy Of SiO 3.9 (b) Depleio mode: Fucio of : () dopig coceraio (N) () Elecroic charge (q) (3) Depleio deph (d) dep d A gb o i series wih dep gb dep ε 0 εsi ( ε Si ) dep 3 gb(gae-o-bulk(subs)), low frequecy dep dep (varied as a fucio of gs) mi, high frequecy ( < 00 Hz )

4 MOS Device capaciace ircui symbol gs, gd gae-o-chael capaciace (Ipu par) sb, db source/drai diff-o-bulk(subs) capaciace gb gae-o-bulk capaciace (Ipu) Toal gae capaciace g of a MOS device (or so-called ipu capaciace) g gb + gs + gd (a)off-regio: ( gs < ) No chael gs gd 0 g gb o + dep (b)no-sauraio regio : ( gs - > ds ) gd ε0ε gs 0 gb SiO ox A (c)sauraed regio: ( gs - < ds ) hael is heavily ivered pich off gd0 (Oupu par) gs ε 0 ε SiO 3 ox A Approx. of MOS gae capaciace 4

5 oservaive approximaio : g o ox PA where ox : hi-oxide capaciace per ui area. ε0εsio pf ox µ m ( λ 0.5µm ) ox o o ( ) 00Α ~ 00Α () (W) (ox) 4 ( µ m) ( µ m) ( pf µ m ) g pF Ui rasisor: A rasisor ha ca be coveiely coeced o meal a boh source ad drai Diffusio (source & drai) capaciace d : proporioal o oal diffusio-o-subsrae jucio area. Base. he area + area of he ( ab ) + ( a + b ) ja jp " side wall " periphery where.ja: jucio capaciace.jp: periphery capaciace / µ m / µ m 3. a : widh of diffusio area /µm 4. b : legh of diffusio area /µm 5

6 6 Thickess of depleio layer depeds o he volage across he jucio, boh ja ad jp are fucios of jucio volage (j) (m0.3~0.5) j jucio volage (egaive for reverse bias) jo(a,p) zero-bias capaciace (j 0) b build-i jucio poeial ~0.6 Diffusio capaciace form sb ad db i Fig Rouig capaciace Rouig capaciace bewee meal ad poly layers ad he subsrae ca be modeled as a parallel-plae capaciace. plus frigig field ha occurs a he edges of he coducor due o is fiie hickess. Toal capaciace (a) Parallel-plae cap. of widh (w-/) + (b) A cylidrical cap. of radiaes (/) Empirical formula ( ) ( ) m b j jo j p a p a,, A ε l h h h h w π ε h h w h w ε

7 I geeral, meal ad poly lies have higher cap. value ha he prediced values (due o frigig facor) Muliple coducor capaciace (Fig.4.,4.) Disribued R effecs og wires large R Trasmissio lie effecs R-secio model dj d (: secio umber) As umber of secios icrease differeial form d d x disace from ipu rc r resisace per ui legh d dx c capaciace per ui legh ( I I ) j rc ( l legh of he wire ) l Example : r 0 Ω µm, j ( j j ) ( j j + ) ( + ) R R R ( propagaio ime) kx ( wire of legh x) x 4 c 4 0 pf µ m (a) Poly bus of -mm, 5 p 4 0 l 6s (b) Poly bus (-mm) poly bus (-mm) + buffer p s + τ buf 5 ( 000 ) + τ ( 000 ) + 4 s buf 8s + τ buf 7

8 ousios: (a) Use poly for oly local iercoecio or very slow global iercoecio i wo-meal process. (b) As speed icreases, meal layer will also have R effec add buffer wide he lie ( R, icreases a lile ) shore legh ( l ) R delay model (impora i calculaig clock disribuio i highspeed, high-desiy chips), R : oal lumped R, of he lie. τ rcl apaciace desig guide (sec.4.3.7, HW#(a)) Wire-legh desig guide (Table 4.7) Iducace (sec.4.4) 4.5 Swichig haracerisics Swichig speed :. Time o charge he load capacior oward. Time o discharge oward SS (a) Rise ime (r): Time for a waveform o rise from 0%~90% of is seady-sae value. (b) Fall ime (f): fall from 90%~0% (c) Delay ime(d): ime differece bewee ipu rasiio(50%) ad he 50% oupu level. 8

9 Fall ime (f) : X: NMOS cu-off X: NMOS sauraed regio X3: NMOS osauraio (liear mode) Aalysis of f IN, (gs ), (iiial value) (a) f ou drops from 0.9 o (-) (X X) (sauraio) (b) f ou drops from (-) o 0. (X X3) (osauraio) (liear mode) f (NMOS is i sauraio mode) d d ou ( ) 0 + (discharge curre is cosa) f f 0.9 ( ) ( 0. ) ( ) d ou f (NMOS is i liear mode) IN DS ou I ( ) ou DS ou d d ou ( ) ou ou f l 9 0 ( ) [ ], / f f f + f k ( Eq.4.37 ) ( k 3 ~ 4) 9

10 Icress speed (How o opimize MOS circui speed) Reduce load capaciace Icrease ow supply volage low speed Rise ime ( p 0.) ( p) ( 9 p) r + l 0 p p p f k p ( k 3 ~ 4) Equal size,p devices, p f r!! f r p W p ( ~ 3) W Delay ime r f dr df ( approxima io ) a aleraive formula (a) ( ) 0 ( ) df AN, AN + l 0 (AN 0.83) wih /, 0ou/ (b) dr A p A p p (c) average gae delay for risig ad fallig rasiio av dr + df 0

11 SPIE simulaio (Figure 4.0) Empirical delay model : Backsubsiue io Eqs. (4.46) & (4.47) o obai AN ad AP for Wp W, AN AP 0.36 dr 0.36 / Gae delays For pull-dow case For pull-up case p,eff p (oly oe ur o), p,eff 3p (hree ur o) For p 0.3 Mobiliy differece 串聯 Graphical udersadig W W W ox p µ, ( ) eff + + ( ) 3, 0.3 r f f r k k series ox series k W 3 3 τ µ

12 Graphical Rule Fall ime: m -devices i series f`m f Rise ime: m p-devices i series r`m r Fall ime: m -devices i parallel (all ur o) f`f/m Rise ime: m p-devices i parallel (all ur o) r`r/m Swich-level R models (A) Simple R model : (R, are lumped ogeher) df ΣRpulldow Σpulldow-pah (RN+RN+ RN3+RN4) (ou+ab+ bc+cd) dr Rp ou Effecive Resisace RReff (W/) (B) Pefield-Rubesei model : calculae delays i geeralized R ree (ladder) Ri summed Resisace from d ΣRii poi i o power or groud i capaciace a poi i df (RN cd)+[(rn+rn) bc]+[(rn+rn+rn3) ab]+[(rn+rn+rn3+rn4) ou] Macro modelig (Daa book) Tswi : ipu waveform

13 i : ipu capaciace Tbeou : delay hrough he gae Tswou : o/p waveform : oupu capaciace I ASI desigs, logic gaes are reaed as simple delays. d ieral + k oupu Example oupu delay which is proporioal o oupu loadig cap. Fixed ieral delay. r k.s f k 3.8s ( k is i pf ) 3

14 Body effec () Body effec : γ sb Beer Bad () Poi D rises o abou.7vols before beig discharged o groud ( 上圖所示 ) (3) Nodes cd,bc,ad ab are a a -hreshold below (~3.vols).whe NIB urs o. Nodes ab,bc,ad cd are pulled o groud i ha order ( 下圖所示 ) (4) Whe >> ieral cap,his effec ca be miimized. Sraegy o hadle Body effec () Place rasisors wih laes arrivig sigals eares he oupu of he gae. The early sigals ``discharge`` ieral odes,ad he body effec is miimized. () Miimize ieral capaciaces : If diffusio wire is used o miimize he gae geomery, ry o use i a he oupu raher ha o some ieral odes. oclusio of secio 4.5: Model mus be accurae so ha AD ools ca work well. 4

15 4.6 MOS-Gae Trasisor Sizig *For rf, Wp(-3)W Icrease layou area *Approximaed delay for a iverer pair (a) iv-pair f + r (WpW) R(3eq)+( R )(3eq) 3Req+3Req6Req R o Res of a ui-size rasisor eqg+d (b) iv-pair (WpW) R(eq)+()(R)(eq) fall 6Req rise * /p raio rise / fall iv (Eg.4) dd+p+ iv + p 4.6. Sage raio p,whep,p idd/ Used whe : () log bus () I/O Buffers 5

16 (3) Pads (4) Off-chip capaciive load * To miimize he delay bewee Ipu ad oupu while miimizig he area ad power dissipaio. * Each sage: R R/a, a da d -sage (a d ) oal delay * /gra (produc of sages) > lr la > Toal delay lr la a d lr,d are cosas > Miimum delay ae (.74) 4.7 Power dissipaio MOS power () Saic dissipaio (leakage curre) + () Dyamic dissipaio (Swichig + rasie curre + charge/discharge ) 4.7. Saic dissipaio >No curre>ps0 Reverse-biased parasiic diodes (leakage curre) 6

17 *eakage curre :i o is (e qv /KT -) 0.A~0.5A per device Where PsΣ is: reverse sauraio curre v: Diode volage leakage curre * supply volage oal devices 4.7. Dyamic Dissipaio 0, 0,p devices are boh o Shor curre pulse from dd o ss 7

18 * Dyamic dissipaio: harge/discharge Pd p/ p i() ou d + p p ip() (dd-ou) d 0 p/ dou i-device rasie curre d d(dd-ou) ipp-device rasie curre d >Pd dd p ou dou + p 0 0 (dd-ou) d(dd-ou) dd 8

19 dd / p * dd * fp 9

20 4.7.3 Shor-circui dissipaio PscImea * dd I mea [ T I() d + 3 T I() d ] Assume -p,ßßpß I mea * T (i()-) d Wih. i() dd r *. dd * r, r,(rfrf) (NMOS ur o) Psc rf (dd-)3 p,fucio of ß,r,f,( ) * PoalPs+Pd+Psc Perceage of aciviy * oal * dd p (simulaor) oal-swich * dd Toal-o-of-cycles * p (AD ool) I * R *Power ecoomy (achieve low-power desig) -Reduce leakage (use complemeary logic + miimize diffusio area) -dd (dd ) - -f clk -Noe dd --> Speed (r,f ) 4.9 harge Sharig 0

21 -Bus is modeled as a capacior b Qbb* b, Qss * s Toal charge : Q T Qb+Qsb*b+s*s Toal capaciace : T b+s Whe swich is closed *If bdd, b>>s b R dd[ b+s ] (Why?) R Q T T b*b+s*s b+s To make reliable rasfer from b o s,s<<b (I geeral, b> 0 s) 4. Yield Fucio of ()echology ()chip area (3)layou No. of oal chip o wafer Yield(Y) Toal o. of chips * 00% (a) Y e AD Achip area (Seed s model) Ddefec desiy (lehal defecs per cm ) (for large chip & Y<30%) -AD - e (b) Y[ AD ] (Murphy s model),for small chips & Y>30%