Plasma Immersion Ion Implantation (PIII)

Transcription

1 Chapter 15 Plasma Immersion Ion Implantation (PIII) Shu Qin Micron Technology, Inc., Boise, ID USA Michael I. Current Current Scientific, San Jose, CA USA Susan B. Felch Silicon Valley Technology Corporation, San Jose, CA USA Nathan W. Cheung UC Berkeley, Berkeley, CA USA Plasma Immersion Ion implantation (PIII) exploits the fundamental advantages of ion implantation using the simplest of systems, direct extraction of ions from a plasma and implantation into a surface that is either inside (or, immersed in) the plasma or at a boundary of the plasma. As such, PIII is one of the oldest of ion implantation techniques as well as an area of vigorous research and development of industrial applications. The efficient transfer of ions from the plasma to the target surface makes it well suited for high-dose implantation for low-energy ions. The principle industrial application for PIII is the doping of poly-si gate electrodes, S/D HDD regions, and S/D contacts in DRAMs. Development issues for the use of PIII for ultrashallow junctions (USJ) and 3-D (FinFET, vertical transistor, etc.) devices are discussed. Chapter Contents Page 1.0 Introduction Plasma Dynamics for DC & Pulsed Plasmas Plasma-Surface Interactions PIII Tool Design Applications References

2 1.0 Introduction 1.1 Early days of plasma immersion ion implantation: Goldstein to Shockley to Mizuno The practice of extracting ions from a plasma and implanting them into a target is the core concept of ion implantation. The earliest study of ions extracted from a plasma is by E. Goldstein in 1886 [Goldstein1886, Freeman86]. Goldstein s apparatus was a glow discharge tube with a grid with multiple apertures at one end [Fig. 1.1]. Figure 1.1 Glow discharge tube of E. Goldstein with ions emerging into the vacuum to the right of a multi-aperture grid [Goldstein1886]. By 1913, J. J. Thompson was investigating the effects of ion penetration into solids, including sputtering [Freeman86]. But it was not until 1954 that W. Shockley filed for a patent [Shockley57] on Forming Semiconductive Devices by Ionic Bombardment using an apparatus that placed a Ge crystal target in front of a beam of ions extracted from a glow discharge BF 3 plasma through a stencil mask [Fig. 1.2]. Figure 1.2 Shockley s ion implantation patent apparatus (1954) with a BF 3 glow discharge and implant mask aperture [Shockely57]. Thirty years later, in the later 1980 s, as J. Conrad was investigating the plasma immersion ion implantation (PIII) techniques for modification of surfaces [Conrad87], B. Mizuno constructed a PIII system at Matsushita for doping of semiconductors [Mizuno88] [Fig. 1.3]. Figure 1.3 Matsushita PIII apparatus (~1987) with an ECR plasma chamber on the right and wafer target platen in the chamber on the left [Mizuno88]. 15-2

3 The early application of the Matsushita PIII system was the doping of trench sidewalls with a 5% B 2 H 6 /He plasma [Fig. 1.4] [Mizuno88]. The uniformity of the doping depth and dose in these 10:1 trenches, which was better than could be achieved by multi-angled implants and a much simpler process, launched the interest in PIII for semiconductor processing that continues to this day [Chu96]. Figure 1.4 SEM image of PIII doped trenches using the Matsushita apparatus [Mizuno88]. The trench openings were 0.45 µm wide and the depth was 4 µm. The applications of PIII for semiconductor materials processing [Fig. 1.5] span an energy range from ~0.1 to ~100 kev and a dose range from ~10 14 to ~10 18 ions/cm 2 and are described in more detail later in this chapter. Plasma doping is currently being used in production for two of these applications (DRAM polysilicon counter-doping and S/D HDD doping) and now represents about 10% of the total market for ion implantation equipment. Varian s PLAD sales for 2007 and 2008 were $64M (out of $1,337M total) and $67M (out of $798M total), respectively [Varian10]. It is estimated that about 100 plasma doping tools have been sold to date to the install base. Dose (ions/cm 2 ) 1E19 1E18 1E17 1E16 1E15 1E14 PIII Process Space SPIMOX (O ) TFT Hydrogenation (H ) Low-k (F,C ) Poly gates (P,B ) S/D Contacts (As, B, N ) S/D & SDE doping (As,B ) Layer transfer (H, He ) Gettering (Ar,He ) PV contacts (As,P) PV doping (P,B ) 1E Energy (kev) Figure 1.5 Applications range for PIII for processing of semiconductor materials. 15-3

4 2.0 Plasma Dynamics for DC & Pulsed Plasmas 2.1 Physics of Plasma Immersion Ion Implantation a Synopsis The physical principle of plasma immersion ion implantation (PIII) is illustrated in Fig By immersing a negatively biased target inside the plasma, electrons will be repelled near the target surface region and a sheath of positive ions will be established. The positive ions will be attracted by the negative target potential and gather kinetic energy while traversing the sheath region. Under collisionless conditions, the maximum implantation energy is approximately the potential sustained by the sheath thickness. As ions are implanted, the sheath will expand to uncover more ions. Replenishment of the positive ions inside the sheath is provided by two mechanisms: (1) from the bulk plasma via a diffusion mechanism through the boundary of the sheath where the ions propagate at the Bohm velocity, (~ 10 5 cm/sec); and (2) by sheath expansion. With efficient plasma sources (e.g., ICP or ECR) to maintain a high ion density ( ions/cm 3 ), one can obtain a high PIII flux of ions/cm 2 per second with DC bias. Plasma wafer Wafer Holder Sheath Region - V ( t ) Figure 2.1 Schematic of a negatively bias target immersed in plasma. The sheath thickness is controlled by the applied bias; increasing with voltage and decreasing with higher plasma ion density. It is important to keep the sheath contained within the reactor chamber and to ensure that sheaths do not overlap between parts in the case of batch processing. The characteristics of the sheath during the PIII process are very important for the optimal design of the PIII configuration and process control. For example, the sheath thickness is critical to the chamber design (chamber size > sheath thickness plus target size for a stable plasma) and monoenergetic ion implantation (s/λ < 1 for collisionless plasma, where s is the sheath thickness and λ is the mean free path of ion-neutral charge exchange collision in the sheath). This is particularly important to applications such as SPIMOX or ion-cutting processes, where a peaked implant profile beneath the surface is desired. Typical PIII processes use pulsed bias waveforms, mainly to avoid the substrate heating problem and the limitations of bias power supply. For substrates containing insulating layers, a pulse bias waveform is necessary to capacitively couple the applied bias to the surface potential. Pulse bias is also required to minimize the voltage drop across thin gate oxides of metal-oxidesemiconductor (MOS) devices during plasma implantation. DC bias or quasi-dc bias (the flat part of each pulse is much longer than the rise-time and fall-time of the pulse) in lieu of pulse bias is desirable for mono-energetic implantation, because the ion-matrix sheath characteristics and the rise-time and fall-time of the high voltage pulse, even in a collisionless plasma, will cause a broadened energy distribution of the implant ions. 15-4

5 Since the PIII technique does not involve ion mass separation, the plasma feed gas and ionization have to be properly chosen for each specific application. The reactor wall has to be constructed with compatible materials to avoid contamination. For high voltage PIII (> 20 kv), X-ray shielding is necessary to block the radiation generated from secondary electrons. The substrate holder has to be designed to avoid electrical arcing and to provide sufficient heat sinking [Iyer96, Iyer97]. 2.2 PIII Modeling There are two dominant methods for PIII modeling. First, and probably most accurate, is Particlein-Cell or similar simulators [Birdsall85]. These simulations make few assumptions, resulting in the most accurate profiles. However, they suffer from long execute times, and generally provide little physical insight. The second method relies on analytical equations and usually assumes that the ion transit time (~ 50 ns) across the sheath is small compared with the rise/fall time of the applied bias [Stewart91, Qin91, Qin92, En94, En95, Chu98]. With this assumption, the implant energy is simply equal to the ion charge times the instantaneous applied voltage. The obvious advantage is the physical insight afforded and the simple extraction of scaling. However, this approach may generate underestimation of the low energy component, especially for very fast rise and fall times of the bias voltage. For these extreme conditions, a more refined model has to be used [Linder01]. For simplicity, we will limit the PIII discussion here to a planar geometry with a single ion specie. A comprehensive discussion on two and three dimensional PIII can be found in the review chapter by Rej et al. [Rej00] and [Qin99]. Comprehensive discussion on multi-ion species and multi-charged PIII modeling can be found in [Qin95, Qin96a]. Effects of dielectric substrates, plasma-induced oxide charging, as well as surface etching and deposition will be discussed in subsequent sections DC or Quasi-DC PIII The DC sheath thickness can be characterized by the well-known Child-Langmuir Law in a onedimensional planar system [Child1911], j i 4 = ε 0 9 2q VS M s 3 / 2 2, and the steady state ion current at the sheath edge with a Bohm acoustic speed 1/ 2 u = B ( qte / M ), and j = q n u, i i B where j i is the ion current density crossing the sheath edge, ε o is the free-space permittivity, q is the ion charge, M is the ion mass, V S is the absolute value of the applied potential, s is the sheath thickness, n i is the ion density, and T e is electron temperature in volts. The steady state sheath thickness s C can be obtained by equating the space-charge-limited current with the steady state ion current at the sheath edge with a Bohm acoustic speed giving [Chu98]: s C 2 2 VS 0 9 = s Te 1/ 4, 15-5

6 in which s 0 is the ion-matrix sheath defined as the sheath formed when t = 0 but t is longer than the electron response time (~ω pe -1 ) and shorter than the ion response time (~ω pi -1 ), and is given by. s 0 = 2 ε 0 q n V i S. We can see that, like the ion-matrix sheath s 0, the DC sheath s C, is independent of the ion species. Fig. 2.2 shows plots of the steady state sheath thickness versus the applied DC potential for different ion densities. For a -50 kv DC potential, the sheath thicknesses are 52.4, 16.6, and 5.24 cm when the ion densities are , , /cm 3, respectively. Figure 2.2 Steady state sheath thickness versus DC biasing for different ion density [Chu98]. After the steady state sheath is determined, the implant ion current, which is also a steady state current, can be obtained directly from the Child-Langmuir Law: j i 4 = ε 0 9 2q VS M s 3 / 2 2, and the implant dose-rate can be calculated by dose-rate = j i /q (at./cm 2 -sec). Fig. 2.3 shows the implant steady state ion current versus DC biasing in an oxygen plasma for the different ion densities when the target is a 150-mm wafer. The ion current is almost independent of the applied potential. For a -50 kv DC potential and a 150-mm wafer, the implant ion currents are 0.01, 0.102, and 1.02 A when the ion densities are , , /cm 3, respectively. The current values translate to implant dose-rates of , , and /cm 2 -sec when the ion densities are , , /cm 3, respectively. 15-6

7 Figure 2.3 Steady-state ion current versus DC biasing in an oxygen plasma for different ion densities when the target is a 6 inch wafer [Chu98]. The plot of λ i versus gas pressure for the case of O (16 amu) in an oxygen plasma is shown in Fig The sheath thickness s is ~17 cm when the potential is -50 kv and the ion density is /cm 3. However, the real sheath thickness is thinner if the two or three-dimensional effect [Qin99] is taken into account and is roughly half of the one-dimension results, that is s ~8 cm. To meet the collisonless assumption, one has to use a gas pressure less than 2 mtorr. MEAN FREE PATH λ i (cm) OPERATING PRESSURE (mtorr) Figure 2.4 Mean free path λ i in an oxygen plasma versus the operating pressure. O is taken as the dominant ion specie in the oxygen plasma [Chu98]. 15-7

8 2.2.2 Pulsed PIII Balancing the Child current density with the uncovered ions due to the moving sheath boundary and the ambipolar diffusion of ions towards the sheath boundary at the Bohm velocity, one obtains: 3/ 2 4 2q VS ds ji = ε 0 = q n, 2 i ub 9 M s dt where V S is the sheath voltage drop and s is the sheath thickness. This equation can be rearranged to solve the time dependence of the sheath thickness s(t) for any time-varying sheath voltage drop V S (t): 1/ 2 2 ds( t) 2 4 ε 0(2q / M ) s ( t) s ( t) u [ V ( t) ] 3 / 2 B = S dt 9 q n Once s(t) is solved, the energy distribution and the ion current density j i can both be determined PIII Current Components The time-dependent total substrate current density J sub consists of four components: J = J J sub ion sec J, elec J disp where J ion is the plasma ion current density, J sec is the secondary electron current density, J elec is the plasma electron current density, and J disp is the displacement current density [Fig. 2.5]. i Figure 2.5. Schematic showing the four current components of the substrate current of PIII. The secondary electron current density has a V S dependence [Szapiro89]: J = α V S J sec ion, with a material constant α. The plasma electron current density can be characterized by a singletemperature Boltzmann distribution: J elec 1 ( qv S / kt e ) 0 ve e = q n 4, 15-8

9 where v e is the average electron velocity. Finally, the displacement current density which includes the currents from the changing sheath potential and the changing sheath capacitance is: dvs J disp = CS V dt S dc dt S, where C S is the sheath capacitance per unit area. To solve the above equations simultaneously requires knowledge of several plasma parameters: the ion density n 0, electron temperature T e, plasma potential V P and floating potential V f. All these plasma parameters can be measured from a single Langmuir probe experiment. Using this methodology, the substrate current density has been accurately predicted for all arbitrary bias waveforms [En96a]. Fig. 2.6 shows the good agreement between substrate current predicted by the plasma model and the measured total substrate current of an aluminum target immersed in an argon plasma. Once the I(t) and V(t) are both known, the energy distribution can be deduced from these data. Figure 2.6 Measured and calculated current pulses for an Ar plasma PIII [En96a] Secondary electron yield Secondary electron yield (γ) for ion-solid interactions is very sensitive to the surface conditions. Data are available for not many ion-target combinations and published results from ion beam experiments may not be representative of PIII conditions [Szapiro89, Holmen81, Svensson81a, Svensson81b, Baragiola78, Alonso80, Delaunay87]. PIII (argon and nitrogen) results on metal targets have been reported by Shamim et al. [Shamim91] up to 40 kv with γ ranging from 5 to 19. En et al. [En96b] reported γ values for Si, SiO 2, Al, and TiN from 2 to 10 with Ar PIII (bias from 2 to 20 kv). Qin et al. [Qin02] used an in-situ Faraday cup to directly measure ion currents and reported γ values on Si substrate from ~ 0.3 to 4 with Ar, He, H 2, BF 3, N 2, O 2 PIII when bias is from 0.5 to 10 kv. All three groups found γ to increase with the V S dependence, in agreement with the Szapiro s results [Fig. 2.7] [Fig. 2.8]. A high secondary electron yield is undesirable in PIII processing because it wastes power of the bias supply, creates heating of chamber walls, and generates X-rays from the chamber wall material. 15-9

10 Figure 2.7 Secondary electron yields with argon PIII [En96a]. Figure 2.8 Secondary electron yield γ i for silicon as a function of incident ion energy. Smooth curves are fits to γ i = A E i (kev ) [Qin02] Construction of energy spectrum from substrate current-voltage waveforms Since measurement of the bias voltage (V) and implanted current (I) waveforms versus time is already a common diagnostic tool in PIII systems, one can use these measured waveforms to derive the energy spectrum of the implanted specie during each implant pulse [Jones97]. From this energy spectrum, the implant profile can be constructed, in principle. The current and voltage waveforms measured during a 5 kv, 5 khz, BF 3 implant are shown in Fig The current waveform is the total current drawn by the implanter, and the bias waveform is measured on the wafer holder. Fig shows the energy spectrum of implanted ions during the 1 µsec, 5 kv PIII pulse. This energy spectrum is obtained assuming the secondary electron yield is known. The energy resolution in the figure is 100 ev; resolution of 10 ev is used for the actual profile construction

11 Figure 2.9 a) Bias waveform applied to PIII wafer holder during implantation showing duration of rise time, on time and fall time of pulse; b) Total current drawn by implanter during application of voltage pulse shown in a). Total current is approximately equal to the ion current plus secondary electron current [Jones97]. The energy spread due to the rise time is not nearly as severe as that due to the fall time. As can be seen from the figure, the long fall time of the wafer bias contributes most to the energy spread of the implant, even though the implant current during the fall time is low and exponentially decreasing. To reduce this spread in the energy the pulse fall time must be reduced. The slow fall time in this PIII system is a function of the matching network, which can be improved to yield more mono-energetic implants. Increasing the pulse on time to make the high energy ions a greater fraction of the total implant dose is not a good solution: when the on-time is increased beyond 1-2 ms, the positive charge deposited on the surface by the implant may be large enough to cause thin oxide charging damage or breakdown [En96c]. Figure 2.10 Energy spectrum of PIII implant, showing dose of ions implanted per energy, assuming ions see instantaneous bias and sheath is collisionless. Energy resolution in figure is 100 ev and minimum energy for ion to implant is taken as 50 ev. Secondary ion yield adjusted for ion species present and substrate material [Jones97]

12 3.0 Plasma-Surface Interactions 3.1 Incorporated Dose with Surface Etching (or Sputtering) and Deposition In the presence of a chemically reactive plasma, the substrate can be removed by reactive ion etching (common with a fluoride plasma like BF 3 ) or have a thin deposited surface layer (common with hydride plasmas such as B 2 H 6 and AsH 3 ) [Shao95, Qin96, Qin07, Qin09a, Qin09b, Qin12a]. Enhanced oxidation can also occur due to the large number of broken bonds created by the near-surface damage, and this can have the same end effect as chemical etching after the oxide is removed during photoresist strip and clean [Qin09c, Qin10a]. For PIII dosimetry control and Si surface structure, both etching and deposition have to be minimized. The concomitant occurrence of implantation and etching can change the accumulative implantation profile because the solid surface recedes continuously during the implantation. Let g(x) be the implantation profile per unit time and v (>0) be the substrate etching rate. The accumulated implantation profile C(x, t) after an implantation time t is a simple convolution [Shao95]: t C (x, t) = g(x-vt')dt' 0 Since there is substrate material being removed, the retained dose in the substrate is: Q (t) = C(x,t)dx vt Under steady-state conditions (i.e., t ), the incorporated dose will asymptotically reach a constant value, independent of the total implantation dose. Similar to the etching case, any thin film deposited on the substrate surface during implantation also affects the overall implantation profile. With v<0, the C (x, t) and Q (t) expressions are: t C (x, t) = g(x-vt')dt' 0 and Q (t) = C(x,t)dx 0 The accumulated implantation profiles for etching and deposition situations are illustrated in Fig Figure 3.1 Schematic illustration of simultaneous plasma a) etching or b) deposition during PIII, and the effect on incorporated dose in the substrate

13 Predicting apriori the amount and direction of surface erosion (sputtering/etching) or deposition is very difficult. Illustrated in Figs. 3.2 and 3.3, angle-resolved x-ray photoelectron spectroscopy (ARXPS) technique was used to evaluate surface sputtering/etching and deposition. Fig. 3.2 shows erosion and deposition data for p-type (boron-based) low energy doping techniques, including conventional mono-atomic 11 B beam-line ion implant, molecular beam-line ion implants, cluster B implant, and plasma doping [Qin09a]. Plasma doping processes using B 2 H 6 and BF 3 gas species have deposition, with 10.4 nm and 3.4 nm, respectively, under the current process conditions and demonstrate different deposition mechanisms and materials. BF 3 PIII in other tools showed a net etching (RIE behavior) [Shao95, Qin96]. Fig. 3.3 shows erosion and deposition for various energies of As and P implants in a beam-line and As PIII doping [Qin09b]. While the 10 kev As beam-line implant resulted in 4.5 nm of surface erosion due to self-sputtering, a 10 kv As implant from a AsH 3 PIII tool resulted in deposition of a 1.5 nm thick polymer-dopant film. 12 Self-Sputtering/Deposition (nm) As-Implanted Beam-line B2keV/5e15 or Equivalent -4 Beamline B (11) Beamline BF2 (49) Beamline C2B10H12 (146) Beamline B18H22 (220) Beamline Cluster B ( 1000) PLAD B2H6 ( 28) PLAD BF3 ( 68) Figure 3.2 Self-sputtering/deposition data of different B-based doping techniques. Negative number shows self-sputtering and RIE and positive number shows deposition. The numbers beneath the implant types are corresponding ion species AMU (Atomic Mass Unit) [Qin09a]. 3 Self-Sputtering/Deposition (nm) Beamline As 10keV/5e15 (75) Beamline As 4keV/5e15 (75) Beamline As 1keV/5e15 (75) Beamline P 10keV/5e15 (31) Beamline P 4keV/5e15 (31) Beamline P 1keV/5e15 (31) PLAD AsH3 3 10kV/5e15 (~75) Figure 3.3 Net surface erosion and deposition for various As and P beam-line implants and a 10 kv As PIII implant, all at a dose of 5E15 ions/cm 2 [Qin09b]

14 3.2 Plasma Induced Oxide Charging During PIII, both ions and electrons bombard the surface of the wafer (Fig. 3.4). With nonuniform plasma parameters over the wafer surface, the ion and electron currents do not balance, and charge will build up on the surface of the wafer. The interconnects conduct this charge from the wafer surface down to the transistor gate, electrically stressing the gate oxide. A large enough electrical field creates tunneling currents. These currents break bonds in the gate dielectric, degrading the bulk and interface properties of the oxide. Figure 3.4 During PIII, ions and electrons bombard the wafer surface (1). Often, the fluxes are not completely balanced, and a charge builds up on the surface. The surface conductor transfers the charge from the surface to the poly layer (2). If the electric field generated by this conducted charge is great enough, tunneling currents flow through the gate oxide, resulting in electrical stress, which is called plasma damage [En96c]. Thin-oxide charging damage in MOS capacitors processed by PIII has been experimentally measured by monitoring the interface trap density (Q it ) using capacitance-voltage (C-V) techniques [En96c]. The plasma sheath model predicts, for the given plasma and capacitor structure, that the magnitude of the voltage drop across the gate oxide will decrease as the frequency of the voltage pulses increases up to a particular threshold frequency. The threshold frequency ( 10 khz) denotes the transition from surface electron accumulation to surface ion accumulation, which causes the oxide voltage drop (V ox ) to change sign and increase rapidly [Fig. 3.5]. By setting a certain oxide damage budget, one can predict the optimum waveform (frequency and duty factor) for various plasma conditions. The fall-time of the PIII pulse has been identified to be crucial for oxide damage and should be minimized. Antenna effects on oxide charging can also be modeled using this methodology [En96e]. For a given pulsed waveform, simulation shows that a lower plasma electron temperature generates a smaller plasma potential, which will allow the electrons to reach the surface more quickly during the pulse-off cycle. This effect will push the threshold frequency for ion accumulation to higher frequency values. Hence, plasmas with lower electron temperature will be desirable to enhance the throughput [En96d]

15 Figure 3.5 Comparison between simulation and experiment for the dependence of oxide charging damage on pulse repetition rate. The simulation curve shows the relationship of V ox for a 10 nm gate oxide as a function of pulse repetition rate, and the experimental curve of the interface trap density (Q it ) for six different pulse repetition rates correlates qualitatively with the simulation results [En96c]. The recent trend for MOS devices is to scale the oxide thickness to below 2 nm. With direct tunneling shunting the oxide leakage current, oxide stressing during plasma processing is more forgiving. Recent work by Linder et al. [En97b, Linder99a] has verified that oxide damage due to PIII is still a function of antenna ratio, but shifting to thinner oxides with larger antenna ratio. The data in Fig. 3.6 show that extreme stressing environments with high ion densities and large antennas can damage ultra-thin oxides. On the other hand with smaller antennas and lower stressing conditions, the thinner oxides appear more robust. Figure 3.6 PIII charging damage measured by SILC peaks as gate oxides are scaled thinner. Damage is found to be a function of antenna ratio (AR), with larger AR s shifting the peak to thinner oxides

16 3.3 PIII plasma chemistry and dopant profiles PIII or PLAD (plasma doping) technology has been utilized in the current advanced microelectronics and is a promising doping technique in the next generation microelectronics. However, PIII shows very different impurity profiles to the conventional beam-line-based ion implantations due to its non-mass separation property and plasma environment with multi-ion species and multi-energetic implant. There is no simulation for PLAD process so far due to a lack of a dopant profile model. Mixture of so many different kind species including charged particles (electrons and ions) and radicals and mixture of the implant, deposition, etch/sputtering, and RIE (reactive ion etching) processes make PLAD profile modeling extremely difficult. Several factors determine impurity profiles of PIII process: 1) plasma chemistry; 2) etching/deposition characteristics, and 3) energy distribution caused by collisions in collisional plasma and rise time/fall time of the bias. Plasma chemistry and deposition/etching characteristics studies are essential to predict PIII dopant profiles PIII plasma chemistry measurements by ion mass spectroscopy and ARXPS The most significant factors to determine the impurity profiles of PLAD process if considering a collisionless case are: plasma chemistry and deposition/etching characteristics of multi-ion species plasmas. Co-gas such as H 2 or He dilutions with plasma gases were often used for process stabilization and toxicity control purposes in PLAD processes. Another purpose of co-gas dilution is to minimize or control deposition and etching. Therefore, the plasma chemistry and deposition/etching characteristics can be varied and adjustable. The plasma chemistry and deposition/etching characteristics of PLAD processes were studied versus co-gas dilutions. The plasma chemistry was measured by ion mass/energy spectroscopy. Deposition/etching characteristics was measured by ARXPS. Four dopant species plasmas including B 2 H 6, BF 3, AsH 3, and PH 3, two non-dopant species plasmas including CH 4 and GeH 4 are studied and demonstrated [Qin12a]. Hiden EQP Ion Mass/Energy Analyzer was used to measure PIII plasma chemistry. Fig. 3.7 shows ion mass spectra of B 2 H 6 PLAD processes when the voltage is -6 kv, RF power is 725 W, and pressure is 6 mtorr for B 2 H 6 /H 2 gas ratio is (A) 2/98 and (B) 15/85 [Qin08, Qin12a]. Both B- based and H-based ions are dominated, and the ion compositions are strongly dependent on H 2 dilution. Fig. 3.8 shows B 2 H 6 PIII ion composition versus B 2 H 6 /H 2 gas ratio when the voltage is -6 kv, RF power is 725 W, and pressure is 6 mtorr. Two interesting features have been demonstrated: 1) B-based ions are only a fraction of the total ions in the plasma, therefore, the implanted B retained dose into the substrate is only a fraction of the implanted nominal dose; and 2) B 2 H y ions, or called dimer ions, are always majority in B-based ions. B-based ions increase with the higher B 2 H 6 /H 2 gas ratio. B 2 H y ions also increase with the higher B 2 H 6 /H 2 gas ratio. When B 2 H 6 gas is 2%, the B-based ions are only ~16%, and the H-based ions are majority 84% of the total ions. B 2 H y ions are 13% and BH y ions are 3% of the total ions. When B 2 H 6 gas is 15%, the B- based ions increase to ~42% and H-based ions are 58% of the total ions. B 2 H y ions increase to ~35% and BH y ions are 7% of the total ions. Higher B 2 H 6 /H 2 gas ratio shows a higher B doping efficiency due to more B and B-based dimer ions created. The B profile in substrate is a superposition of the profiles of the different B species. However, when the B 2 H 6 /H 2 gas ratio increases, as shown in Fig. 3.9, B deposition increases significantly and the retained B dose in Si substrate will reduce and the B profile will vary because the B deposition layer will block and trap B ions. The final B profile and dose will be determined by the B ion composition and the deposition characteristics

17 Intensity (c/s) 8.E03 6.E03 4.E03 2.E03 H y B 2 H 6 /H 2 (2%) PLAD, -6kV, 6mT, 725W (A) BH y B 2 H y H y = 83.8% BH y = 2.9% B 2 H y = 13.3% B 3 H y B 4 H y Intensity (c/s) 4.E03 3.E03 2.E03 1.E03 B 2 H 6 /H 2 (15%) PLAD, -6kV, 6mT, 725W H y (B) BH y B 2 H y H y = 58.3% BH y = 7.1% B 2 H y = 34.6% B 3 H y B 4 H y 0.E Ion Mass (amu) 0.E Ion Mass (amu) Figure 3.7 Ion mass spectra of B 2 H 6 PLAD processes when the voltage is -6 kv, RF power is 725 W, and pressure is 6 mtorr for B 2 H 6 /H 2 gas ratio is (A) 2/98 and (B) 15/85, which are measured by Hiden EQP ion mass/energy analyzer [Qin12a]. 100 B 2 H 6 PLAD, -6kV, 6mT, 725W B 2 H 6 Plasma Ion Composition (%) Hy H y BHy BH y B2Hy B 2 H y 1/99 (1%) 2/98 (2%) 5/95 (5%) 10/90 (10%) 15/85 (15%) B 2 H 6 /H 2 Gas Ratio Figure 3.8 B 2 H 6 PLAD ion composition versus B 2 H 6 /H 2 gas ratio when the voltage is -6 kv, RF power is 725 W, and pressure is 6 mtorr [Qin12a]. B Deposition Thickness (nm) B 2 H 6 PLAD, -6kV/1E16, 6mT, 725W 1/99 (1%) 2/98 (2%) 5/95 (5%) 10/90 (10%) 15/85 (15%) B 2 H 6 /H 2 Gas Ratio Figure 3.9 B deposition versus B 2 H 6 /H 2 gas ratio when the voltage is -6 kv, RF power is 725 W, and pressure is 6 mtorr, which are measured by ARXPS method [Qin12a]

18 Fig shows ion mass spectra of AsH 3 PLAD processes when the voltage is -5 kv, RF power is 725 W, and pressure is 6 mtorr for AsH 3 /H 2 gas ratio is (A) 2/98 and (B) 15/85 [Qin12a]. Fig shows AsH 3 PIII ion composition versus AsH 3 /H 2 gas ratio when the voltage is -5 kv, RF power is 700 W, and pressure is 6 mtorr. Differing from the B 2 H 6 PLAD process, two interesting features have been demonstrated: 1) As-based ions are always majority and H-based ions can be negligible; and 2) AsH y ions are majority in the As-based ions. This means that Asbased ions are close to the total ions in plasma. Therefore, the implanted As retained dose into the substrate is close to the implanted nominal dose. It noted that As 2 H y ions, or called dimer ions, increase with the higher AsH 3 /H 2 gas ratio, which could be beneficial on productivity because the implanted As retained dose could be larger than the implanted nominal dose due to more dimer ions. As shown in Fig. 3.12, As deposition is less and weakly dependent on the H 2 dilution, comparing with the B 2 H 6 PLAD case. Intensity (c/s) 7.E03 6.E03 (A) 5.E03 4.E03 3.E03 2.E03 1.E03H 3 (3) AsH 3 /H 2 (2%) PLAD, -5kV, 6mT, 700W AsH (76) AsH 2 (77) AsH 3 (78) H y = 0.6% AsH y = 91.4% As 2 H y = 8.0% As 2 H (151) Intensity (c/s) 3.0E04 2.5E04 2.0E04 1.5E04 1.0E04 5.0E03 H y (B) AsH 3 /H 2 (15%) PLAD, -5kV, 6mT, 700W AsH y H y = 0.5% AsH y = 76.2% As 2 H y = 23.3% As 2 H y 0.E Ion Mass (amu) 0.0E Ion Mass (amu) Figure 3.10 Ion mass spectra of AsH 3 PLAD processes when the voltage is -5 kv, RF power is 700 W, and pressure is 6mTorr for AsH 3 /H 2 gas ratio is (A) 2/98 and (B) 15/85, which are measured by Hiden EQP ion mass/energy analyzer [Qin12a]. 100 AsH 3 PLAD, -5kV, 6mT, 700W AsH 3 Plasma Ion Composition (%) Hy H y AsHy y As2Hy 2 H y 1/99 (1%) 2/98 (2%) 5/95 (5%) 10/90 (10%) 15/85 (15%) 20/80 (20%) AsH 3 /H 2 Gas Ratio Figure 3.11 AsH 3 PLAD ion composition versus AsH 3 /H 2 gas ratio when the voltage is -5 kv, RF power is 700 W, and pressure is 6 mtorr [Qin12a]

19 8 AsH 3 PLAD, -5kV/5E15, 6mT, 700W As Deposition Thickness (nm) /99 (1%) 2/98 (2%) 5/95 (5%) 10/90 (10%) 15/85 (15%) 20/80 (20%) AsH 3 /H 2 Gas Ratio Figure 3.12 As deposition versus AsH 3 /H 2 gas ratio when the voltage is -5 kv, RF power is 700 W, and pressure is 6 mtorr, which are measured by ARXPS method [Qin12a] More accurate dopant dose and profile measurement using SIMS/ARXPS method PIII is a more complicated process than conventional ion implantation because of its plasma environment and non-mass-analyzed feature. PIII process is a combination of ion implantation, deposition, and etching (including chemical etching and physical sputtering) depending upon the plasma species and processing conditions. It is very critical to accurately determine the doping results including the retained dopant profiles, which determine the junction depth and abruptness, and the retained dopant doses, which determine the values of R S, for the ultra-low energy implants. These critical requirements are particularly relevant for PIII because PIII have some unique properties compared with the conventional beam-line implants. These unique properties include a different impurity profile and more surface treatments, with potential deposition and etching effects besides the ion implant. A surface measurement by combining SIMS technique with Angle-Resolved XPS (ARXPS) technique, called SIMS/ARXPS method, is developed to overcome the transient effect of the SIMS measurement and achieve more accurate results of the impurity profiles and doses for low energy implant including conventional beam-line implant and PIII [Qin09c]. Because the SIMS results near surface may not be correct due to the sputtering effects mentioned above, we use ARXPS to determine the surface chemical composition, and in turn, the surface material, for example, a possible native oxide, and the doping profile and dose near the surface. As long as the native oxide is decoupled by ARXPS, the conventional SIMS technique is used to determine the doping profile and dose in Si substrate [Qin09c, Qin10b, Qin10c]. Fig shows SIMS/ARXPS depth profiles of B for different ultra-low energy doping techniques on (A) as-implanted wafers and (B) annealed wafers. The ultra-low energy doping techniques include beam-line atomic 11 B implant; BF 2, C 2 B 10 H 12 molecular implants; cluster B (B 18 H 22 ) implant; gas cluster ion beam (GCIB); and B 2 H 6 and BF 3 PLAD implants. The implant conditions are B 500 ev energy and /cm 2 B dose with 0-degree tilt angle or equivalent. The native oxide thickness is defined and decoupled by ARXPS measurement. The native oxide is always re-grown after a strip/clean as long as Si fresh surface exposed to the atmosphere for a period of time (minutes to hours). Native oxide thickness plays a very significant role in ultra-low energy implants; not only does it determine impurity loss and final B profiles, but it also impacts the post-implant, pre-metallization strip and clean processes. Several factors affect the native oxide re-grown thickness. Higher doping level and surface roughness can enhance native oxidation. B loss into the surface native oxides is more severe in the ultra-low energy PIII regime

20 The native oxide of PLAD processed Si wafers is relatively thicker than that of the beam-linebased implants and PLAD loses more impurities into native oxide due to PLAD s much higher surface impurity concentration. BF 3 PLAD has the highest B concentration peak near the surface and cause thicker native oxide. For beam-line implants, around ~1/2 of the total implanted B doses are trapped and lost into the native oxides. B 2 H 6 and BF 3 PLAD implants lost 2/3 and 4/5, respectively, of the total implanted B doses due to PLAD s unique exponential-like B profiles. The B components in the native oxide must be extracted from the total B dose because the B dose in the oxide cannot be activated and will be lost by subsequent clean processes, such as pre-clean for metal contact deposition. The B loss into native oxides is a main mechanism of B loss for both as-implanted and annealed wafers. B Concentration (atoms/cm 3 ) 1E23 1E22 1E21 1E20 1E19 1E18 1E17 (A) Cluster B,5.2e14 C 2 B 10 H 12,5.04e14 Native Ox B 18 H 22,5.8e14 BF 2,5.96e14 11 B,5.2e14 Beam-line B500eV/1E15 or Eq. As-Implanted PLAD B 2 H 6,9.6e14 PLAD BF 3,8.0e14 Xj(5e18) Depth (nm) B Concentration (atoms/cm 3 ) 1E23 1E22 1E21 1E20 1E19 1E18 1E17 (B) Cluster B,5.0e14 Native Ox 11 B,5.14e14 C 2B 10H 12,4.5e14 BF 2,4.04E14 Beam-line B500eV/1E15 or Eq. RTP: 1000ºC/spike B 18 H 22,5.4e14 PLAD B 2 H 6,7.8e14 PLAD BF 3,6.2e14 Bss: 1.8e20 xj(5e18) Depth (nm) Figure 3.13 SIMS/ARXPS B profiles of different doping techniques on (A) as-implanted wafers and (B) annealed wafers [Qin10c]. 4.0 PIII Tool Designs All commercial plasma doping tools today use some type of inductively coupled (ICP) plasma source. Figs. 4.1 to 4.4 show schematics of four commercial plasma doping tools and the locations of their plasma sources. These plasma sources consist of an RF generator at or 2 MHz [Torregrosa06, Renau10] and RF coils that generate a magnetic field, which create and confine the high density plasma. One unique type of remote ICP source used is the toroidal plasma source [AMAT ]. Horizontal and vertical coils can be used to optimize the plasma uniformity (Fig. 4.1). The RF generator can even be pulsed to produce a pulsed plasma, as illustrated in Fig. 4.2, which can help to minimize particle generation due to nucleation in BF 3 plasmas. The early plasma doping tools used a glow discharge plasma, which was created by the same pulsed voltage used to bias the wafer being implanted. However, a minimum voltage of 0.5 kv and a relatively high working pressure of > 50 mtorr are required to ignite and sustain such a plasma, so this technique is not compatible with the voltages needed (<0.5 kv) for present day and future ultra-shallow junction implants

21 Figure 4.1 Schematic view of a PLAD (PLAsma Doping) chamber [Renau10]. Figure 4.2 Schematic view of a PULSION chamber [courtesy of Ion Beam Services]

22 Figure 4.3 Schematic view of a LEDA chamber [courtesy of SEN]. The other key component of plasma doping tools is the negative voltage applied to the wafer, which accelerates the positive ions from the plasma, across the plasma sheath, and into the wafer surface, as shown in Figs. 4.1 to 4.4. The magnitude of this wafer bias determines the implant energy. Since the wafer sits on a cooled electrostatic chuck, the voltage is usually applied through special pins that are located in holes through the chuck and contact the wafer at multiple points. Many plasma doping tools use a bias supply with a square wave (pulsed DC) [Renau10], while an RF self-bias is implemented on other tools [Mizuno88, AMAT , Fuse11]. A gas containing the desired species to be implanted is introduced into the plasma source. Common dopant gases are BF 3, B 2 H 6, AsH 3, and PH 3. The choice between fluoride and hydride gas depends on the effects of the co-implanted F or H and whether a certain amount of etching, enhanced oxidation, or deposition is problematic (also see the discussion in Section 3.1). GeH 4, GeF 4, SiH 4, and SiF 4 can be used for PAI (pre-amorphization implant), while CH 4 and CF 4 can be used to co-implant C to retard diffusion of B or P dopants during anneal. All of these gases can also be used for materials modification, as well as N 2, O 2, He, H 2, Ar, F 2, etc. Typical chamber pressures range from 0.1 to 500 mtorr, while gas flow rates vary between 1 and 500 sccm. The choice of plasma gas feed affects the shape of the accumulated dose profile, especially at high doses. As shown in Fig. 4.5, the near surface accumulation of B dopants is quite pronounced with the use of B 2 H 6 gas and not noticeable in B profiles from BF 3 plasmas [Spiegel10]

23 Figure 4.5. SIMS profiles of Boron using B 2 H 6 (left) and BF 3 (right) in an IBS Pulsion tool for a dose of to 5x10 16 or ions/cm 2. The wafer bias for the B 2 H 6 implants was 3 kv and 6.5 kv for the BF 3 profiles [Speigel10]. Plasma doping chambers use several different approaches to improve the uniformity of the number of ions implanted and their energy. Some of these are illustrated in Figs. 4.1 and 4.2. The electrostatic plane of the wafer can be enlarged by adding a biased shield ring around the wafer chuck or by extending the diameter of the conducting surface of the chuck beyond the wafer. This improves the uniformity of the electric field responsible for the ion implantation near the wafer edge. The uniformity of the gas flow and plasma can be improved by introducing the gas into the plasma source through a showerhead [AMAT ] or baffle [Renau10]. The baffle can also be grounded to serve as an anode, which can additionally help the electric field uniformity. Finally, wafer rotation can be used to smooth out azimuthal non-uniformities due to differences around the chamber diameter, and a taller chamber can minimize plasma nonuniformities [Torregrossa06]. Plasma doping tools also have special features to minimize contamination. Some chambers use removable liners, so that the plasma sees a less-contaminating surface than the aluminum chamber walls and the liner can be periodically cleaned as deposits accumulate to an unacceptable level. Water cooling of the chamber walls can also be used to minimize deposition on the walls. Finally, a clean/season sequence can be added to the processing of every wafer, so that each wafer sees the same, clean coating of the chamber walls [AMAT ]. In this case, a second plasma source and side gas injectors create plasmas in the process chamber that first remove ( clean ) the existing film on the chamber walls and then deposit ( season ) a new film. Several different techniques for dosimetry have been implemented in today s plasma doping tools [EATON , VSEA , VSEA ]. In the PLAD tool, the wafer is surrounded by a magnetically suppressed annular Faraday, which provides a real-time measurement of the positive ion current to the wafer (Fig. 4.1). Other tools integrate the current flowing through the wafer and high voltage power supply, but this current includes the secondary electrons emitted by the wafer surface as well as the positive ions being implanted. Recently optical emission spectroscopy, residual gas analysis, ion mass spectroscopy, and time-of-flight ion sensors have been added in conjunction with the two techniques described above to measure the total dose and the dose of each component being implanted (e.g. B, BF, BF 2, and F ions with a BF 3 plasma, or BH y, B 2 H y, and H y ions with a B 2 H 6 plasma) [Qin08, MICRON ]. For all of these techniques, the measured signal is typically monitored automatically to stop the implant process at a pre-set value to provide process control and repeatability

24 Commercial plasma doping tools are usually configured as cluster tools with 2 to 4 process chambers. All of the process chambers can be plasma doping ones, or there can be a combination of plasma doping, annealing, and photoresist strip chambers. The maximum throughput of these tools is about 200 wafers per hour, although the actual throughput is usually limited by plasma stabilization time and the process time for very high doses used. Today s dual-chamber tools typically achieve about wafers per hour (WPH) for the DRAM poly-silicon gate doping and SD (source and drain) HDD (highly-doped drain) doping applications. 5.0 Applications 5.0 Doping and Modification of Semiconductors: Shallow Junctions In 2014, the semiconductor device industry is engaged in fabrication of devices for the 22 nm technology node with physical gate lengths of under 20 nm. These devices require source/drain extension junction depths 10 nm. Beam-line implantation using 5 kev BF 2 was used for the first reported 50 nm gate CMOS transistors in 1994 [Hori94]. Plasma doping was proposed as an alternative for its promise to dramatically lower the cost of ownership (COO) for advanced LSI device manufacturers designing 0.1 micron devices under the condition of retail price collapse [Mizuno88, Mizuno96, Takase97]. In 1998 Ha and Felch demonstrated good results with plasma doping, including gate oxide reliability and compatibility of silicidation with plasma doping [Ha98]. These commercial considerations and technical developments have been summarized in several reviews [Mizuno99, Mizuno00, Mizuno02, Chu99, Felch02 Decreasing the wafer bias will result in a shallower, as-implanted dopant profile. This effect is illustrated in Fig. 5.1 for BF 3 plasma doping, where the junction depth (X j ) measured by SIMS at B cm -3 is plotted for several wafer biases [Goeckner99]. The approximate doses for all implants were B cm -2. As seen in the figure, X j is a linear function of bias over a range from 0.14 kv to 5 kv. This fit suggests that the as-implanted junction depth decreases 125 Å for every 1 kv reduction in bias f(x) = 125 x 56 R^2 = X j (Å) Enlarged area Implant Bias (kv) Figure 5.1 Junction depth, X j, as a function of implant bias [Goeckner99]

25 5.1 Doping of DRAM p-type Poly-Si Gates Almost all of today s DRAM devices use plasma doping in production to counter-dope the polysilicon gates of the peripheral PMOS transistors. This implant step is often called Poly Counter-Doping or Dual Poly Doping (DPG), due to the different doping methods for the n- and p-type poly gates. The polysilicon for both types of gates is in-situ doped with phosphorus during the LPCVD process. Then, BF 3 plasma doping is used to convert the PMOS gates to heavily p- type. The wafer bias is chosen to implant boron to the bottom of the gate but not enable any dopant to penetrate the gate dielectric and end up in the channel of the transistor. For this reason, the minimum channeling effect and lack of high energy contamination make plasma doping extremely attractive over beam-line implantation, which intrinsically has channeling effect and would require drift mode (with its low beam currents) to be energy contamination-free. Typical production processes use wafer biases of 3-7 kv and implant doses of cm -2. Since the anneal temperature is limited to C due to its late placement in the device process flow, an extremely high dose is required to achieve sufficient electrically active boron at the poly/gate dielectric interface, in the poly depletion region. Even though plasma doping is dominant for this application today, matching implant recipes between different chambers or between different types of tools requires considerable care due to the many electrical parameters that must be matched, such as ring oscillator delay, poly depletion layer thickness and threshold voltage (Fig. 5.2). Figure 5.2 Boron poly-si gate doping for -6 kv PLAD (using B 2 H 6 ) and 2 kev B beamline implants (left) and normalized poly-gate depletion thickness comparison (right). The B peaks at 700 Å are at the gate oxide boundary at the bottom of the poly-si gate [Fang06]. 5.2 S/D Region Doping S/D HDD p -type doping for PMOS device S/D HDD (highly-doped drain) doping is another application of plasma doping that has entered DRAM manufacturing. This boron implant places dopant into the S/D (source/drain) regions of the PMOS periphery transistors. B 2 H 6 is usually used for the precursor, since the co-implanted fluorine with BF 3 would lead to contact reliability problems, although some manufacturers are using BF 3 for this application. Micron used B 2 H 6 PLAD with a typical wafer bias of -6 kv, and a nominal dose of cm -2, slightly lower than those used for poly counter-doping, to match a conventional beam-line counterpart of B ion implant with a energy of 2 kev and a dose of cm -2. The experiment has shown that plasma doping reduces the contact resistance by 15-25

26 ~50% and increases the conducting current I DS by ~15% compared to beam-line implant (Fig. 5.3) [Qin07]. B Concentration (atoms/cm 3 ) 1E23 1E22 1E21 1E20 1E19 1E18 (A) As-implanted PLAD 6kV/2e16, 1.2e16 Beamline II control 2keV/4.5e15, 6.5e Depth (nm) B Concentration (atoms/cm 3 ) 1E23 1E22 1E21 1E20 1E19 1E18 (B) Annealed 965 ºC/20 s PLAD 6kV/2e16, 9.1e15 Beamline II control 2keV/4.5e15, 6.e15 B SS 1.4e Depth (nm) Figure 5.3 (A) As-implanted and (B) annealed S/D B profiles for a -6 kv voltage and cm -2 dose B 2 H 6 PLAD and a 2 kev energy and cm -2 dose B beam-line implants. Note the much higher surface dopant concentration for the PLAD doping case [Qin07]. Norm. R CS Norm. I DS Beamline II Control PLAD 0.4 Beamline II Control PLAD Norm. I OFF Figure 5.4 Normalized contact resistance R CS (left) and conducting current I DS versus off current I OFF characteristics (right) of S/D doping of PMOS devices [Qin07] S/D HDD n -type doping for NMOS device PLAD for n S/D HDD doping used AsH 3 dopant gas with nominal implant voltage and dose of kv and cm -2, respectively. The process conditions used for conventional beam-line ion implantation are 75 As, energy 10 kev, dose cm -2, and implant angle 0º. The experiment has shown that plasma doping reduces the contact resistance by ~20% and increases the conducting current I DS by ~8% compared to beam-line implant (Fig. 5.5) [Qin08a]

27 Norm. NCH R SD, R CS R SD RSD Beamline II R SD Beamline II Control RSD Plasma Doping R CS R CS RCS Beamline II RCS Plasma Doping Plasma Doping Norm. NCH I DS Beamline II Control Plasma Doping Linear (Beamline II Control) Linear (Plasma Doping) Norm. NCH V T Figure 5.5 Normalized contact resistance R CS and R SD (left) and conducting current I DS versus threshold voltage V T characteristics (right) of S/D doping of NMOS devices [Qin08a] S/D BC (buried contact) doping For ultra-shallow junction (USJ)-based CMOS transistors, suitable values of threshold voltage (V T ), sub-threshold voltage (SV T ), and high drive current (I DS ) with low device off current (I OFF ) are essential for high-performance ICs, including logic and memory circuits. The sum of the series resistance in source/drain (S/D) regions (R SD ) and the contact resistance (R CS ) between S/D regions and conductive interconnects is one of the limitations of I DS. With device scaling, the contact resistance (R CS ) is becoming a larger portion of the overall parasitic resistance that directly impacts I DS. R CS is degrading rapidly as the devices continue to shrink due to the contact area decreases with a function of square power on the scaling factor. There are several techniques already deployed in logic and memory to reduce R CS and increase I DS, such as cobalt and nickel silicided active areas. However, issues such as integration difficulty and higher cost are present with these options. The use of an additional implant into the active area contacts, prior to contact metallization, will be referred to as a buried contact (BC) implant. There are several motivations for this BC implant: to compensate impurity loss during contact area etching and cleaning, and increase impurity concentration at the metal/si interface without negatively impacting junction characteristics such as V T, SV T, breakdown voltages, and leakages. After the normal S/D HDD regions formed, the BC implants was processed through the contact opening down to the S/D regions followed by a PVD Ti/CVD W-based metallization. The wafers were then processed through a local interconnect flow to allow for electrical testing. TABLE 5.1 lists the experiment matrix. The implant times for each split are also listed in TABLE 5.1 and demonstrate the benefit of PLAD on productivity [Qin12]. TABLE 5.1 MATRIX TABLE OF BC IMPLANT EXPERIMENTS P BC IMPLANT Implant Time (sec) 1C POR Control (No BC Implant) None 2E BL B 1keV/3x E PLAD BF 3 2kV/2x E PLAD B 2 H 6 2kV/2x The PMOS transistor parameters were measured and evaluated extensively. Fig. 5.6 (left) compares R CS of the PMOS SD regions with metal conductive interconnects. The R CS of devices processed by BC implants are ~70% lower than those without BC implant. It is believed that the 15-27

28 reduction in R CS is a result of the higher B concentration near the metal/si interface. Additionally, it is shown that group 4E shows a much tighter distribution. Fig. 5.6 (right) shows I DS versus I OFF performance curves of a PMOS device. It has demonstrated that I OFF has no degradation, but the I DS of PMOS devices processed by the BC implants show ~15% increase over the POR. Other device parameters such as breakdown voltages between source and drain BV SD, threshold voltage V T, sub-threshold voltage SV T have almost no change. Norm. Contact Resistance R CS POR no BC Implant BL B 1keV/1x10 15 PMOS STANDARD DEVICE(80X1) PLAD BF 3 2kV/2x10 16 PLAD B 2 H 6 2kV/2x Norm. I DS POR no BC Implant BL B 1keV/3E15 PLAD BF3 2kV/2E16 PLAD B2H6 2kV/2E Norm. I OFF PMOS STANDARD DEVICE(80X1) Figure 5.6 Normalized contact resistance R CS (left) and conducting current I DS versus off current I OFF characteristics (right) of S/D BC doping of PMOS devices [Qin12] Optimized Ge co-implant with B 2 H 6 PLAD on PMOS S/D doping For the advanced PMOS S/D doping, B 2 H 6 PLAD is replacing B beam-line implant in order to meet the requirements for both technology and manufacture productivity. It is critical for B 2 H 6 PLAD to continue scaling down the junction depth while still improve PMOS device performance. It has been demonstrated that the sequence of the Ge co-implant with B 2 H 6 PLAD was very critical in order to improve the advanced PMOS performance. Ge implant after B 2 H 6 PLAD improved PMOS performance more significantly than Ge implant before B 2 H 6 PLAD due to less implant damage and higher total retained B dose. Ge implant energy was optimized to locate Ge peak around B deposition layer/si substrate for better knock-on effect and less implant damage. With the optimized Ge implant conditions, the S/D Rc and Rs were significantly reduced while the junction leakage current was not degraded. As a result, the advanced PMOS performance is improved with 12% better I DS, 14% better trans-conductance KL, similar I OFF mean but 33% better I OFF variation. The SCE, GIDL and V T roll off were not impacted at the same time. This process may help to overcome the technical challenges for B 2 H 6 PLAD, and continue scaling down the junction depth with even better device performance for the advanced PMOS devices [Liu13]. The advanced PMOS device wafers were implanted by B 2 H 6 PLAD process with Ge co-implant to form p S/D regions. The doping gas was B 2 H 6 /H 2 with the nominal implant voltage at -2.5kV and dose at cm -2, respectively. Ge implant was processed by Ge ion beam-line implant with different energy from 5 kev to 10 kev and dose at cm -2, respectively. Ge implant was placed right before or right after B 2 H 6 PLAD implant on purpose for the design of the experiments. The n-type single-crystalline Si blanket monitoring wafers were also processed with the same design of the experiments as device wafers under the same process conditions. SIMS/ARXPS method were utilized to measure the B profiles, extract the B junction depth and calculated total retained B dose in the Si substrate after post PLAD clean steps

29 Fig. 5.7 shows the B profiles on the monitoring wafers for PLAD with and without Ge coimplant. The data was collected right after post PLAD cleans. There was a native oxide layer on the top of the Si substrate, which thickness was measured by ARXPS. A background doping level marked as cm -3 was used to determine x j. Fig. 5.8 shows that the Ge co-implant before B 2 H 6 PLAD with shallower B profiles and x j and with less B dose than the B 2 H 6 PLAD alone, which is a typical PAI effect. However, Ge co-implant after B 2 H 6 PLAD shows deeper and little more box-like profiles but with a similar x j and with more dose than the B 2 H 6 PLAD alone. B Concentration (/cm 3 ) 1E23 1E22 1E21 1E20 1E19 1E18 Native Oxide 1E17 Ge10keV before PLAD Si Ge5keV before PLAD Depth (nm) B 2 H 6 PLAD 2.5kV/3.5E16 As-implanted Ge10keV after PLAD Ge5keV after PLAD PLAD alone xj at 2e18 Fig. 5.7 The B profiles on the monitoring wafers for B 2 H 6 PLAD and Ge co-implant before/after B 2 H 6 PLAD [Liu13]. It is believed that these significant differences on the B profile and the total retained B dose for B 2 H 6 PLAD were caused by Ge knock-on effect. B 2 H 6 PLAD has B deposition during implant. After PLAD, the B deposition layer and the very first layers of the Si substrate usually include the majority of total implanted dose. During post-plad clean steps, the deposition layer was removed and the first several nm substrate layers were also etched away by post PLAD strip/clean steps. Therefore, the majority of B was lost after post-plad clean steps. However, when we implanted Ge right after B 2 H 6 PLAD, Ge ions knocked B species from the deposition layer into the Si substrate. Ge also pushed B species in the Si surface layers even deeper. Therefore, during post PLAD clean steps, there were fewer B dopants removed with the deposition layer and the Si surface layers. As a result, the total retained B dose in Si was increased. It could also explain why it did not increase the total retained B dose for Ge implant after B beam- line implant because B beam-line implant did not have B deposition layer. Fig. 5.8 (left) was the sheet resistance (R S ) of the PMOS S/D area. Comparing to PLAD without Ge co-implant, Ge implant at 5 kev before PLAD reduced R S by 8%. Since Ge implant before PLAD had comparable total retained B dose but shallower x j than PLAD without Ge co-implant, this R S improvement should be speculated from the enhanced B activation by Ge. On the other hand, Ge implant at 5 kev after PLAD reduced R S by 28.6%. Since it is much higher than 8%, it should not be caused majorly by B activation enhancement from Ge. Ge implant at 5 kev after PLAD had over 30% higher retained total B dose than PLAD without Ge, it is obvious that such total retained B dose improvement should be the major root cause for the significant R S 15-29

30 improvement. When we kept increasing Ge energy to be 10 kev, the R S was reduced further by 40% due to even higher retained total B dose which was caused by more Ge knock-on effect at higher energy. Fig. 5.9 (right) was the contact resistance (R C ) of the advanced PMOS S/D area. Comparing to PLAD without Ge co-implant, Ge implant at 5 kev before PLAD reduced R C by about 50%. On the other hand, Ge implant at 5 kev after PLAD reduced Rc by about 73%. However, when we increased Ge energy to be 10 kev, the R C was not reduced further, but it was still about 70% lower than PLAD without Ge co-implant. Figure 5.8 (left): the normalized sheet resistance R S of the advanced PMOS S/D area; (right): the normalized contact resistance R C of the advanced PMOS S/D area [Liu13]. Fig. 5.9 was the normalized I DS vs. I OFF of the advanced PMOS device. Compared to PLAD without Ge co-implant, Ge implant at 5 kev after PLAD improved I DS mean by 12% with a similar I DS variation and I OFF mean. V T roll off (V T vs. L GATE ) were comparable which indicated that they had similar SCE. I SOFF vs. I DOFF was also comparable which indicated GIDL was not degraded by Ge co-implant Norm. I DS Norm. I OFF PLAD only Ge 5keV before PLAD Ge 5keV after PLAD Ge 10keV after PLAD Figure 5.9 The normalized I DS vs. I OFF for the advanced PMOS device [Liu13]. 5.3 He PIII Pre-Amorphization The ion flux during a pulsed plasma doping cycle can be ~10 ma/cm 2 or greater. In addition to providing high-throughput implantation, the high flux rate of PIII also enables unique process conditions not attainable with beam-line current densities. Using a high-flux PIII implanter (and 15-30

31 limiting wafer temperature rises during implant) even light ions, such as He, can be used to produce thin amorphous surface layers which can limit dopant ion channeling during subsequent implantation cycles. Fig shows a TEM image of an amorphous layer formed by He PIII implantation at 60 V with a thickness of ~6 nm [Sasaki04]. Figure 5.10 TEM image of amorphous silicon layer formed by He plasma immersion at 60 V and an implant time of 7 sec. The amorphous layer is ~6 nm thick [Sasaki04]. The thickness of the amorphous layer created by He ion PIII can be controlled by the PIII bias voltage (Fig. 5.11) using much lower implantation energies than are typical for the heavier ions, such as Si or Ge, used in beam-line pre-amorphization implantation (usually in the range of 1 to 10 kev). Figure 5.11 Thickness of amorphous layer vs. PIII bias voltage for helium PIII [Sasaki04]. After the He pre-amorphization implant, the gas mix in the PIII plasma can be adjusted to form a dilute (~5% B 2 H 6 in 95% He) dopant plasma, and the doping cycles are implanted for a process time of ~7 s. After 100 ns annealing with a green light laser (wavelength ~530 nm), the resulting junction was <11 nm deep with a vertical junction abruptness of 2.2 nm/decade and a sheet resistance of 588 Ω/square (Fig. 5.12)

32 Figure 5.12 Boron profiles after PIII doping with a combination of He pre-amorphization and a dilute B plasma with 60 V bias voltage. Also shown is the B profile after annealing with a pulsed All-Solid-state Laser (ASLA) with a wavelength of 530 nm. The ASLA pulse length was 100 ns at a power density of ~1.5 J/cm 2 [Sasaki04]. 5.4 Conformal and 3-Dimensional Doping Trench capacitor doping Plasma doping of non-planar topographies, such as DRAM trench capacitors and vertical channel transistors, is another attractive application, since conformal doping of such structures with a beam-line implanter is also extremely difficult. The first plasma doping of a trench capacitor was performed by Mizuno, who applied a bias to a substrate placed in an RF plasma of a dopant gas [Mizuno87, 88]. Collisions with gas neutrals randomized the incident ion angle so that the sidewalls and bottom of the trenches were conformally doped. That work demonstrated that the angular divergence among the ions is large enough to conformally dope a trench with a top opening of 0.45 µm and a depth of 2.8 µm. Later trench sidewall doping was accomplished with plasma doping operating at higher gas pressures (several mtorr). Trenches with an aspect ratio of 12 and a top opening of 1 µm were conformally plasma-doped at a pressure of 5 mt [Yu94]. In this case, the slight beam divergence due to ion-neutral collisions can enhance the conformal doping via both direct implantation and reflected implantation. Most recently trench doping for DRAM capacitor cells has been shown in joint work between Infineon (Siemens) and IBM [Lee99, 00]. Plasma-doped trench capacitor cells showed an increase in capacitance of 10-20% compared with those conventionally doped by solid phase diffusion from As-silicate glass Shallow STI trench doping Plasma doping can be extremely suitable to screen defective Si interfaces that may induce parasitic charges into devices using pinned diodes. CMOS image sensor typically used a pinned photodiode for which the dark current has to be kept under the noise level. A typical source of this dark current is the defective interface close to the pinned photodiode. Such interfaces states are screened via the formation of a p-type layer close to the interface. While shallow trench isolation is used to separate photodiodes, Moon et al. from Samsung have shown that a conformal doping of the shallow trench leads to a significant reduction of the dark current in advanced CMOS images sensors compared to the standard p-type implants [Moon07]. With such a conformal doping applied to STI before the STI gap fill, the authors have demonstrated that the 15-32

33 temporal noise and the dark level decreased while the saturation characteristics of photodiodes are not degraded. As Fig shows, BF 3 plasma doping produces a shallow, conformal doping around the shallow trench isolation (STI). This doped layer screens the defective sidewalls and edges of the STI from the depletion region of the photodiode. The measured dark current of the devices decreased as the plasma implant dose was increased. Figure 5.13 SEM images of STI regions doped by PIII and beam-line (insert) implants. Note the conformal doping along the sides and bottom of the STI structure for the PIII doping [Moon07] Source/Drain extension challenges for FinFETs Multi-gate transistor architectures are emerging today for their recognized ability to enhance the control by the gate electrode of the conduction channel of FETs. Various Double-Gate (DG) FET architectures have been proposed and fabricated. Recently, one of the most promising doublegate architectures is the FinFET device, shown in Fig A vertical crystalline silicon wall defines the fin, which is wrapped around on both sides (and the top) by the gate. For a narrow fin, i.e. small fin width, two conduction channels are created on each side. Gate Fin Source Drain Spacers Figure 5.14 An SOI FinFET with 3 fins in parallel. Fig. 5.15a shows the typical doping distribution through the SDE as simulated by TCAD when low tilt angle beam-line implant is used. In this case, the depth distribution of dopants is emulated with a Gaussian profile having the peak concentration at the silicon surface. The doping 15-33

34 concentration of the top part of the fin is 10 higher than the sidewalls. The Figs. 5.15b and 5.17c are two cross sections of the fin at the gate edge and 10nm under the gate, showing the 2D distribution of the electron density of FinFETs with SDE doping profile shown in Fig. 5.15a. At the gate edge, the electron path is confined in the highly doped part of the SDE (Fig. 5.15b), whereas the electron density is perfectly uniform all around the fin under the gate (Fig. 5.15c). Thus, for a non uniform SDE, the current tends to spread out from the highly doped SDE into the conduction channel adding an additional spreading resistance to the access series-resistance. To assess the impact of this additional spreading resistance, TCAD simulations of FinFETs were performed with two different SDE profiles. a) S gate D S gate D b) Figure 5.15 TCAD simulation of a non-uniform 2D doping profile through the fin in the SDE region of n-finfet (a) and the resulting on-state 2D electron density distribution in the SDE region at the gate-edge (b) and in the channel region 10 nm under the gate (c). The difficulty of achieving conformal doping along the sides as well as the top of a FinFET contact is illustrated in Fig. 5.16, where SIMS measurements of implanted boron concentrations (done with an un-doped poly-si fill deposition between the fins prior to the SIMS profiling) shows the nearly order of magnitude drop in sidewall doping levels between as 45 o incident ion beam and a glancing (10 o ) beam [vandal08]. The drop in the sidewall doping arises from a combination of ion reflection, limited ion penetration into the sidewall and sputtering for glancing angle conditions

35 Figure 5.16 Top and sidewall doping for a 5 kev BF 2 beam at 45 o and 10 o incidence (measured with a poly-si deposition between the fins before SIMS analysis) [vandal08]. An approach called self-regulatory plasma doping (SRPD) technique that has shown success in obtaining uniform doping for a variety of FinFET sidewalls and planar SDE implants is to employ a low ion density plasma with a mix of B 2 H 6 and He gases to limit the implantation and sputtering of the fin top surface while allowing for dopant deposition to enhance doping of the fin sidewalls [Sasaki08]. Fig shows 2D scanning spreading resistance microscopy (SSRM) pictures obtained with the SRPD. The conformal doping layer such as the ratio of the top to the side resistivity of is realized. It notes that by using low pressure, the original shape of the corners of fin is kept during the SRPD process without sputter erosion. Figure 5.17 SSRM picture after the SRPD process for (a) dense or (b) high aspect ratio fin structures [Sasaki08]. Advantage of the SRPD process has been verified with FinFETs with metal/high-k gate stack (Fig. 5-20). Short channel effect (SCE) improvement for FinFETs is clearly obtained. V TSAT -roll off characteristic is clearly improved by introducing the SRPD compared to the BL-based ion implant (II) (Fig left). It seems to be due to conformal doping in sidewalls of fins. The within-wafer V TSAT uniformity with the SRPD is excellent (1σ =6.4 mv) for 48 nm gate pmos FinFETs compared to that with II (1σ =15 mv) (Fig right). It is acceptable even for 38 nm gate pmos FinFETs (1σ =13 mv). This new SRPD will be the excellent compatible doping method for pmos FinFETs as well as planar pmosfets extension for 32 nm node and beyond

36 Figure 5.18 FinFET device performance (left) V TSAT -roll off characteristics of nm gate length FinFETs, and (right) comparison of within-wafer V TSAT uniformity for FinFET between fabricated with the SRPD and the BL-based ion implant (II) [Sasaki08]. In a recent paper [Lee13], an advanced plasma doping scheme for the conformal doping of fin resistor and FinFET with ion assisted deposition and doping technique had been demonstrated. The damage free As-doped fin for n-type bulk FinFET structures using the plasma doping had been obtained. Compared to a standard ion-implantation, the plasma doping scheme suppresses the crystalline defect formation. The diagnosis of FinFET performance is shown for the plasma doping and the standard ion-implantation doping scheme using the analysis of I-V characteristics, low frequency noise, hot carrier reliability, and mobility. For the standard ion-implantation doping reference, 10⁰ tilted As implantation was used at room temperature. For the conformal doping technique, the plasma doping was performed as follows: After As deposition on fin, fin surface is knocked in by Arsine plasma. In this work, fin resistors and FinFETs are both fabricated on 300 mm wafers. For FinFET gate stack, 1.8 nm HfO 2 and 3 nm TiN are deposited using atomic layer deposition (ALD). RTA annealing is used at 1050 ⁰C for dopant activation for both the standard ion implantation and the plasma doping. The cross-sectional transmission electron microscopy (TEM) images of the standard ionimplanted and the plasma doped fins are shown in Figs. 5.19(a) and (b). For the standard ionimplantation, multiple twin boundary defects along the {111} plane are observed whereas the plasma doped fin has defect-free mono-crystalline Si. As shown in Fig (c), implantation damages are expected for a narrow fin by process simulation. Compared to the standard ionimplantation, the plasma doping technique needs less energy for the ion acceleration. Thus, the formation of crystalline defects is significantly suppressed for the plasma doping scheme. Scanning Spreading Resistance Microscopy (SSRM) image shows a 2-D resistance profile of the plasma doped fin in Fig (d). The uniform resistance of fin surface shows that the plasma doping scheme gives good doping conformality along the top and sidewall of the fin

37 Figure 5.19 Cross-sectional TEM images of fin doped by (a) standard ion-implantation and (b) plasma doping. (c) Process simulation shows a damage profile of ion-implanted fin. (d) SSRM image of conformal plasma doped fin. [Lee13] Vertical trench transistor doping There are many challenges in semiconductor manufacturing for Si technology at 22 nm node and beyond, including device architectures/structures, design rules, and processes. The widely published 3D device structure candidates include FinFET and vertical trench transistors. The doping technique is very critical for implementing the 3D device technology. However, the doping challenges for vertical transistor are very different to that for FinFET. FinFET requires uniform doping at top, sidewall, and bottom of the fin structure. Vertical trench transistor usually has a higher aspect ratio (AR) of the trench than FinFET, and requires a heavily doped at the bottom (transistor source and digital line), but minimal doping at the sidewall (transistor channel). There are significant limitations for conventional beam-line (BL)-based ion implant because of fundamental issues like line of sight shadowing effect, space charge limit, self-sputtering effect, and angle variation issues. PLAD method is more promising for non-planar structures because of its unique advantages which can overcome or minimize many of the same issues. The doping of a 3D trench transistor structure by utilizing both BL implant and PLAD methods had been investigated [Qin13]. Electron holography (EH) was used as a powerful method to study 2D cross-sectional doping profiles of As-based doping processes for trench transistor structures. Electron holography method shows quantitative definitions of junction depths x j in both vertical and lateral directions at the bottom part of the trench channel array transistor (TCAT). A trench transistor structure is shown in Fig with ~30 nm opening, ~20 nm space, ~230 nm depth, and aspect ratio: ~12. The sidewall was covered by ~6.7 nm thin silicon nitride (Si 3 N 4 ) liner to protect doping because the sidewall regions are part of the transistor channel. Only the bottom of the trench was opened and required to be doped to form source regions of the vertical transistors