Yield. Economics. Victor Ovchinnikov. Chapters 36, 37

Transcription

1 Yield. Economics Victor Ovchinnikov Chapters 36, 37

2 Previous material CMOS Released structural layers MEMS Multilayer metallization Aalto Nanofab, 2017 Microfabrication 2

3 Content Yield definition Yield models Yield trends Wafer/chip cost Cost-of-ownership Cost of processed silicon Aalto Nanofab, 2017 Microfabrication 3

4 IC defects Aalto Nanofab, 2017 Microfabrication 4

5 Silicon wafer and chips edge exclusion 2-3 mm scribe lines for chip dicing 100 µm alignment marks for lithography 0.3x0.3 mm 2 wafer flat for orientation checking 32.5 mm (100 mm wafer) 100 mm diameter silicon wafer Chip allocation on a wafer Aalto Nanofab, 2017 Microfabrication 5

6 Yield It is a quotient of good outcomes to total (wafers, chips): YY = NN gggggggg NN tttttttttt If a process consists of several steps YY = where i notes yield of individual step. ii yy ii In case of systematic and random components YY = YY ssssss YY rrrrrrrr e.g., global disturbance Y sys and spot defects Y rand Aalto Nanofab, 2017 Microfabrication 6

7 Effect of process step amount YY = ii yy ii y i - yield of i-th step Aalto Nanofab, 2017 Microfabrication 7

8 Poisson yield model The random-yield loss Good matching YY = ee DDDD D defect density, A chip area Too pessimistic for large A Aalto Nanofab, 2017 Microfabrication 8

9 General yield model (negative binomial) α cluster factor All models present random part of yield Y rand! Aalto Nanofab, 2017 Microfabrication 9

10 Clustering coefficien (α=β) and yield 58% 38% ANF average number of faults YY PP = ee 1 = 36.8% Aalto Nanofab, 2017 Microfabrication 10

11 Defect densities Investments in new equipment and technology have driven down defect densities and ultimately improved yields. Aalto Nanofab, 2017 Microfabrication 11

12 Die size Shrinking linewidth have showed the rate of growth in die size to 1.14x per year. Aalto Nanofab, 2017 Microfabrication 12

13 Why do we talk about yield? Yield defines profit Yield demonstrates quality of the process Yield variations reflect process changing: Materials Environment Tools Operator skill Wrong desing... Aalto Nanofab, 2017 Microfabrication 13

14 Yield loss contributors and yield ramp Mask set has been designed Start from beginning Aalto Nanofab, 2017 Microfabrication 14

15 Yield and technology nodes Aalto Nanofab, 2017 Microfabrication 15

16 Why does microfabrictation exist? Science New gadgets Money Aalto Nanofab, 2017 Microfabrication 16

17 Intel Market share 14% Profit 20% Aalto Nanofab, 2017 Microfabrication 17

18 Factory cost Aalto Nanofab, 2017 Microfabrication 18

19 Exposure system costs Aalto Nanofab, 2017 Microfabrication 19

20 Revenue for semiconductors Aalto Nanofab, 2017 Microfabrication 20

21 Silicon wafers 5 billion dollars used for silicon wafers 5 km 2 of silicon wafers used Cost of silicon is 5*10 9 $/5*10 10 cm 2 = 0.1 $/ cm mm wafer (314 cm 2 ) 30 dollars 160 million wafers annually (if all were 200 mm) A big fab has wafer starts per month (WPM) No more than 250 big wafer fabs in the world Aalto Nanofab, 2017 Microfabrication 21

22 Cost of processed silicon IC industry annual turnover is 250 billion, 250 big fabs a fab produces 1 billion $ a year Price of processed silicon is: 250*10 9 $/5*10 10 cm 2 = 5 $/cm 2 Because profits are very small, the cost of processing silicon is close to 5 $/cm 2 Silicon wafer cost is only 2% of IC cost Aalto Nanofab, 2017 Microfabrication 22

23 Equipment numbers for a WPM fab Lithography tools 35 Wet stations 70 Oxidation/diffusion tubes 30 Ion implanters 15 LPCVD tubes 10 PECVD reactors 40 Plasma etchers 50 Metal deposition systems 40 CMP tools 60 Aalto Nanofab, 2017 Microfabrication 23

24 Cycle time Cycle time (CT) is the number of days it takes to complete a lot. Process time (PT) is the actual time it takes for the wafer to be processed. The ratio CT/PT is a measure of fab efficiency and is about 2 for standard processing. Aalto Nanofab, 2017 Microfabrication 24

25 Cost of ownership (CoO) equipment+labour+consumables+operation+yield loss CoO = equipment life throughput utilization rework rate Process step cost per wafer =investment cost + process cost Aalto Nanofab, 2017 Microfabrication 25

26 Lithography cost Equipment cost $ Equipment life 5 years Utilization 85% Throughput 25 WPH Rework rate wafers and investment cost is $4.2 per wafer Aalto Nanofab, 2017 Microfabrication 26

27 Process cost and yield loss Labour Consumables (resist) Operation (electricity) $1.7 per wafer $2 per wafer $0.15 per wafer Total lithography cost (CoO) is $8.55 per wafer If cost of chip is $3 and 350 chips on wafer and 7 of them are scrap, then yield loss is 7 3=$21 Aalto Nanofab, 2017 Microfabrication 27

28 Cost of Ownership (CoO) Aalto Nanofab, 2017 Microfabrication 28

29 Technology nodes and market Aalto Nanofab, 2017 Microfabrication 29

30 Most profitable linewidth Yield Cost Profit Aalto Nanofab, 2017 Microfabrication 30

31 Optimum chip size constant over 30 years!!! Aalto Nanofab, 2017 Microfabrication 31

32 Conclusions Yield (defect loss) is inherent feature of the microfabrication Yield can be statistically analyzed and controlled Yield depends both on design and on processing Every technology node has optimum chip size Cost of ownership is a universal figure of merit for all tools Aalto Nanofab, 2017 Microfabrication 32