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1 Предлагаем продукцию SEMIKRON и другие ЭЛЕКТРОННЫЕ КОМПОНЕНТЫ (радиодетали) СО СКЛАДА И ПОД ЗАКАЗ Беларусь г.минск т ел./факс 8(017) SEMiSTART Prducts Technical Infrmatin Melanie Gill December 009 Versin 1.0 Page 1 f by SEMIKRON

2 1 Intrductin Features Tplgy Type designatin Typical Applicatins... 4 Mechanical Details Dimensins Internal cnstructin Mechanical samples Explanatin f electrical parameters Measuring Thermal Resistance R th(j-s) Transient Thermal Impedance Explanatin f electrical parameters Qualificatin Standard Tests fr Qualificatin Surge verlad current Tests using change f temperature Lifetime Calculatins Applicatin Overvltage prtectin Over-current and shrt circuit prtectin Permissible ver-currents Captin f the figures in the data sheets Packaging Infrmatin Packaging Unit Disclaimer Versin 1.0 Page f by SEMIKRON

3 1 Intrductin SEMiSTART, the anti-parallel uninsulated thyristr mdule that was designed specifically fr use in sftstart devices, basts ne main advantage: cmpact dimensins. A 400 kw sft-starter featuring SEMiSTART has just ne sixth f the vlume f the same device with cnventinal capsule thyristrs. Plus, due t pressure cntact technlgy and duble-sided chip cling, these new mdules can withstand verlad currents f up t 3000 A fr a 0 s duratin f verlad. 1.1 Features SEMiSTART mdules are available in 3 sizes 5 current classes vltage classes Anti-parallel thyristr mdules develped fr verlad cnditins High lad cycle capacity by prven pressure cntact technlgy N rating f heat sink necessary due t integrated heat sink Lw thermal resistance between chip and heatsink beause f duble-sided cling f thyristrs Thyristrs with amplifying gate Cmpact design Simple munting withut special tls and thermal paste 1. Tplgy SEMiSTART prducts are available as W1C as given belw: Fig.1-1 SEMiSTART tplgy Versin 1.0 Page 3 f by SEMIKRON

4 1.3 Type designatin SK KQ 800 /14 E SEMIKRON cmpnent W1C, single phase AC cntrller I sin 180, 0s, T jmax =150 C, T jstart =40 C Vltage class (V RRM [V], divided by 100) dv/dt class (E: 1000V/µs) 1.4 Typical Applicatins Sft starters fr electric mtrs Mechanical Details.1 Dimensins SEMiSTART has 3 different husing sizes: SKKQ 560 SKKQ 800/100/1500 SKKQ 3000 Size Name Length (mm) Width (mm) Height (mm) A SKKQ B SKKQ 800/100/ C SKKQ Fig.-1 SEMiSTART prduct family Versin 1.0 Page 4 f by SEMIKRON

5 . Internal cnstructin In SEMiSTART mdules the thyristr chips are directly pressed between tw heat sinks using pressure cntact technlgy. The heat sinks als serve as electrical cnnectrs. The mdules have few cntact layers and n electrical insulatin. Fig.- SEMiSTART design principle.3 Mechanical samples Fllwing SEMiSTART mechanical samples can be rdered: Item N. Name Size SKKQ 560 A SKKQ 800/100/1500 B SKKQ 3000 C Fig.-3 Item numbers fr SEMiSTART mechanical samples Versin 1.0 Page 5 f by SEMIKRON

6 3 Explanatin f electrical parameters 3.1 Measuring Thermal Resistance R th(j-s) The definitin fr thermal resistance R th is the difference between tw defined temperatures T divided by the pwer lss P V which gives rise t the temperature difference under steady state cnditins: ΔT P T T 1 R th 1 (3-1) V PV Fr SEMiSTART mdules the thermal resistance junctin t heat sink R th(j-s) is given. The data sheet values base n measured values. As can be seen in equatin (3-1), the R th value depends n the temperature difference ΔT, s the reference pints have a majr influence. The reference pints fr SEMiSTART mdules are the virtual junctin f the chip (T j ) and the lateral surface f the heat sink, where T s is measured next t the drill hle where the T-sensr is fixed (s. View B in the datasheet). The pint fr the T s measurements mves away frm the chip with grwing mdlue size and the thermal resistance rises. Fr this reasn R th can nly be used t estimate the chip temperature but nt t make a cnclusin abut the current. This is nt necessary because SEMiSTART mdules shuld nt be used with cntinuus lad. They absrb heat quite fast and release it again with a time cnstant that is nt f interest fr the applicatin. Fr further infrmatin n the measurement f thermal resistances please refer t: M. Freyberg, U. Scheuermann, Measuring Thermal Resistance f Pwer Mdules ; PCIM Eurpe, May Transient Thermal Impedance When switching n a cld mdule, the thermal resistance R th appears smaller than the static value given in the data sheet. This phenmenn ccurs due t the internal thermal capacities f the package. These thermal capacities are uncharged and will be charged with the heating energy resulting frm the lsses during peratin. In the curse f this charging prcess the R th seems t increase. Therefre it is called transient thermal impedance Z th during the rise time. When all thermal capacities are charged and the heating energy has t be emitted t the ambience, the transient thermal resistance Z th has reached the static data sheet value R th. This behaviur leads t the advantage f shrt-term verlad capability f the pwer mdule. Versin 1.0 Page 6 f by SEMIKRON

7 Fig.3-1 Example fr the transient thermal impedance 3.3 Explanatin f electrical parameters I verlad verlad current Maximum verlad current (rms value). The verlad current is limited t 0s nly because the junctin temperature f the thyristr may rise up t 150 C. I TSM surge n-state current Peak value fr a surge current in the frm f a single sinusidal half wave which lasts fr 10ms. After ccasinal current surges with current values up t the given surge frward current, the thyristr can withstand the reverse vltages specified in Fig. 7 f the datasheets. i t This value is given t assist in the selectin f suitable fuses t prvide prtectin against damage caused by shrt circuits and is given fr junctin temperatures f 5 C and 15 C. The i t value f the fuse fr the intended input vltage and the prspective shrt circuit in the device must be lwer than the i t f the thyristr fr t = 10ms. When the perating temperature increases, the i t value f the fuse falls mre rapidly than the i t value f the thyristr. A cmparisn between the i t f the thyristr fr 5 C and the i t value f the (unladed) fuse is generally sufficient. V RSM nn-repetitive peak reverse vltage Maximum permissible value fr nn-repetitive transient reverse vltages. Versin 1.0 Page 7 f by SEMIKRON

8 V RRM repetitive peak reverse vltages, V DRM ff-state vltage Maximum permissible value fr repetitive transient ff-state and reverse vltages. T j junctin temperature The mst imprtant referential value fr calculating limiting values is the maximum permissible junctin temperature T j. At a circuit fault (e.g. when a fuse is activated) this value may be exceeded briefly (cf. "surge n-state current"). T stg strage temperature The permissible ambient cnditins withut current r vltage stress are described, amng ther things, by the maximum permissible strage temperature T stg. The parameter T stg is als the maximum permissible case temperature, which must nt be exceeded by an internal r external temperature rise. V T n-state vltage Maximum frward vltage. V T(TO) threshld vltage, r T n-state slpe resistance These tw values define the frward characteristics (upper value limit) and are used t calculate the instantaneus value f the frward pwer dissipatin P T r the mean frward pwer dissipatin P TAV : P T V I r T ( T 0) T T T i P TAV V I T ( T 0) TAV T TRMS r I fr square-wave pulses: I TRMS TAV I 360 TRMS fr [part] sinusidal half waves:, 5 I I TAV r I TRMS TAV I 180 Θ: current flw angle i T : instantaneus frward current value I TRMS : RMS n-state current I TAV : mean n-state current I DD direct ff-state current Maximum ff-state current fr the given temperature and maximum vltage. This value depends expnentially n the temperature. Versin 1.0 Page 8 f by SEMIKRON

9 Time definitins fr triggering Fig. 3- shws the characteristics f gate trigger signal V G and ande-cathde vltage V AK which define the time intervals fr the triggering prcess. Fig. 3- Time definitins fr thyristr triggering t gd gate-cntrlled delay time Time interval between the start f a triggering pulse and the pint at which the ande-cathde vltage falls t 90% f its starting value. The datasheet specifies a typical value which is applicable, prvided the fllwing cnditins are fulfilled: Square-wave gate pulse, duratin 100μs Ande-cathde starting vltage 0.5 V DRM On-state current after firing apprx. 0.1 I 85 C Junctin temperature during firing apprx. 5 C t gr gate-cntrlled rise time Perid within the ande-cathde vltage falls frm 90% t 10% f its starting value during firing. t gt gate current pulse duratin The sum f the gate cntrlled delay time t gd and the gate cntrlled rise time t gr. Versin 1.0 Page 9 f by SEMIKRON

10 (dv/dt) cr critical rate f rise f ff-state vltage The values specified apply t an expnential increase in ff-state vltage t 0.66 V DRM. If these values are exceeded, the thyristr can break ver and self trigger. (di/dt) cr critical rate f rise f n-state current Immediately after the thyristr has been triggered, nly parts f the thyristr cnducts the current flw, meaning that the rate f rise f the n-state current has t be limited. The critical values specified apply t the fllwing cnditins: repetitive lads with 50-60Hz a peak current value crrespnding t the crest value f the permissible n-state current fr sinusidal half waves a gate trigger current that is five times the peak trigger current with a rate f rise f at least 1A/µs The critical rate f rise fr n-state current falls as the frequency increases, but rises as the peak n-state current decreases. Fr this reasn, fr frequencies > 60Hz and pulses with a high rate f rise f current, the peak n-state current must be reduced t values belw thse given in the datasheets. t q circuit cmmutated turn-ff time The circuit cmmutated turn-ff time lies in the range f several hundred µs and cnstitutes the time required fr a thyristr t discharge t allw it t take n frward vltage again. This value is defined as the time that elapses between zer crssing f the cmmutatin vltage and the earliest pssible lad with ff-state vltage. In the case f thyristrs fr phase-cmmutated cnverters and a.c. cnverters, the circuit cmmutated turn-ff time is usually f n significance. Fr this reasn, the datasheets cntain typical values nly, and n guarantee is given fr these values. I H hlding current Minimum ande current which will hld the thyristr in its n-state at a temperature f 5 C. If the thyristr is switched n at temperatures belw 5 C, the values specified may be exceeded. I L latching current Minimum ande current which will hld the thyristr in its n-state at the end f a triggering pulse lasting 10µs. The values specified apply t the triggering cnditins stipulated in the sectin n "Critical rate f rise f n-state current". V GT gate trigger vltage, I GT gate trigger current Minimum values fr square-wave triggering pulses lasting lnger than 100µs r fr DC with 6V applied t the main terminals. These values will increase if the triggering pulses last fr less than 100µs. Fr 10µs, fr instance, the gate trigger current I GT wuld increase by a factr f between 1.4 and. Firing circuits shuld therefre be arranged in such way that trigger current values are 4 t 5 times larger than I GT. If the Versin 1.0 Page 10 f by SEMIKRON

11 thyristr is laded with reverse blcking vltage, n trigger vltage may be applied t the gate in rder t avid a nn-permissible increase in ff-state pwer lsses and the frmatin f ht spts n the thyristr chip. V GD gate nn-trigger vltage, I GD nn-trigger current These trigger vltage and current values will nt cause the thyristr t fire within the permissible perating temperature range. Inductive r capacitive interference in the triggering circuits must be kept belw these values. R th(x-y) thermal resistances, Z th(x-y) thermal impedances Fr SEMiSTART mdules thermal resistances/impedances are given fr the heat flw between pints "x" and "y". Fllwing indices are used: j - junctin s - sink a - ambient The transient thermal impedances Z th(j-s) and Z th(s-a) are shwn as a functin f time t in Fig. 3 and Fig. 4 f the datasheets. Fr t > 1s, Z th(s-a) f the heat sink must be added t Z th(j-s) in rder t calculate the ttal thermal impedance. M t munting trque Tightening trque fr terminal screws and fasteners. m weight Weight f the cmplete mdule (including heat sink). Case Same number means same mechanical features. Fr details please refer t the drawings in the data sheet. Versin 1.0 Page 11 f by SEMIKRON

12 4 Qualificatin 4.1 Standard Tests fr Qualificatin The bjectives f the test prgramme are: 1. T ensure general prduct quality and reliability.. T evaluate design limits by perfrming stress tests under a variety f test cnditins. 3. T ensure the cnsistency and predictability f the prductin prcesses. 4. T appraise prcess and design changes with regard t their impact n reliability. Test Nrm Parameters High Temperature Reverse Bias IEC h, 66% f vltage class, 105 C T C 10 C High Temperature Strage IEC h, T stgmax Lw Temperature Strage IEC h, T stgmin Thermal Cycling (TC) IEC Test Na 5 cycles, T stgmax -T stgmin Pwer Cycling (PC) IEC lad cycles, T j =100K Vibratin IEC Test Fc Sinusidal sweep, 5g, h per axis (x,y,z) Mechanical Shck IEC Test Ea Half sine pulse, 30g, 3 times each directin ( x, y, z) Fig. 4-1 SEMIKRON standard tests fr prduct qualificatin SEMiSTART mdules have n sft mld prtectin arund the chip. They are therefre susceptible t envirnmental influences (humidity, dust, etc.). The humidity test accrding t IEC is nt passed by this prducts. Mre details t the abve specified quality tests, specific test results and a cmplete essay fr custmer presentatin are available upn request. Please cntact SEMIKRON SEMiSTART Prduct Management. Versin 1.0 Page 1 f by SEMIKRON

13 4. Surge verlad current Fig. 4- Surge verlad current vs. time Fig. 4- shws the peak value f verlad current I T(OV) permissible under fault cnditins nrmalised t the surge n-state current I TSM shwn as a functin f the duratin f the fault t. The additinal parameter is the peak reverse vltage reapplied immediately after the fault current has ceased. Fr faults lasting lnger than 10ms it is assumed that the current wavefrm is a series f half sinewaves with a perid f 16.6ms respectively 0ms. Three different curves are shwn: 0. V RRM : n reverse vltage is reapplied ½. V RRM : a vltage equal t half the repetitive peak reverse vltage rating is reapplied 1. V RRM : a vltage equal t the full repetitive peak reverse vltage rating is reapplied 4.3 Tests using change f temperature Since the external cntacts have a significantly higher thermal expansin cefficient than the silicn chip, it is apparent that temperature cycling, which stresses these external cntacts, is a particularly gd test fr checking the lad cycling stability f the internal cntacts. After the testing, the first criteria used fr checking whether the cntacts have withstd the stresses impsed, is t check the thermal resistance, and additinally the frward and reverse characteristics are checked. Tests which use external heating and cling f the cmpnent deviate frm actual perating cnditins in s far as the cmpnent under test is unifrmly heated and cled. In reality a varying temperature gradient ccurs between the silicn chip and the ambient. Therefre, it is recmmended, particularly fr a new develped cmpnent, t use a further test methd, which makes it pssible t g thrugh a large number f cycles in a shrt time with stresses similar t thse which ccur in the actual wrking envirnment. T achieve this, the cmpnent under test is brught in clse cntact with a water cled Versin 1.0 Page 13 f by SEMIKRON

14 heat sink t keep the case temperature almst cnstant. By applying shrt, high current pulses the silicn chip is heated up peridically t almst its maximum allwable virtual junctin temperature. During the intervals between the pulses the junctin cls dwn very rapidly. This methd prduces peridically a high temperature gradient between the silicn chip and the munting surface. 4.4 Lifetime Calculatins The lifetime f a pwer mdule is limited by mechanical fatigue f the package. This fatigue is caused by thermally induced mechanical stress caused by different cefficients f thermal expansin (CTE). In the curse f heating (pwer n) and cling (pwer ff), the materials expand differently due t their different CTEs. Since the materials are jined, they are unable t expand freely, leading t the mentined mechanical stress. The mechanical stresses that ccur inside the different material layers, lead t material fatigue when temperature changes. The higher the temperature difference (ΔT), the mre stress is induced. With every temperature cycle aging takes place. Wire bnding and slder layers are particularly affected by this. Aging results in small cracks, which start at the edges and extend t the centre f the material with every pwer cycle that ccurs. The higher the medium temperature T j m, the faster the cracks grw, because the activating energy is higher. The typical defect characteristics resulting frm field returns is lift ff f the wire bnds. This means that the cracks meet in the centre and pen the cnnectin in such a way that the wire bnd is lse. This shws that the lifetime is determined by the number f temperature cycles, which can be withstd by the mdule. In the 1990 s intensive investigatins were carried ut in this area, including a research prject knwn as the LESIT study. One f the main findings f this study was the equatin given belw (4-1), which shws the relatinship between the number f cycles Nf, the junctin temperature difference ΔT j and the medium temperature T j m. SEMiSTART mdules base n the same design principles as the mdules, which were investigated in the curse f the LESIT study. Fr this reasn the LESIT results may be used fr life time estimatins. The reliability f pwer mdules has imprved since the LESIT study was cncluded, s the results f equatin (4-1) can be seen as a wrst-case scenari. Nf A α Q ΔTj exp (4-1) R Tm j A = 640 α = -5 Q = J/ml R = J/ml K Versin 1.0 Page 14 f by SEMIKRON

15 ΔT j and T j m in [K] Fig. 4-3 Example f T j m and ΔT Fig.4-4 shws the experimental results f the LESIT study (as bullet pints) as well as the results f equatin 4-1 (as drawn lines). Fig. 4-4 LESIT curves, based n experimental results Fr further infrmatin n the lifetime calculatins fr pwer mdules please refer t: M. Held et.al., Fast Pwer Cycling Tests fr IGBT Mdules in Tractin Applicatin ; Prceedings PEDS, pp , 1997 Versin 1.0 Page 15 f by SEMIKRON

16 5 Applicatin 5.1 Overvltage prtectin It is well knwn that single crystal semicnductr devices are sensitive t ver-vltages. Every time their specified reverse vltage is exceeded this can lead t their destructin. It is therefre necessary t prtect thyristrs against vltage transients hwever caused, i.e. the transient vltages must be reduced t values belw the maximum specified limits fr the semicnductr device. A variety f well tried and tested cmpnents is suitable fr the abve suppressin. The mst imprtant are: resistrs and capacitrs (RC snubber netwrks) varistrs silicn avalanche dides The RC netwrk perates by frming a series resnant circuit with existing inductances. It transfrms any steeply rising transient vltage int a damped sinewave f lwer amplitude. The pwer f the vltage transient is cnverted frm a high value f shrt duratin t a lwer value extending ver a lnger time. All ther cmpnents listed abve have nn-linear characteristics. Their internal resistances reduce when the applied vltage increases. Tgether with the ther resistances and inductances in the circuit, they build nn-linear vltage dividers, which allw lw vltages t pass unattenuated but clip high vltages abve a defined level. The energy f the transient vltage spreads ver a lnger perid again, and is almst cmpletely absrbed by the suppressin cmpnent. The suppressin cmpnents can be psitined n the a.c. side f the thyristr stack, n the d.c. side, r acrss each semicnductr device in the circuit. The advantages and disadvantages f these varius arrangements will be cnsidered separately fr each type f suppressin cmpnent. RC snubber circuits are ften cnnected in parallel t the thyristr t prvide prtectin frm transient vervltage, althugh in sme cases varistrs are used. Due t the RC circuit the rate f rise f vltage is limited during cmmutatin, which reduces the peak vltages acrss the circuit inductrs. 5. Over-current and shrt circuit prtectin If shrt circuit prtectin is required fr the thyristrs, (ultra fast) semicnductr fuses are used. These must be dimensined n the basis f the frward current and i t value. Other types f prtectin fr high current circuits are, fr example fuses, which islate damaged thyristrs frm the parallel cnnectins. T prtect cmpnents frm statically nn-permissible high vercurrents, it is pssible t use magnetic r thermal vercurrent circuit breakers f temperature sensrs n the heat Versin 1.0 Page 16 f by SEMIKRON

17 sinks, but these d nt detect dynamic verlad within a circuit. Fr this reasn, temperature sensrs are used mainly with frced air cling in rder t prtect damage t the thyristrs in the event f fan failure. 5.3 Permissible ver-currents The permissible frward currents fr shrt-time r intermediate peratin, as well as fr frequencies belw 40 Hz must be calculated n the basis f the transient thermal impedance r the thermal impedance under pulse cnditins s that the junctin temperature T j des nt exceed the maximum permissible value at any time. Versin 1.0 Page 17 f by SEMIKRON

18 6 Captin f the figures in the data sheets Fig. 1 Pwer dissipatin per mdule vs. rms current Fig. Pwer dissipatin f three mdules vs. rms current Fig. 3 Transient thermal impedance Zth(j-s) vs. time Fig. 4 Typical transient thermal impedance Zth(s-a) vs. time (natural cling) Fig. 6Typical verlad current vs. time (natural cling) Fig. 7 Surge verlad current vs. time Fig. 9 Typical cling dwn vs. time (natural cling) 7 Packaging Infrmatin 7.1 Packaging Unit In ne bx are 3 pieces (valid fr all sizes). Type Pieces per bx Weight [kg] SKKQ ~1,60 SKKQ 800 / 100 / ~ 3,6 SKKQ ~ 10,0 Versin 1.0 Page 18 f by SEMIKRON

19 8 Disclaimer The specificatins f ur cmpnents may nt be cnsidered as an assurance f cmpnent characteristics. Cmpnents have t be tested fr the respective applicatin. Adjustments may be necessary. The use f SEMIKRON prducts in life supprt appliancesand systems is subject t prir specificatin and written apprval by SEMIKRON. Wetherefre strngly recmmend prir cnsultatin f ur persnal. Versin 1.0 Page 19 f by SEMIKRON