Low Switching Loss and Scalable V LDMOS Transistors with Low Specific On-Resistance

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Meagan Morgan
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1 International Conference on Technology and Social Science 218 (ICTSS 218) Invited Low Switching Loss and Scalable 2-4 V LDMOS Transistors with Low Specific On-Resistance Jun-ichi Matsuda, Jun-ya Kojima, Nobukazu Tsukiji, Masataka Kamiya, and Haruo Kobayashi Gunma University Apr. 18, 218 (Kiryu, Japan) 1

2 Outline 1. Objective and Background 2. Conventional and Proposed LDMOS Transistor Structures 3. Simulation Results Electric characteristics I DS -V DS, I DS -V GS, Breakdown, Specific on-resistance vs. breakdown voltage Hot carrier endurance Total power dissipation 4. Summary Simulation: 3D device simulator Advance/DESSERT developed by AdvanceSoft Corporation 2

3 Objective and Background Objective: To obtain scalable (low cost) 2-4 V LDMOS transistors for automotive applications to meet the requirements for (1) wide SOA, (2) high hot carrier endurance, (3) low specific on-resistance, and (4) low switching loss Uses of LDMOS transistors: 2-4 V LDMOS transistors are widely used as switching devices of power converters for automotive as well as consumer applications including smartphones and tablets. Automotive applications operating in harsh environments have to meet the above requirements. Conventional devices: We developed dual RESURF scalable 3-5 V LDMOS transistors based on a basic LDMOS transistor in 215. These devices meet the above requirements except for (4). Thus we proposed a 4 V LDMOS transistor to meet all the requirements by improving the 3-5 V LDMOS transistors. This is a single device. Scalable (low cost) lower voltage devices are required to obtain circuit design flexibility. Proposed device: We propose 2-4 V LDMOS transistors by reducing the drift region of the 4 V LDMOS transistor. Note: SOA (safe operating area), RESURF (reduced surface field) 3

4 Problems of a Basic LDMOS Transistor Source Gate V GS Intrinsic MOSFET Surface Drain p + n + n n-drift + V DS I DS Damage to the intrinsic MOSFET Damage to the surface Device destruction Drain current expansion Region A Region B p-sub. A cross-section of a basic n-ldmos transistor V GS Breakdown Boundary of SOA V DS I DS -V DS characteristics with drain current expansion Problems (1) Low hot carrier endurance due to DAHC (drain avalanche hot carriers) Caused by a high electric field in Region A (2) Drain current expansion (CE) leading to a narrow SOA Caused by a high electric field in Region B due to the Kirk effect (3) High specific on-resistance Caused by a low impurity concentration in the n-drift region 4

5 Conventional LDMOS Transistor Structure y V SS p + n + Source Gate P-Body p + -pickup PBL1 FP P-Well V GS Region A NDL2 PBL2 Region B NDL1 Region C P-Sub. n + V DS Drain x P-buried Layers (Dual RESURF Structure) PBL1: Enhances the RESURF effect in Region A, leading to high hot carrier endurance PBL2: 1 Causes a uniform electric field in the drift region 2 Avoids premature breakdown in Region C N-drift Layers NDL1: The basic layer of the drift region NDL2: Reduces specific on-resistance and suppresses CE due to a low electric field in Region B Field Plate (connected to the gate) Complements the RESURF effect in the drift region Increases the Miller capacitance, leading to a large switching loss A cross-section of the conventional device (One cell size: μm.3 μm).35 μm CMOS compatible process Reduction of the switching loss is required. 5

6 Proposed LDMOS Transistor Structure I PB y p + V SS I SS Source n + p + -pickup P-Body V GS Gate PBL1 NDL2 I SUB GFP P-Well V FP PBL2 NDL3 I DS Drain NDL1 P-Sub. A cross-section of the proposed device (One cell size: μm.3 μm).18 μm CMOS compatible process n + V DS x P-buried Layers (Dual RESURF Structure) PBL1 and 2: Same as the conventional device N-drift Layers NDL1 and 2: Same as the conventional device NDL3: Reduces specific on-resistance and suppresses CE (Needed to reduce the specific on-resistance increased by GFP) Field Plate (connected to the ground): GFP (Grounded Field Plate) Complements the RESURF effect in the drift region Reduces the Miller capacitance, leading to a low switching loss Single LDMOS transistor (only for 4 V operation) limits the flexibility of circuit design Scalable (low cost) lower voltage devices are required to enhance the flexibility of circuit design. 6

7 How to Make Scalable LDMOS Transistors Source p + n + Gate P-Body PBL1 NDL2 p 1 GFP p + -pickup p 2 f p d r n 3 PBL2 NDL3 n + NDL1 P-Well Drain x Reduction of the Drift Region Length (DRL) Each of p 1, p 2, and f p is scaled down in proportion to the change in d r (DRL). n 3 is not changed to avoid an increase in the electric field near the gate-side drift region edge. y P-Sub. f p : the length of GFP over the drift region d r : the length of the drift region (DRL) n 3 : the length of NDL3 p 1 : the length of PBL1 under the drift region p 2 : the length of PBL2 under the drift region 7

8 Drain Current (μa) Drian Current (μa) I DS -V DS Characteristics of the Proposed Devices Maximum V GS Rating Current Expansion V GS (V) DRL Reduction 15 1 Maximum V GS Rating Current Expansion V GS (V) Boundary of SOA Drain Voltage (V) (a) No DRL reduction device (One Cell: 3.555μm.3μm) SOA excluding the CE region Sufficiently satisfies an operation V DS of 4 V Specific on-resistance R on A = 4.9 mω mm 2 at V GS = 3.3 V Boundary of SOA Drian Voltage (V) (b) 5 % DRL reduction device (One Cell: 2.23μm.3μm) SOA excluding the CE region Sufficiently satisfies an operation V DS of 2 V Specific on-resistance R on A = 18.4 mω mm 2 at V GS = 3.3 V 8

9 Drain Current (A) Drain Current (A) I DS -V GS Characteristics of the Proposed Devices 1E-4 1E-4 1E-6 1E-8 1E-1 V DS (V) 4.1 DRL Reduction 1E-6 1E-8 1E-1 V DS (V) 2.1 1E-12 1E-12 1E-14 1E-14 1E Gate Voltage (V) (a) No DRL reduction device (One Cell: 3.555μm.3μm) Threshold voltage V TH V TH (at I DS =.1 μa and V DS =.1 V) =1.26 V V TH reduction due to a V DS increase ΔV TH (V DS =.1V 4 V) =.14 V Very low leak current even at V DS = 4 V 1E Gate Voltage (V) (b) 5 % DRL reduction device (One Cell: 2.23μm.3μm) Threshold voltage V TH V TH (at I DS =.1 μa and V DS =.1 V) =1.23 V V TH reduction due to a V DS increase ΔV TH (V DS =.1V 2 V) =.1 V Very low leak current even at V DS = 2 V 9

10 Drain Current (A) Breakdown Characteristics of the Proposed Devices 1E-4 1E-6 1E-8 1E-1 5 % DRL Reduction No DRL Reduction Breakdown voltage BV DS (at I DS = A) 5 % DRL reduction device: BV DS =39.8 V Ensures sufficient margin for an operation V DS of 2 V 1E-12 1E-14 1E-16 V GS =V Drian Voltage (V) No DRL reduction device: BV DS =61.9 V Ensures sufficient margin for an operation V DS of 4 V Breakdown Characteristics of the Proposed Devices 1

Electric Field Distributions upon Breakdown Gate GFP

regions Surface DRL Reduction High Electric Field

locations) All in the bulk for both devices V DS =62V,

would not cause damage to the surface and the

11 Electric Field Distributions upon Breakdown Gate GFP Drift Drain Gate Drift GFP Drain High Electric Field regions Surface DRL Reduction High Electric Field regions Surface High electric field regions (Breakdown locations) All in the bulk for both devices V DS =62V, V GS = V DS =4V, V GS =V Even repetitive ESD events would not cause damage to the surface and the intrinsic MOSFET (a) No DRL reduction device (b) 5 % DRL reduction device 11

12 R on A-BV DS Characteristics Renesas (Reliability Driven) (ISPSD217) UMC (ISPSD217) Conventional Proposed R on A-BV DS of the proposed device Almost the same as that presented by UMC at ISPSD217 State-of-the-art level Note: In this simulation, contact and wiring resistances are not considered. 12

= 2 V where the intrinsic MOSFET operates in the saturation mode Caused by DAHC generated by impact ionization in Region A

13 P-Body + Substrate Current (μa) V GS Dependence on I PB + I SUB (Total Hole Current) 4 3 No DRL reduction (V DS =4V) Region A % DRL reduction (V DS =2V) Gate Voltage (V) The peak hole currents for both devices Occur near V GS = 2 V where the intrinsic MOSFET operates in the saturation mode Caused by DAHC generated by impact ionization in Region A A cross-section of the proposed device The damage due to hot carriers becomes the maximum near V GS = 2 V for both devices. 13

14 Electric Field in Minus X-Direction (kv/cm) Electric Field in Minus X-Direction (kv/cm) Electric Field Profiles along the Surface (V GS = 2 V) Gate V GS = 2 V 8 y = 5 nm A GFP Drift Distance (nm) (a) No DRL reduction device V DS (V) 6 Drain V GS = 2 V Gate y = 5 nm B 1 Drift GFP Distance (nm) V DS (V) (b) 5 % DRL reduction device Drain DRL -E xx (kv/cm) I SS (μa) V DS (V) V GS (V) No Reduction 248 (A) % Reduction 254 (B) E xx : Electric field in the x-direction at x = 1 nm I SS : Source current (Electron current) for one cell Note: Hole current by impact ionization = F(E xx, I SS ) Both of the proposed devices would have almost the same hot carrier endurance would likely be able to have high hot carrier endurance due to the dual RESURF structure 14

15 Gate Current (μa) Gate Voltage (V) Turn-n Characteristics and FOM 3.3 V Proposed LDMOS Transistor (One cell) 5 kω 5 MΩ i gs v gs No DRL Reduction: 4 V The circuit used to obtain turn-on characteristics i ds v ds 5 % DRL Reduction: 2 V Solid Line (5 % DRL Reduction) Dashed Line (No DRL Reduction) Time (ps) Turn-on characteristics of the gate current and the gate voltage (one cell) FOM (on-resistance gate charge) Drift Region Length Qg/A (nc/mm 2 ) R on A (mω mm 2 ) FOM (mω nc) No Reduction % Reduction Q g /A: Gate charge density FOM of the no DRL reduction device about 1/3 that of the conventional device (141 mω nc) FOM of the 5 % DRL reduction device much lower than that of the no DRL reduction device due to the lower specific on-resistance 15

dissipation consists of (1) Gate driving loss due to charging and discharging the gate

16 Total Power Dissipation R L Turn-on Turn-off Charge C GD ON OFF R G C GS Discharge Gate charge during turn-on and gate discharge during turn-off Switching and conduction losses The total power dissipation consists of (1) Gate driving loss due to charging and discharging the gate capacitances (C GS and C GD ) through R G (2) Switching loss during turn-on and turn-off (3) Conduction loss 16

17 Total Power Dissipation Density (W/mm 2 ) Switching frequency dependence of P TD Solid Line (5 % DRL Reduction) Dashed Line (No DRL Reduction) D on Switching Frequency (khz) The switching frequency dependence of the total power dissipation density P TD for the proposed devices Components of the switching energy loss density per switching cycle E SW for the proposed devices Drift Region Length E GD [J/mm 2 ] E ON/OFF [J/mm 2 ] E sw [J/mm 2 ] No Reduction % Reduction The P TD of the 5 % DRL reduction device Much lower than that of the no DRL reduction device for each D on (due to lower R on A) Further lower in a high switching frequency region (due to lower E SW ) 17

18 Summary Each of the proposed 2-4 V LDMOS transistors Has a wide SOA enough for 2-4 V operations, respectively Has a state-of-the-art level characteristic for R on A -BV DS Has a very low FOM representing high suppression of conduction and switching losses Would likely be able to have high hot carrier endurance Adequate for harsh environment automotive applications Enhances the flexibility of circuit design. 18

19 Acknowledgement We would like to express sincere thanks to AdvanceSoft Corporation for lending us 3D TCAD simulator. The development of this simulator is assisted by Japan Science and Technology Agency, National Research and Development Agency using A-STEP program. 19

20 Thank you very much for your kind attention! 2

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