NOT RECOMMENDED FOR NEW DESIGN USE DMC2053UVT. Features -3.1A -2.0A. Pin Configuration

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1 YM O OMMDD FO W DSIG US DM253UV OMPLMY PI HM MOD MOSF Product Summary Device BV DSS DS(O) Q 2V Q2-2V Description = +25 V GS = 4.5V 4.5 V GS =.8V 3.5 V GS = -4.5V V GS = -.8V his MOSF is designed to minimize the on-state resistance ( DS(O)) and yet maintain superior switching performance, making it ideal for high efficiency power management applications. pplications Motor ontrol Power Management Functions D-D onverters Backlighting Features Low On-esistance Low Input apacitance Fast Switching Speed Low Input/Output Leakage Fast Switching Speed otally Lead-Free & Fully ohs ompliant (otes & 2) Halogen and ntimony Free. Green Device (ote 3) Qualified to -Q Standards for High eliability PPP apable (ote 4) Mechanical Data ase: SO26 ase Material: Molded Plastic, "Green" Molding ompound. UL Flammability lassification ating 94V- Moisture Sensitivity: Level per J-SD-2 erminals Matte in nnealed over opper Leadframe. Solderable per MIL-SD-22, Method 28 erminal onnections Indicator: See Diagram Weight:.3 grams (pproximate) SO26 Q D Q2 D2 G 6 D S2 2 5 S G G2 G2 3 4 D2 op View op View Pin onfiguration S -hannel S2 P-hannel Ordering Information (ote 5) Part umber ompliance ase Packaging -7 Standard SO26 3/ape & eel Q-7 utomotive SO26 3/ape & eel otes:. o purposely added lead. Fully U Directive 22/95/ (ohs), 2/65/U (ohs 2) & 25/863/U (ohs 3) compliant. 2. See for more information about Diodes Incorporated s definitions of Halogen- and ntimony-free, "Green" and Lead-free. 3. Halogen- and ntimony-free "Green products are defined as those which contain <9ppm bromine, <9ppm chlorine (<5ppm total Br + l) and <ppm antimony compounds. 4. utomotive products are -Q qualified and are PPP capable. utomotive, -Q and standard products are electrically and thermally the same, except where specified. For more information, please refer to 5. For packaging details, go to our website at Marking Information 3 3 = Product ype Marking ode YM = Date ode Marking Y = Year (ex: F = 28) M = Month (ex: 9 = September) Date ode Key Year ode F G H I J K Month Jan Feb Mar pr May Jun Jul ug Sep Oct ov Dec ode O D of December 28

2 O OMMDD FO W DSIG US DM253UV Maximum atings -HL Q (@ = +25, unless otherwise specified.) haracteristic Symbol Value Unit Drain-Source Voltage V DSS 2 V Gate-Source Voltage V GSS ±2 V ontinuous Drain urrent (ote 6) V GS = 4.5V ontinuous Drain urrent (ote 7) V GS = 4.5V Steady State t<s Steady State t<s = +25 = +7 = +25 = +7 = +25 = +7 = +25 = +7 Maximum ontinuous Body Diode Forward urrent (ote 7) I S.5 Pulsed Drain urrent (µs Pulse, Duty ycle = %) M Maximum atings P-HL Q2 (@ = +25, unless otherwise specified.) haracteristic Symbol Value Unit Drain-Source Voltage V DSS -2 V Gate-Source Voltage V GSS ±2 V ontinuous Drain urrent (ote 6) V GS = -4.5V ontinuous Drain urrent (ote 7) V GS = -4.5V Steady State t<s Steady State t<s = +25 = +7 = +25 = +7 = +25 = +7 = +25 = +7 Maximum ontinuous Body Diode Forward urrent (ote 7) I S -.5 Pulsed Drain urrent (µs Pulse, Duty ycle = %) M hermal haracteristics (@ = +25, unless otherwise specified.) otal Power Dissipation (ote 6) hermal esistance, Junction to mbient (ote 6) otal Power Dissipation (ote 7) hermal esistance, Junction to mbient (ote 7) haracteristic Symbol Value Units = +25 P D.8 = +7.5 Steady State J 68 t<s 2 = +25 P D. = +7.7 Steady State θj 4 t<s 72 hermal esistance, Junction to ase (ote 7) θj 39 Operating and Storage emperature ange J, SG -55 to +5 W /W W /W otes: 6. Device mounted on F-4 substrate P board, 2oz copper, with minimum recommended pad layout. 7. Device mounted on F-4 substrate P board, 2oz copper, with inch square copper plate. 2 of December 28

3 , DI U (), DI U () O OMMDD FO W DSIG US DM253UV lectrical haracteristics -HL Q (@ = +25, unless otherwise specified.) OFF HISIS (ote 8) haracteristic Symbol Min yp Max Unit est ondition Drain-Source Breakdown Voltage BV DSS 2 V V GS = V, = 25μ Zero Gate Voltage Drain = +25 SS. μ V DS = 6V, V GS = V Gate-Source Leakage I GSS ± n V GS = ±2V, V DS = V O HISIS (ote 8) Gate hreshold Voltage V GS(H).4. V V DS = V GS, = 25μ Static Drain-Source On-esistance DS(O) V GS = 4.5V, = mω V GS = 2.5V, = V GS =.8V, =.5 Forward ransfer dmittance Y fs 9 S V DS = 5V, = 3.4 Diode Forward Voltage V SD.4. V V GS = V, I S = DYMI HISIS (ote 9) Input apacitance iss 4 53 pf Output apacitance oss 7 9 pf everse ransfer apacitance rss 65 pf V DS = V, V GS = V, f =.MHz Gate esistance g.9 Ω V DS = V, V GS = V, f = MHz otal Gate harge (V GS = 4.5V) Q g 5.7 n otal Gate harge (V GS = V) Q g 2 7 n Gate-Source harge Q gs.7 n Gate-Drain harge Q gd.4 n urn-on Delay ime t D(O) 5 ns urn-on ise ime t 8 6 ns urn-off Delay ime t D(OFF) 25 4 ns urn-off Fall ime t F 8 6 ns V DS = 5V, = 5.8 V DS = V, V GS = 4.5V, G = 6Ω, S = otes: 8. Short duration pulse test used to minimize self-heating effect. 9. Guaranteed by design. ot subject to product testing V =V GS V GS=4.5V V GS=4.V V GS=3.V 2 5 V = 5.V DS = -55 = 85 = 5 2 V GS=3.5V V GS=2.5V = 25 = 25 5 V GS=2.V 5 5 V GS=.5V V DS, DI -SOU VOLG(V) Fig. ypical Output haracteristics V GS, G SOU VOLG(V) Fig. 2 ypical ransfer haracteristics 3 of December 28

4 I S, SOU U () DS(O), DI-SOU O-SIS (ormalized) DS(O), DI-SOU O-SIS ( ) DS(O),DI-SOU O-SIS( ) DS(O), DI-SOU O-SIS( ) O OMMDD FO W DSIG US DM253UV V = 4.5V GS.6.6 = 25 = 5.5 V =.8V GS.4.3 V = 2.5V GS V = 4.5V GS.4 = 85 = = , DI SOU U () Fig. 3 ypical On-esistance vs. Drain urrent and Gate Voltage , DI SOU U () Fig. 4 ypical On-esistance vs. Drain urrent and emperature.5.5 V GS=5V = V GS=V =.7. V V ) ( G L O V D L O H S H.5 G, VGS(H), G HSHOLD VOLG (V) H ) S ( G J, JUIO MPU ( ) Fig. 5 On-esistance Variation with emperature I =m D I =25µ D , MBI MPU ( ) Fig. 7 Gate hreshold Variation vs. mbient emperature J, JUIO MPU ( ) Fig. 6 On-esistance Variation with emperature = V SD, SOU-DI VOLG (V) Fig. 8 Diode Forward Voltage vs. urrent 4 of December 28

5 r(t), SI HML SIS ID, DI U (), JUIO PI (pf) V GS, G-SOU VOLG (V) O OMMDD FO W DSIG US DM253UV f = MHz F ) p ( I P O I U J, rss iss oss V =5V DS V DS, DI-SOU VOLG (V) Fig. 9 ypical Junction apacitance Q g, OL G HG (n) Fig. Gate-harge haracteristics ) ( U I D, D I DSO) Limited D P = s W P = s W P = ms W P = ms W P = ms W P = µs W. J(max) = 5 = 25 V GS = V Single Pulse. DU on * MP Board. V DS, DI-SOU VOLG (V) Fig. SO, Safe Operation rea D =.7 D =.5 D =.3. D =. D =.9 D =.5 D =.2. D =. D =.5 θj(t) = r(t) * θj θj = 64 /W 癈 Duty ycle, D = t/ / t2 t2 Single Pulse......, t, PULS DUIO IMS (sec) t, PULS DUIO IM (sec) Fig. 2 ransient hermal esistance Fig. 2 ransient hermal esistance 5 of December 28

6 -, DI U () -ID, DI U () I- D, DI U () O OMMDD FO W DSIG US DM253UV lectrical haracteristics P-HL Q2 (@ = +25, unless otherwise specified.) OFF HISIS (ote 8) haracteristic Symbol Min yp Max Unit est ondition Drain-Source Breakdown Voltage BV DSS -2 V V GS = V, = -25μ Zero Gate Voltage Drain = +25 SS -. μ V DS = -6V, V GS = V Gate-Source Leakage I GSS ± n V GS = ±2V, V DS = V O HISIS (ote 8) Gate hreshold Voltage V GS(H) V V DS = V GS, = -25μ Static Drain-Source On-esistance DS(O) V GS = -4.5V, = mω V GS = -2.5V, = V GS = -.8V, = -. Forward ransfer dmittance Y fs S V DS = -5V, = -3. Diode Forward Voltage V SD V V GS = V, I S = -.6 DYMI HISIS (ote 9) Input apacitance iss pf Output apacitance oss 7 95 pf everse ransfer apacitance rss 6 9 pf V DS = -V, V GS = V, f =.MHz Gate esistance g 72 Ω V DS = V, V GS = V, f = MHz otal Gate harge (V GS = -4.5V) Q g 7 n otal Gate harge (V GS = -V) Q g 4 n Gate-Source harge Q gs.95 n Gate-Drain harge Q gd.2 n urn-on Delay ime t D(O) 2 ns urn-on ise ime t 2 22 ns urn-off Delay ime t D(OFF) 2 34 ns urn-off Fall ime t F 3 23 ns V DS = -5V, = -6 V DS = -V, V GS = -4.5V, G = 6Ω, I S = - otes: 8. Short duration pulse test used to minimize self-heating effect. 9. Guaranteed by design. ot subject to product testing. 2 -V =V GS 2 V DS = -5.V -V =4.5V GS 5 -V =4.V GS -V =3.V GS 5 -V =3.5V GS -V =2.5V GS 5 -V =2.V GS 5 -V GS=.5V V DS, DI -SOU VOLG(V) Fig. 3 ypical Output haracteristics V GS, G SOU VOLG(V) Fig. 4 ypical ransfer haracteristics 6 of December 28

7 -V GS(H), G HSHOLD VOLG(V) -I S, SOU U () DS(O), DI-SOU O-SIS (ormalized) DS(O), DI-SOU O-SIS ( ) DS(O), DI-SOU O-SIS( ) O OMMDD FO W DSIG US DM253UV DS(O), DI-SOU O-SIS (Ω) V GS = -.8V V GS = -2.5V V GS = -4.5V , DI SOU U () Fig. 5 ypical On-esistance vs. Drain urrent and Gate Voltage.2 V GS DS = = 4.5V -4.5V = 25 = 25 = 85 = 5 = , DI SOU U () Fig. 6 ypical On-esistance vs. Drain urrent and emperature V GS=5V -=5 -V GS=V -= J, JUIO MPU ( ) Fig. 7 On-esistance Variation with emperature J, JUIO MPU ( ) Fig. 8 On-esistance Variation with emperature , MBI MPU ( ( 癈 ) Fig. 9 Gate hreshold Variation vs. mbient emperature V SD, SOU-DI VOLG (V) Fig. 2 Diode Forward Voltage vs. urrent 7 of December 28

8 r(t), SI HML SIS -ID, DI U (), JUIO PI (pf) -V GS, G-SOU VOLG (V) O OMMDD FO W DSIG US DM253UV f = MHz F ) p ( I P O I U J, rss oss iss Q g vs. VGS V DS, DI-SOU VOLG (V) Fig. 2 ypical Junction apacitance Q g, OL G HG (n) Fig. 22 Gate-harge haracteristics 6 ) ( U I D - I, D DS(O) Limited D P W = s P W = s P W = ms P W = ms. J(max) = 5 P W = ms = 25 P W = µs V GS = -V Single Pulse DU on * MP Board.. -V DS, DI-SOU VOLG (V) Fig. 23 SO, Safe Operation rea D =.7 D =.5 D =.3. D =. D =.9 D =.5 D =.2. D =. D =.5 (t) r(t) θj(t) = r(t) * θj J θj = 64 /W 癈 Duty ycle, D = t/ t2 / t2 Single Pulse......, t, t, PULS DUIO IMS (sec) Fig ransient hermal esistance 8 of December 28

9 O OMMDD FO W DSIG US DM253UV Package Outline Dimensions Please see for the latest version. SO26 /2 e D e b /2 (4x) (4x) 2 Seating Plane L c L2 Gauge Plane Seating Plane SO26 Dim Min Max yp D BS b.3.45 c.2.2 e.95 BS e.9 BS L.3.5 L2.25 BS θ 8 4 θ 4 2 ll Dimensions in mm Suggested Pad Layout Please see for the latest version. SO26 Y Dimensions Value (in mm).95 X.7 Y. Y 3.99 Y X 9 of December 28

10 O OMMDD FO W DSIG US DM253UV IMPO OI DIODS IOPOD MKS O WY OF Y KID, XPSS O IMPLID, WIH GDS O HIS DOUM, ILUDIG, BU O LIMID O, H IMPLID WIS OF MHBILIY D FISS FO PIUL PUPOS (D HI QUIVLS UD H LWS OF Y JUISDIIO). Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes without further notice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the application or use of this document or any product described herein; neither does Diodes Incorporated convey any license under its patent or trademark rights, nor the rights of others. ny ustomer or user of this document or products described herein in such applications shall assume all risks of such use and will agree to hold Diodes Incorporated and all the companies whose products are represented on Diodes Incorporated website, harmless against all damages. Diodes Incorporated does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized sales channel. Should ustomers purchase or use Diodes Incorporated products for any unintended or unauthorized application, ustomers shall indemnify and hold Diodes Incorporated and its representatives harmless against all claims, damages, expenses, and attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized application. Products described herein may be covered by one or more United States, international or foreign patents pending. Product names and markings noted herein may also be covered by one or more United States, international or foreign trademarks. his document is written in nglish but may be translated into multiple languages for reference. Only the nglish version of this document is the final and determinative format released by Diodes Incorporated. LIF SUPPO Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the express written approval of the hief xecutive Officer of Diodes Incorporated. s used herein:. Life support devices or systems are devices or systems which:. are intended to implant into the body, or 2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user. B. critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or to affect its safety or effectiveness. ustomers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of Diodes Incorporated products in such safety-critical, life support devices or systems, notwithstanding any devices- or systems-related information or support that may be provided by Diodes Incorporated. Further, ustomers must fully indemnify Diodes Incorporated and its representatives against any damages arising out of the use of Diodes Incorporated products in such safety-critical, life support devices or systems. opyright 28, Diodes Incorporated of December 28

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