1 Introduction and background

Transcription

1 Published in IET Control Theory & Applications Received on 23rd March 2007 Revised on 5th September 2007 ISSN Favorable effect of time delays on tracking performance of type-i control systems A.A. Khan D.M. Tilbury J.R. Moyne Department of Mechanical Engineering, University of Michigan, Ann Arbor, MI , USA Abstract: Time delays in a control system are usually considered to degrade system performance. This is true when stability margins (gain and/or phase margins) of the control system are taken as the performance criteria. However, there are many instances when performance criteria other than stability margins are used for control system design and controllers comparison. For example, tracking error is one such performance criterion that is widely used for designing many real control systems. When tracking error is considered as the performance criterion, it is shown that consistent time delays in the feedback path can actually reduce the steady-state tracking error of a control system to polynomial reference inputs (such as ramps). 1 Introduction and background Time delays have always been considered undesirable in control systems, because of their tendency to reduce stability margins of the system. Most control textbooks, for example [1, 2], show the undesirable effect of time delays on the stability of a system: they reduce the phase margin. On the other hand, there is a tremendous amount of literature dealing explicitly with the analysis and design of controllers to stabilise systems that have been made vulnerable to instability by time delays [3 5]. Theissueoftimedelayinthefeedbackloophasreemerged in recent years with the proliferation of Networked Control Systems (NCS) [6 8]. In an NCS, sensors, actuators and controllers send information across a communication network. Because the bandwih on a network is shared by all nodes, not every node can communicate continuously and there will always be some delay. The rapid advances in communication networks have reduced the magnitude of this delay significantly, but it still cannot be ignored when designing a control system. Many researchers have worked to calculate the upper bounds on the network induced delays for the system to remain stable, but most indicate that time delays unequivocally degrade the control system performance. For example, Branicky et al. [9] state, This delay, either constant or time varying, can degrade the performance of control systems designed without considering it and even de-stabilise the system. Yong et al. [10] state, These (delays) can make the system s performance worse or even make the system unstable. Lian et al. [11] state, This type of time delay could potentially degrade systems performance and possibly cause system instability. Tipsuwan and Chow [12] state, Network delays degrade the NCS control performance and destabilise the system. Yook et al. [13] take the performance measure as the tracking error but assume its degradation because of time delays in their formulation beforehand, by stating, we define the performance degradation function as the difference between the performance of the system with and without time delay. Apart from considering time delays to be bad for control systems, many researchers in the past have also used them to their advantage [14 17]. Many applications of using time delays in the system and time delay control can be found in a recent survey on the topic of time delay systems, including a discussion of the advantages of using time delays in control [18]. A complete survey of the work on time delays in control systems is beyond the scope of this paper. The contribution of this paper is to point out situations in which unmodelled time delays can 210 / IET Control Theory Appl., 2008, Vol. 2, No. 3, pp & The Institution of Engineering and Technology 2008

2 improve the control system performance without explicitly designing controllers for these delays. Specifically, we take the tracking error as the performance criterion and show in a straight-forward manner that when time delay is present in the feedback path then the steady-state tracking error is reduced for type-i control systems (plant þ controller) that have ramp reference inputs. In this paper, we do not design a new controller to compensate for or use time delays to advantage, but merely show their favorable effect on the tracking performance of a control system with a delay-free controller. The system s stability margins are affected by the introduction of time delays, which in turn may affect robustness properties of the system. In situations where reference tracking is more desirable than large stability margins, the introduction of a time delay in the feedback path can be advantageous at the expense of robustness properties of the system. Using simple mathematical analysis, this paper shows that the commonly-held assumption that time delays always degrade the performance of a control system is not true. This paper is organised as follows: Section 2 describes some widely used performance criteria for control system design, whereas in Section 3, we take steadystate tracking error as the performance criterion and derive relationships showing the effects of time delays in the control loop. Section 4 illustrates some example systems and the paper ends with conclusions drawn in Section 5. 2 Performance criteria Control systems are designed to meet several performance criteria, such as stability margins, disturbance rejection, reference tracking, and so on. When comparing different controllers these performance criteria must be quantified. Several criteria are discussed below. Stability is the classical design criterion used in control system design and analysis. In a linear system, the stability margins (gain and phase margins) characterise the stability of the system and are often used as performance criteria. Since a pure time delay adds phase to the system but no gain, a time delay in the loop decreases the phase margin directly [1, 2]. The time delay s effect on the gain margin is not as direct, but typically a time delay will also decrease the gain margin. Disturbance rejection is another widely used performance criterion for real systems. The disturbance input to a system is usually modelled as a random noise. Optimal control design methods can be used to minimise the effect of disturbances on the output, for example H 2 and H 1 controllers minimise the H 2 and H 1 norms (performance criteria) of the transfer function from the disturbance input to the controlled output [19]. Reference tracking provides yet another performance criterion for the design of control systems. Different reference-based performance criteria are used for this purpose, When the step response is important, performance criteria such as rise time, overshoot, settling-time and steady-state error are used for comparison. When ramp and/or sinusoidal reference tracking is important, the tracking error, defined as the difference between the actual system output and the reference, provides a basis for comparison of control system performance (e(t) ¼ r(t) 2 y(t)). Since the tracking error is a time-domain signal depending on the reference signal and the controller, an error norm is typically used for more straightforward comparisons of different controllers. Popular error norms include maximum error and root-mean-square error. However, these norms don t differentiate between transients and steady-state. Therefore other norms like integral of the absolute value of the error (IAE) and integral of the time multiplied by the absolute value of the error (ITAE) are also used [1]. Note that many of these performance criteria are interrelated and improvement in one criterion often results in degradation of another. Indeed, as we show in this paper, a reduction in the tracking error can occur with a decrease in the phase margin. 3 Steady-state error with time delays In this section, we consider the steady-state errors to different reference signals. In a feedback control system, time delays can be present 1. at different locations such as the process and/or the controller, 2. in different paths such as sensor-to-controller, controller-to-actuator, 3. at the devices (sensor, controller and actuator), because of queuing and processing times. From a control point of view all these delays can be lumped together into two main types, sensor-tocontroller delays (sensor delays, t sc ) and controller-toactuator delays (control delays, t ca ), as shown in Fig. 1. & The Institution of Engineering and Technology 2008 IET Control Theory Appl., 2008, Vol. 2, No. 3, pp / 211

3 be found as t max ¼ PM v PM Figure 1 Block diagram of the control system 3.1 System model The reference input r(t) the control input u(t) and the system output y(t) are real-valued scalar signals defined for t 0. All time delays in the feedback loop are lumped together into a forward delay t ca (between the controller and plant) and a feedback delay t sc (between the output and controller). A delayed signal x d (t) is simply a delayed version of a signal x(t): x d (t) ¼ x(t 2 t). Since all signals are assumed to be zero for t 0, the delayed signals are well-defined for t. 0. The error signals e c (t) and e a (t) are computed as the difference between the reference and the delayed and actual outputs, respectively. We consider that the plant can be modelled as a single-input, single-output (SISO) linear time-invariant (LTI) system. That is, the input signal u(t) to the plant is related to the output signal y(t) by a finiteorder ordinary differential equation with constant coefficients [20]. The transfer function of the plant G(s) is the Laplace transform of its impulse response; G(s) is a rational polynomial in the complex variable s with real coefficients [21]. We further assume that the system is strictly causal, implying that the order of the denominator polynomial of G(s) is greater than the order of its numerator polynomial. The controller is also a causal SISO LTI system with transfer function C(s). A pure time delay t has a transfer function given by e 2st [1]. For the convenience of notation, we will define the loop transfer function (with no delay) as L(s) ¼ C(s)G(s). The phase margin of the delay-free system (in radians) is found as PM ¼ /L( jv PM ) þ p where the magnitude of the loop gain is unity at the frequency v PM : jl(jv PM )j ¼ 1. If the magnitude of L(jv) is unity at more than one frequency, the Nyquist plot can be used to find the phase margin, see [1]; if the magnitude is never equal to 1 then the phase margin is undefined. Since the time delay adds a pure phase to the loop, the maximum tolerable time delay for systems with single crossover frequency can The calculation of t max for systems with multiple crossover frequencies is more complex [22] and beyond the scope of this paper. For total time delays greater than t max, the closed-loop system will be unstable; for smaller time delays, the closed-loop system will be stable [1]. It will also be convenient to discuss systems based on their type. Let L(s) be defined as L(s) ¼ L o (s) s m where L o (s) is such that L o (0) is finite (e.g. L o (s) has no poles at the origin). The system type is m, or the number of poles of the open-loop system at the origin [1]. If m 1, the phase margin of the system is always defined. 3.2 Control delays Consider the feedback control system of Fig. 1 and let there be only the control delay (t ca ) in the forward path, thus t sc ¼ 0. Then, the closed-loop transfer function can be computed as T(s) ¼ Y(s) ca R(s) ¼ L(s)e st 1 þ L(s)e st ca We are interested in the tracking error of the system denoted by e a (t) in Fig. 1 (e a (t) ¼ r(t) 2 y(t), subscript a represents actual ). It can be easily verified that for the case of control delays, both the tracking error and the control error (e c (t)) have the same expression E a (s) ¼ E c (s) ¼ E(s) ¼ R(s) Y(s) ¼ [1 T(s)]R(s) (1) Consider a reference signal r(t) that is a polynomial in time, that is, r(t) ¼ t k for t 0; then R(s) ¼ 1/s kþ1. The steady-state error can easily be computed and the effects of control delays on the steady-state error can be analysed. Assuming that the conditions of the final value theorem are satisfied [1], application of the 212 / IET Control Theory Appl., 2008, Vol. 2, No. 3, pp & The Institution of Engineering and Technology 2008

4 theorem to (1) gives the steady-state error [1 T(s)] e ss se(s) s!0 s!0 s k 1 s!0 s k [1 þ L(s)e st ca ] s m s!0 s k [s m þ L o (s)e st ca ] (2) (3) The limit in the above equation exists if the conditions of the final value theorem are satisfied, that is, the closedloop system is stable and all poles of se(s) are in the left half s-plane [1] Thus, the existence of the limit depends both on the system type and the polynomial input order k. Now, taking the derivative of (3) with respect to the delay value t ca, we obtain an expression that shows how the steady-state error depends on the time delay de ss ca s!0 ca mþ1l(s)e st s s k [s m þ L o (s)e st ca ] 2 (4) Equation (4) shows that if the steady-state error exists, it doesn t change with the increase of control delay (as long as t ca, t max ) for any system or reference type. 3.3 Sensor delays In this section, we consider the same feedback control system of Fig. 1 but with only sensor delays (t sc ); thus t ca ¼ 0 and the closed loop transfer function is given by T(s) ¼ Y(s) R(s) ¼ L o (s) s m þ L o (s)e st sc When there are sensor delays, the actual and control errors have different expressions E a (s) ¼ R(s) Y(s) ¼ [1 T(s)]R(s) (5) E c (s) ¼ R(s) Y(s)e st sc ¼ [1 T(s)e st sc ]R(s) (6) Here again, we compute the steady-state errors and analyse the effects of sensor delays. Assuming that the conditions of the final value theorem are satisfied, we have [1 T(s)] e ssa se s!0 a (s) s!0 s k s m þ L o (s)e st sc L o (s) s!0 s k [s m þ L o (s)e st (7) sc ] Now, taking the derivative of (7) with respect to the delay value t sc, we obtain an expression that shows how the actual steady-state error depends on the time delay de ssa sc s!0 L 2 sc o (s)e st s k 1 [s m þ L o (s)e st sc ] 2 (8) Applying the same procedure to (6), we obtain a similar expression for the control steady-state error [1 T(s)e st sc ] e ssc se s!0 c (s) s!0 and the derivative is s!0 s m s k [s m þ L o (s)e st sc ] de ssc sc s!0 s k (9) s mþ1 sc st L o (s)e s k [s m þ L o (s)e st sc ] 2 (10) Equations (8) and (10) can be used to see the effects of sensor delays. Different combinations of reference inputs and system types are considered. For step reference inputs (k ¼ 0), (8) shows that the steady-state actual error does not depend on the sensor delay (as long as t sc, t max ). de ssa sl 2 sc st o(s)e sc s!0 [s m þ L o (s)e st sc ] 2 ¼ 0 8m ¼ 0, 1, 2,...) e ssa ¼ constant (¼ 0 for m. 0), for any t sc, t max For ramp reference inputs (k ¼ 1), however, (8) results in the following expression for the actual steady-state error de ssa sc s!0 L 2 sc o (s)e st [s m þ L o (s)e st sc ] 2 The negative sign shows that the actual tracking error in steady-state decreases with the increase of sensor delay (where t sc, t max ) 8 m ¼ 1, 2,... This can also be seen explicitly by putting k ¼ 1 in (7) and considering the cases when m 1 (for m ¼ 0, the control system can t track ramp reference inputs). For the given values of m and k (7) results into e ssa ¼ 0/0 8 m 1. Using L Hôspital s rule on (7), it can be shown that for all m 1 e ssa ¼ e ssa j (No delay) t sc (11) where e ssa j (No delay) is the steady-state error in the delay free case. For type-i systems subjected to ramp & The Institution of Engineering and Technology 2008 IET Control Theory Appl., 2008, Vol. 2, No. 3, pp / 213

5 reference inputs e ssa j (No delay) ¼ 1=L 0 (0). 0, therefore the absolute value of e ssa will decrease with the addition of sensor delays as long as 1/L 0 (0). t sc. On the other hand type-ii and above systems have e ssa j (No delay) ¼ 0 and the above result shows that with sensor delays in the feedback path e ssa, 0, that is, sensor delay destroys the zero steady-state error property of these systems. For reference inputs with k. 1 no conclusion about e ssa with sensor delay can be drawn from (8). Whereas, using L Hôspital s rule on (7) reveals that e a doesn t converge to a steady-state value for all m. k. Thus sensor delay destroys the zero steady-state error property in these cases and has to be considered in the design of controllers for maintaining stability. For steady-state control error, (10) gives a familiar result: that the control error is independent of the sensor delay (as long as t sc, t max ). de ssc sc s!0 s mþ1 sc st L o (s)e s k [s m þ L o (s)e st sc ] 2 ¼ 0 8 m ¼ 0, 1, 2,... constant, for m ¼ k ) e ssc ¼ 0, for m. k The above results are summarised in Tables 1 and 2, where the following notation is used: (No change), NA (Not Applicable), d (Decreases), b (Increases) and NE (Not Existent). The control error is not affected by sensor delays, whereas the tracking error is reduced for type-i systems with ramp reference inputs. Simulation results show that sinusoidal inputs follow the trend of ramp reference inputs (k ¼ 1). The results in Table 1 can be explained by the fact that the control signal u(t) in Fig. 1 depends directly on the control error (e c (t) ¼ r(t) y(t t sc )). When the reference is time-varying, such as a ramp, larger delays give a larger control error, which in turn increases the control signal and subsequently the output of the system is pushed harder towards the Table 1 Effects of sensor delay on e ssa Degree of reference input System type 0 I II III k ¼ k ¼ 1 NA d b b k ¼ 2 NA NA NE NE Table 2 Effects of sensor delay on e ssc Degree of reference input System type 0 I II III k ¼ k ¼ 1 NA 0 0 k ¼ 2 NA NA 0 reference (e a (t) ¼ r(t) 2 y(t)). If the delay is large enough then the steady-state error may even become negative. Thus, the effect of the time delay is favorable on the tracking error (reducing it), but adverse on the stability margin (decreasing the phase margin). Based on the same reasoning, for step inputs it is logical to conclude that larger delays will increase the overshoot of the output, y(t). This increase in the overshoot can also be explained by the fact that time delays reduce the phase margin of the open loop system, resulting in less damping and larger overshoots. In the case of step inputs, the two error signals have the same value in steady-state since the reference input does not change with respect to time. To consider the effects of transient and steady-state effects together, performance criteria such as IAE and ITAE are widely used in general practice. IAE ¼ ITAE ¼ ð tf t o ð tf t o je(t)j, or Xnf n¼n o tje(t)j, or Xnf je(n)j n¼n o nje(n)j (12) where t o (n o ) and t f (n f ) are the initial and final times of the evaluation period, respectively. 4 Examples In this section, we present two simple examples of type- I systems to illustrate the results of section 3. Since control delays do not affect the steady-state tracking error, we will only consider the case of sensor delays. Furthermore, we will only consider step and ramp reference inputs in these examples, since higher degrees of reference inputs are rarely used. In both of these examples, the controller is designed for a delayfree system to achieve some desired specifications and the analysis is then based on the loop-transfer function L(s). We show the effects of unmodelled time delays on the tracking error of the system without designing new controllers. 214 / IET Control Theory Appl., 2008, Vol. 2, No. 3, pp & The Institution of Engineering and Technology 2008

6 Example I: Type-I system: 40:3 System: G(s) ¼ s(0:01s þ 1) Controller: C(s) ¼ s þ 8 s þ 18 ) L o (s) s þ 8 ¼ 40:3 (s þ 18)(0:01s þ 1) m ¼ 1 For ramp references (k ¼ 1), (9) results in 1 e ssc s!0 s m þ L o (s)e st sc 1 ¼ 0:0558 (13) s!0 L o (s) and (11) gives e ssa ¼ 0:0558 t sc (14) Equation (13) shows that e ssc remains constant for any value of t sc, whereas (14) is linear in t sc. Using the above system and controller, the phase margin is PM ¼ 1.49 rad at v PM ¼ 34.7 rad/s, thus the maximum tolerable delay (t max ) for the closed loop system is 43 ms. The output response for delays of 0 and 42 ms are shown in Figs. 2a and 2b respectively. Here we can see the initial oscillatory behaviour of the response because of an increase in delay, shown in Fig.2b. This is expected, as the result of the reduced phase margin. To compute IAE and ITAE for both the tracking and control errors we use the discrete time versions of (12). For this purpose, we simulated the above system for 6 s and computed the tracking error (e a ) and control error (e c ) at regular intervals of 10 ms. The resulting IAE and ITAE values are plotted against sensor time delay in Figs. 3a and 3b, respectively. Both the IAE a and ITAE a for tracking Figure 2 Ramp response of type-i system a With t sc ¼ 0ms b With t sc ¼ 42 ms Figure 3 Performance metrics for type-i system a IAE against time delay b ITAE against time delay & The Institution of Engineering and Technology 2008 IET Control Theory Appl., 2008, Vol. 2, No. 3, pp / 215

7 error decrease linearly as the time delay increases, suggesting that the amount of overshoot is not significant when compared to the reduction in steadystate tracking error. Since e ssa depends linearly on sensor delay (14) and the steady-state is achieved in a very short time (as shown in Figs. 2a and 2b), the IAE a and ITAE a also vary linearly with respect to sensor delays. On the other hand, the slightly increasing trend of both IAE c and ITAE c for longer delays shows the effect of increasing oscillations in e c as the time delay increases since e ssc remain unchanged. Example II: Non Minimum Phase (NMP) system with ramp reference: System: G(s) ¼ Controller: C(s) ¼ 1:5 ) L o (s) ¼ 0:3 and m ¼ 1 0:2(s 5) s(0:04s þ 1) s 5 0:04s þ 1 For this system, (9) and (7) result in e ssc ¼ 0:6667 and (15) e ssa ¼ 0:667 t sc Thus, there is no effect of delay on e ssc while (15) is linear in t sc. Figs. 4a and 4b show the output response for the cases of 0 and 460 ms delay, respectively. The phase margin for this system is PM ¼ 1.2 rad at v PM ¼ 1.57 rad, so t max for the closed loop system is 767 ms. Here again we see smaller e ssa but more oscillations in the initial response for longer delays. In this example, the output reaches steady-state in a longer time for longer delays therefore we simulated the control system for 100 s and calculated e a and e c at regular intervals of 10 ms. The resulting IAE and ITAE plots are shown in Figs. 5a and 5b. Both the IAE a and ITAE a decrease as the time delay increases showing that reduction in e ssa is significant when compared to the increase in overshoot for this system. However the increase in Figure 4 Ramp response of NMP system a With t sc ¼ 0ms b With t sc ¼ 460 ms Figure 5 Performance metrics for NMP system a IAE against time delay b ITAE against time delay 216 / IET Control Theory Appl., 2008, Vol. 2, No. 3, pp & The Institution of Engineering and Technology 2008

8 overshoot for very long delays is considerable as compared to the reduction in e ss. This larger overshoot coupled with longer time taken to reach the steady-state results in an upward trend in IAE c and ITAE c at larger time delays as shown in Fig Conclusions This paper presented some simple analysis to show that, contrary to many recent statements in the literature, time delays do not always degrade the performance of a control system. The analysis presented in Section 3 showed that, in situations when tracking error is taken as the performance criterion and its steady-state exists for a control system, unmodelled time delays in the feedback path can improve the tracking performance of a type-i system to ramp reference inputs, although the control error remains unchanged. Time delays in the forward path have no effect on the steady-state tracking error of the system as long as stability is maintained. The reduction in tracking error comes at the expense of the reduced phase margin, resulting in larger overshoots. Therefore in situations when transient behaviour is less important than steady-state behaviour, time delays can be used in a control system for improved tracking of ramp-reference inputs. Of course, it is important that the time delays remain smaller than the maximum time delay that can be tolerated by the system. The choice of a particular performance criterion depends upon the physical system and application domain. There is always a trade-off between the transients and steady-state. Performance criteria like IAE and ITAE can be used to quantify this tradeoff. Simulation results presented in this paper show that the IAE and ITAE also decreased with increasing time delay (up to the stability boundary). NCS have many sources of delay such as waiting time for nodes to get access to the network, device delays for encoding sender and receiver addresses to the information being sent and network transmission delays [11]. The analysis in this paper shows that if steady-state tracking error is taken as the performance criterion for the control system, then the control quality of performance (QoP) can be improved for NCS with consistent and predictable (constant) time delays. The effect of random time delays on the control system performance was considered through a simulation study in [23]. 6 Acknowledgments This research was supported in part by the NSF under grant EEC References [1] FRANKLIN G.F., POWELL J.D., EMAMI-NAEINI A.: Feedback control of dynamic systems (Addison-Wesley, 1995, 3rd edn.) [2] NISE N.S.: Control systems engineering (John Wiley, 2000, 3rd edn.) [3] DUGARD L., VERRIEST E.I.: Stability and control of timedelay systems (Springer, 1998) [4] GORECKI H., FUKSA S., GRABOWSKI P., ET AL.: Analysis and synthesis of time delay systems (John Wiley, 1989) [5] MARSHALL J.E.: Control of time-delay systems (IEE Control Engineering Series, 1979) [6] ANTSAKLIS P., BAILLIEUL J. (Eds.): Special issue on networked control systems, IEEE Trans. Autom. Control, 2004, 49, (9), pp [7] CHOW M.-Y. (Ed.): Special section on distributed network-based control sytems and applications, IEEE Trans. Ind. Electron., 2004, 51, (6), pp [8] YANG T.: Networked control system: a brief survey, IEE Proc., Control Theory Appl., 2006, 153, (4), pp [9] BRANICKY M.S., PHILLIPS S.M., ZHANG W.: Stability of networked control systems: explicit analysis of delay. Proc. American Control Conf., 2000, vol. 4, pp [10] YONG H.K., WOOK H.K., PARK H.S.: Stability and a scheduling method for network-based control systems. Proc. IECON, Industrial Electronics Conf., 1996, vol. 2, pp [11] LIAN F.-L., MOYNE J.R., TILBURY D.M.: Network design consideration for distributed control systems, IEEE Trans. Control Syst. Technol., 2002, 10, (2), pp [12] TIPSUWAN Y., CHOW M.-Y.: Control methodologies in networked control systems, Control Eng. Pract., 2003, 11, (10), pp [13] YOOK J.K., TILBURY D.M., SOPARKAR N.R.: A design methodology for distributed control systems to optimize performance in the presence of time delays, Int. J. Control., 2001, 74, (1), pp [14] ILCHMANN A., SANGWIN C.J.: Output feedback stabilisation of minimum phase systems by delays, Syst. Control Lett., 2004, 52, (3 4), pp [15] NICULESCU S.-I., GU K., ABDALLAH C.T.: Some remarks on the delay stabilizing effect in SISO systems. Proc. American Control Conf., 2003, vol. 3, pp & The Institution of Engineering and Technology 2008 IET Control Theory Appl., 2008, Vol. 2, No. 3, pp / 217

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