DIGITAL CONTROLLER DESIGN

Size: px

Start display at page:

Download "DIGITAL CONTROLLER DESIGN"

Brooke Gibson
5 years ago
Views:

1 ECE4540/5540: Digital Control Systems 5 DIGITAL CONTROLLER DESIGN 5.: Direct digital design: Steady-state accuracy We have spent quite a bit of time discussing digital hybrid system analysis, and some time on controller design via emulation. We now look at direct digital design. Specifications: Steady-state accuracy, Transient response Absolute/ relative stability, Sensitivity, Disturbance rejection, Control effort. Steady-state accuracy How well does a control system track step/ramp/... inputs? General formulation: Y (z) = T (z)r(z). The error is: e[k] =r[k] y[k]. InLaplacedomain: E(z) = R(z) T (z)r(z) =[ T (z)]r(z).

2 ECE4540/5540, DIGITAL CONTROLLER DESIGN 5 2 Use the final-value theorem to find ess. Unity-feedback systems: e ss = lim z (z )[ T (z)]r(z). If the system is of the form (unity-feedback) r[k] D(z) G(z) y[k] Then, T (z) = T (z) = D(z)G(z) + D(z)G(z) + D(z)G(z). Let D(z)G(z) = K m i= (z z i) (z ) N p i= (z p i), z i =, p i =. Also, define the Bode Gain m i= K dc = K (z z i) p i= (z p i) z= which is the dc-gain with all poles at z = removed. Consider a step input. e ss = lim z (z ) [ = lim z + D(z)G(z). If K p = lim z D(z)G(z) then e ss = + D(z)G(z) + K p. ] z z

3 ECE4540/5540, DIGITAL CONTROLLER DESIGN 5 3 If N = 0 then e ss =. + K dc If N > 0 then e ss = 0. Now, consider a ramp input. e ss = lim z (z ) [ ] + D(z)G(z) T = lim z (z ) + (z )D(z)G(z). If K v = lim z T (z )D(z)G(z) then e ss = = K v If N = then e ss = T. K dc If N > then e ss = 0 (and so forth). General unity-feedback result Tz (z ) 2 T K dc. Poles and large gains at z = of D(z)G(z) decrease ess but also decrease stability. System design is a tradeoff between steady-state accuracy, relative stability, and complexity.

4 ECE4540/5540, DIGITAL CONTROLLER DESIGN : Direct digital design: Other requirements Transient response If the system is dominated by second-order poles near z =, thenwe can determine pole locations for transient-response (step-response) specifications. t p M p ω n.8/t r 0.9 σ 4.6/t s M p e πζ/ ζ t r t s t To convert these specifications to the z-plane, r = e σ T. Use zgrid to plot locus of constant ζ and ω n. Mark regions of acceptable poles on plot. EXAMPLE: Plot the specifications for Mp 6% ζ 0.5. ts < 0 s σ 0.5. tr.8s ω n. T = 0.2s. Then, r = e σ T = e 0. = 0.9. Our three boundaries are plotted. What is the region of acceptable closed-loop poles?

5 ECE4540/5540, DIGITAL CONTROLLER DESIGN 5 5 For dominant second-order systems, transient-responsedesigncan also be done using frequency-response information. Mp (percent overshoot) and M r (resonant peak) are related through ζ : M p = + e ζ/ ζ 2 M r = 2ζ ζ 2 Use M r < 2 db. Settling time, t s 4 ( 2ζ ω b ζ 2 ) + 4ζ 4 4ζ 2 + 2, where ω b is the closed-loop bandwidth. Also, tr ω b 2. Relative stability Want GM and PM 0. PM 00ζ (especially for second-order systems). Only sure way to measure GM and PM is Nyquist plot. Sensitivity and disturbance rejection If we define S(z) = T (z) then Y (z) = T (z)r(z) + S(z)W (z) + T (z)v (z) =[ S(z)]R(z) + S(z)W (z) +[ S(z)]V (z) for a unity-feedback system.

6 ECE4540/5540, DIGITAL CONTROLLER DESIGN 5 6 Want sensitivity small for good disturbance rejection and tracking, but large for sensor-noise rejection and robustness. This typically places Magnitude of D(e jω )G(e jω ) Steady state Error Boundary Sensor noise and plant sensitivity boundary constraints on the loop gain L(z) = D(z)GH(z). 80 Phase Margin Boundary Control effort There are always physical constraints on control effort. u(t) < # saturation limits t f 0 u(τ) dτ <# finite total resources u 2 (t) < # finite power Designing controllers with constrained control effort can be difficult. Subject of optimal control.

7 ECE4540/5540, DIGITAL CONTROLLER DESIGN : Phase-lag compensation Compensators/controllers come in many varieties. Some common types are phase-lead, phase-lag, and PID. Root-locus and Bode techniques can be used to design compensators. We mostly consider compensation using a first-order system: D(z) = K d (z z 0 ) (z z p ). We first consider using Bode methods to design our compensator, so we need to convert D(z) D(w). D(w) = D(z) z= +(T/2)w (T/2)w which is also first-order, and has transfer function [ ] + w/ωw0 D(w) = a 0, + w/ω wp where ω w0 = zero location and ω wp = pole location in the w-plane; a 0 is the dc-gain. We will eventually need to convert the compensator back to D(z). The correspondences are [ ] ωwp (ω w0 + 2/T ) K d = a 0 ω w0 (ω wp + 2/T ), z 0 = 2/T ω w 0 2/T + ω w0 z p = 2/T ω w p 2/T + ω wp. If ωw0 < ω wp then compensator is a lead compensator. If ωw0 > ω wp then compensator is a lag compensator.

8 ECE4540/5540, DIGITAL CONTROLLER DESIGN 5 8 Phase-lag compensation Aphase-lagcompensatorhasitspoleclosertotheorigin(ofthe w-plane) than its zero (closer to in the z-plane). The Bode plot of a typical lag compensator is ω wp ω w0 20 log 0 (a 0 ) ( ) a0 ω wp 20 log 0 ω w0 ω wp ω w0 90 ( ) a0 ω wp Low-frequency gain is a0,high-frequencygainis20 log 0 ω w0 We consider designing a compensator for the system db. r(t) T D(z) e st s G p (s) y(t) ( e st ) Let G(s) = s G p (s), G(z) = Z[G(s)], G(w) = G(z) z= +(T/2)w (T/2)w Lag controller adds phase. Must be careful NOT to add phase near crossover of G( jω w ).. Therefore, keep both the pole and zero at low frequency. Phase-lag design method (Bode) System ess specifications determine dc-gain a 0. Desired phase margin PM also specified.

9 ECE4540/5540, DIGITAL CONTROLLER DESIGN 5 9. Plot Bode plot of G(w). 2. Determine frequency ω w where phase of G(w) is about 80 + PM + 5.Thecrossoverofthecompensatedsystemwill occur at approximately this frequency. 3. Choose ω w0 = 0.ω w.thisensuresthatlittlephaselagisintroduced at new crossover (actually, about 5... seeabove) 4. At ω w we want D(ω w )G(ω w ) =. Thegainofthecompensatorat high frequency is a 0 ω wp /ω w0. a 0 ω wp G( jω w ) ω = w0 or a 0 ω wp ω w0 = G( jω w ) ω wp = 0.ω w a 0 G( jω w ). 5. Design is complete since we know a 0, ω w0,andω wp.notethatif H(s) =, thenwereplaceg(w) with GH(w). EXAMPLE: Let G p (s) = and T = 0.05 s. s(s + )(0.5s + ) G(z) = z [ ] Z z s 2 (s + )(0.5s + ) = z [ 0.005z z (z ).5z ] 2 z + 2z z z z Plot Bode plot of G(w)

10 ECE4540/5540, DIGITAL CONTROLLER DESIGN 5 0 Magnitude (db) Blue: Plant; Red: Lag; Green: Compensated Phase (deg) Frequency (warped rads/sec) Design spec gives a0 = 0 db, PM = 55. From graph, we see that ω w Also, G( jω w ) G( jω w ) = ( ) = 20 at ωw0 = 0.ω w = and ω wp = 0.ω w a 0 G( jω w ) = Combining the above, and converting from D(w) to D(z) we get Finite-precision problem D(z) = 0.389z z When implementing a phase-lag filter we may have difficulty. Coefficients of filter stored as binary fixed-point values. For example, Value = b b b b for an 8-bit fixed-point value.

11 ECE4540/5540, DIGITAL CONTROLLER DESIGN 5 EXAMPLE: ( ) 2 = ( ) 256 Minimum value that can be represented is zero. 0 = ( ) 0. Maximum value is (0.)2 = ( /256) 0 = ( ) 0. For previous example, need denominator coefficient of but implement Neednumeratorcoefficients (0.389) 0 (0.0000) 2 = ( ) 0 ( ) 0 (0.0000) 2 = ( ) 0 Compensator zero is shifted to causingadc-gainofzero.weget (z ) D(z) implemented = z Magnitude (db) Blue: Plant; Red: Lag; Green: Compensated Phase (deg) Phase margin of 70 (good). System type reduced (bad) Frequency (warped rads/sec) Need more bits in implementation or smarter implementation method.

12 ECE4540/5540, DIGITAL CONTROLLER DESIGN : Phase-lead compensation ] Aphase-leadcompensatorhasitszeroclosertotheorigininthe w-plane than its pole (closer to in the z-plane). Low-frequency gain of 20 log0 a 0 db. a 0 ω wp High-frequency gain of 20 log0 db. (same) ( ) a0 ω wp 20 log 0 ω w0 ω w0 20 log 0 (a 0 ) θ m ω w0 ω wm ω wp ω w0 ω wm ω wp Adds phase. Maximum phase shift occurs at ω wm = ω wp ω w0 geometric mean The phase shift is [ ( ωwp θ m = tan 2 ω w0 ωw0 ω wp )]. At this location, D( jω wm ) =a 0 ωwp ω w0. Note that lead controller decreases phase near crossover. Stabilizing effect, but Increases high-frequency gain,... destabilizing. Design tends to be trial-and-error.

13 ECE4540/5540, DIGITAL CONTROLLER DESIGN 5 3 Phase-lead design method (Bode) System ess specifications determine dc-gain a 0. Desired phase margin PM also specified.. Crossover frequency must be generated ω w (more later). Then, spec is D( jω w )G(ω w ) = must be adequate. ( 80 + PM). Gainmarginnotspecified,but 2. We see that and D( jω w ) = G( jω w ) D( jω w ) = 80 + PM G( jω w ) = θ. 3. Can derive (Appendix I of Phillips/Nagle) a = a 0 G( jω w ) cos θ ω w G( jω w ) sin θ where ω w0 = a 0 /a and ω wp = /b. and b = cos θ a 0 G( jω w ), ω w sin θ Note that this design method only works when certain constraints on the value chosen for ω w are met. First, θ>0 since this is a lead compensator. Also, system must be stable. I) θ>0 leads to G( jω w )< 80 + PM. II) D( jω w ) > a 0 for lead compensator, so G( jω w ) < /a 0. III) b must be positive for stability. cos θ>a 0 G( jω w ). Note: If H(s) = then replace G(w) with GH(w) everywhere. EXAMPLE: Revisit previous example. Unity dc-gain, a0 = and PM 55.

14 ECE4540/5540, DIGITAL CONTROLLER DESIGN 5 4 Choose ωw : G( jωw ) < by condition (II). G( jω w )< 25 by condition (I). Select (arbitrarily) ωw =.2. Then, G( jω w ) = 73,and G( jω w ) =0.45. Thus,conditions(I) and(ii)aremet. Verify: θ = = 48. cos(θ) = 0.67 > G( jω w ) =0.45 so condition (III)ismetaswell. Therefore, our selection for ωw is valid. Continue with design. So, D(w) = a w + a 0 b w + =.70w w (z 0.970) D(z) =. z The PM for this controller is 55 and the GM is 2.3 db. Adifferentchoiceofωw would give same PM but different GM. a = ()(0.4576)(cos(48 )) (.2)(0.4576)(sin(48 )) b = cos(48 ) ()(0.4576) (.2)(sin(48 )) =.70 = Blue: Plant; Red: Lead; Green: Compensated Magnitude (db) Phase (deg) Frequency (warped rads/sec)

15 ECE4540/5540, DIGITAL CONTROLLER DESIGN 5 5 Compare the two examples from an open-loop perspective. Magnitude (db) 60 Blue: Plant; Red: Lead; Green: Lag Phase-lead has larger bandwidth. Phase (deg) Compare from a closedloop perspective. Again, phase-lead has large closed-loop bandwidth or large high-frequency gain Frequency (warped rads/sec) Closed-Loop: Blue: Plant; Red: Lead; Green: Lag Magnitude (db) Step Response Frequency (warped rads/sec) Time (sec.) This may magnify effects due to sensor noise, and accentuate unmodeled high-frequency dynamics. One possible solution is to add a pole to D(w) at high frequency (so not to change PM, buttoreducehigh-frequencygain).

16 ECE4540/5540, DIGITAL CONTROLLER DESIGN : Lead/lag tradeoffs; other compensators In summary, some possible advantages of phase-lag compensation are:. The low-frequency characteristics are maintained or improved. 2. The stability margins are improved. 3. The bandwidth is reduced, which is an advantage if high-frequency noise is a problem. Also, for other reasons, reduced bandwidth may be an advantage. Some possible disadvantages of phase-lag compensation are:. The reduced bandwidth may be a problem in some systems. 2. The system transient response will have one very slow term. This will become evident when root-locus design is covered. 3. Numerical problems with filter coefficients may result. Some possible advantages of phase-lead compensation are:. Stability margins are improved. 2. High-frequency performance, such as speed-of-response, is improved. 3. Phase-lead compensation is required to stabilize certain types of systems. Some possible disadvantages of phase-lead compensation are:. Any high-frequency noise problems are accentuated. 2. Large signals may be generated, which may damage the system or at least result in nonlinear operation of the system. Since the design assumedlinearity, the results of the nonlinear operation will not be immediately evident. Lag-Lead Compensation System specifications cannot always be achieved using a first-order (lead or lag) compensator. For example, low steady-state error may give very large bandwidth if aleadcompensatorisused.

17 ECE4540/5540, DIGITAL CONTROLLER DESIGN 5 7 One option is to cascade lag and lead filters. Mag Phase Lag increases low-frequency gain. Lead increases bandwidth and stability margins. Lead-lag design method (Bode) Design lag first for acceptable Bode gain. Design lead for resulting system to give bandwidth and stability. PID compensation ApracticalPIDcompensatorhastransferfunction [ D(z) = K + T ( ) ( )] z + z + T D. 2T I z Tz Note that a bilinear integrator and a reverse-euler derivative were used. Mag Phase

18 ECE4540/5540, DIGITAL CONTROLLER DESIGN 5 8 Integrator term improves steady-state performance. Derivative term improves stability and PM. PID design method (Bode) Very similar to lead design. Use D(w) = K + Find D(w) such that D( jω w )G( jω w ) = 80 + PM for a selected ω w.letθ = 80 + PM G( jω w ). Then, we can show that and K = cos(θ) G( jω w ) T D ω w + T I ω w = tan(θ). K T I w + KT Dw. Note that TD and T I are not uniquely specified. Choose one to meet some other specification. Increasing T D increases bandwidth. Decreasing T I decreases steady-state errors.

19 ECE4540/5540, DIGITAL CONTROLLER DESIGN : Root-locus design An alternative design method is to use the root locus. Locus uses open-loop D(z)GH(z) information to plot locus of closed-loop poles. By adding dynamics to D(z) we change the locus. Phase-lag controller To design a root-locus lag controller, we assume that the uncompensated system has good transient response but poor steady-state response. We set D(z) = ( ) ( ) z p z z0. z }{{ 0 z z } p K d Note D(z) has unity dc-gain and Kd <. Weplacethepolenear (very near) z = and the zero a little to the left of the pole. Consider the uncompensated locus to the right. Pick a gain K u to give pole locations z a and z a. Assume that these pole locations are chosen to provide good transient response. z z 2 z a z a z 3 Add the lag pole and zero very close to z =. Thetwopolesandzero are so close together, they behave almost like a single pole. The locus is unchanged, except around z =.

20 ECE4540/5540, DIGITAL CONTROLLER DESIGN 5 20 z z 2 z a z 0 z 3 }{{} Expanded scale But, consider the gain Kc to get poles at z a and z a.thecompensator gain K d = z p z 0 <. The uncompensated gain is the gain to put poles at za and z a without D(z). The compensated gain is z a z p K u = z a z 2 z a z 3. z a z K c = z a z p z a z 2 z a z 3 K d z a z 0 z a z z a z 2 z a z 3 K d z a z = K u K d > K u. Therefore, the lag compensator allows us to use larger gain for the same transient response and hence steady-state error is improved. Phase-lag design procedure (root-locus method). Plot locus of uncompensated system. Find acceptable pole locations for transient response on the locus. Set K u = gain to put poles there. 2. Determine from specifications the required gain K c to meet steady-state error requirements.

21 ECE4540/5540, DIGITAL CONTROLLER DESIGN Compute K d = K u /K c. 4. Choose compensator pole location close to z =. 5. The compensator zero is z 0 = z p K d. 6. Iterate (if necessary) to perfection (choosing slightly different pole location). Phase-lead controller Aphase-leadcontrollergenerallyspeedsupthetransientresponse of asystem. D(z) = K d (z z 0 ) (z z p ), K d = z p z 0 >. That is, the zero is closer than the pole to the unit circle. Phase-lead design procedure (root-locus method). Choose desired pole locations z b and z b. 2. Place the zero of the compensator to cancel a stable pole of G(z). 3. Choose either the gain of the compensated system K c or the compensator pole z p such that D(z) is phase-lead. 4. Then, for z b to be on the locus, we must satisfy K c D(z)G(z) z=zb = Solve for the unknown, which is either K c or z p. Note that we only solve for one pole location. The other roots may not be satisfactory. May need trial-and-error approach to design.

22 ECE4540/5540, DIGITAL CONTROLLER DESIGN 5 22 z b z a z 3 z z p z 0 = z 2 z b z a Pole-zero Cancellation Can it occur? If our zero is too far left If our zero is too far right z 3 z 3 z p z 0 z 2 z p z 2 z 0 Either way, the locus is still okay. (What if we tried to cancel an unstable pole?)

23 ECE4540/5540, DIGITAL CONTROLLER DESIGN : Numeric design of PID controllers APIDcontrollerisimplementedviadifferenceequations:e.g., u[k] =u[k ]+ [( K + T + T ) D e[k] T I T or, ( + 2T ) D T e[k ]+ T ] D e[k 2] T u[k] =u[k ]+q 0 e[k]+q e[k ]+q 2 e[k 2] where q 0, q,andq 2 are constants. Different sets of {q0, q, q 2 } give different performance. Can select a set of parameters to satisfy some design specifications. Some types of design spec: IAE : J = k e[k] ISE : J = k e[k] 2. ITAE : J = k k e[k] Over large number of samples, select q ={q0, q, q 2 } to minimize J. Function minimization in one dimension What value of q minimizes J(q) = q 2 + 2q + 5? Start with a guess, then refine until required accuracy is achieved.. Start with a guess. Say, q = 3. J(q) q Set the step size to a small value. Say γ = 0 3,andsetthe gradient test step size δq to a value smaller than γ.

24 ECE4540/5540, DIGITAL CONTROLLER DESIGN Estimate the slope: J J(q + δq) J(q). q ( δq ) J 4. Update parameters: q q γ. q 5. Repeat from (3) until convergence. Note that update is in negative direction of gradient. Function minimization in two dimensions Suppose we need to minimize a function of two variables, q 0 and q.forexample, J(q 0, q ) J(q 0, q ) = (q 0 2) 2 + (q + ) 2. Instead of a curve to track along, we have a three-dimensional surface.. Start with a guess. Say, q 0 = 5 and q = Set the step size to a small value. Say γ = 0 3,andsetthe gradient test step sizes δq 0 = δq to a value smaller than γ. 3. Estimate the slope in the q 0 -direction: J q 0 J(q 0 + δq 0, q ) J(q 0, q ) δq 0 4. Estimate the slope in the q -direction: J q J(q 0, q + δq ) J(q 0, q ) δq 5. Normalize the gradient for better performance = ( ) J 2 ( ) J 2 +. q 0 q

25 ECE4540/5540, DIGITAL CONTROLLER DESIGN Update q 0 and q : ( ) J q 0 q 0 γ q q γ 7. Repeat from (3) until convergence. q 0 ( ) J. q Note: In many dimensions, performance optimization is complicated and global minimum is not guaranteed. Function minimization in three(+) dimensions Our PID controller design problem is a problem in three variables.. Start with a guess. q ={q 0, q, q 2 }. 2. Set the step size to a small value. Say γ = 0 3,andsetthe gradient test step sizes δq 0 = δq = δq 2 to a value smaller than γ. 3. Estimate the slope in the q 0 -direction: J J(q 0 + δq 0, q, q 2 ) J(q 0, q, q 2 ) q 0 δq 0 4. Estimate the slope in the q -direction: J J(q 0, q + δq, q 2 ) J(q 0, q, q 2 ) q δq 5. Estimate the slope in the q 2 -direction: J q 2 J(q 0, q, q 2 + δq 2 ) J(q 0, q, q 2 ) δq 2

26 ECE4540/5540, DIGITAL CONTROLLER DESIGN Normalize the gradient for better performance ( ) J 2 ( ) J 2 ( ) J 2 = + +. q 0 q q 2 7. Update q 0, q and q 2 : ( ) J q 0 q 0 γ q q γ q 2 q 2 γ 8. Repeat from (3) until convergence. q 0 ( ) J q ( ) J. q 2 g=zpk([0.+0.*j 0.-0.*j],[ *j *j 0.8],,-); gamma=0.0; dq=0.00; T=20; wgtfn=[0:t]; % for ITAE q0 = 0.; q = 0.; q2 = 0.; maxiter=40; J=zeros([ maxiter]); for i=:maxiter, d=tf([q0+dq q q2],[ - 0],-); t=feedback(d*g,); s=step(t,t+); J=wgtfn*abs(-s); d=tf([q0 q+dq q2],[ - 0],-); t=feedback(d*g,); s=step(t,t+); J2=wgtfn*abs(-s); d=tf([q0 q q2+dq],[ - 0],-); t=feedback(d*g,); s=step(t,t+); J3=wgtfn*abs(-s); d=tf([q0 q q2],[ - 0],-); t=feedback(d*g,); s=step(t,t+); J(i)=wgtfn*abs(-s); if (mod(i-0,00)==0), J(i), plot(0:t,s); axis([0 T 0.4]); drawnow; end

27 ECE4540/5540, DIGITAL CONTROLLER DESIGN 5 27 p=(j-j(i))/dq; p2=(j2-j(i))/dq; p3=(j3-j(i))/dq; Delta=sqrt(p*p+p2*p2+p3*p3); ] q0=q0-(gamma/delta)*p; q=q-(gamma/delta)*p2; q2=q2-(gamma/delta)*p3; end Optimization progressing: PID Step Responses 300 Learning Curve Amplitude J Time (sec.) Iteration Note that each time we adapt {q0, q, q 2 } we need to simulate the system performance (e.g., output to a step input) four times. Initial guess for K, T I and T D : Ziegler Nichols can give a good initial guess for PID parameters. Rules of thumb for selecting K, TI, T D. Not optimal in any sense just provide good performance. METHOD I: If system has step response like this, A Slope, A/τ Y (s) U(s) = Ae τds τs +, (first-order system plus delay) τ d τ We can easily identify A, τd, τ from this step response.

28 ECE4540/5540, DIGITAL CONTROLLER DESIGN 5 28 Don t need complex model! Tuning criteria: Ripple in impulse response decays to 25% of its value in one period of ripple 0.25 Period RESULTING TUNING RULES: P PI PID K = τ K = 0.9τ K =.2τ Aτ d Aτ d T I = T I = τ Aτ d d T 0.3 I = 2τ d T D = 0 T D = 0 T D = 0.5τ d METHOD II: Configure system as r(t) K u Plant y(t) Turn up gain Ku until system produces oscillations (on stability boundary) K u = ultimategain. Period, P u RESULTING TUNING RULES: P PI PID K = 0.5K u = T I T D = 0 K = 0.45K u T I =.2 P u T D = 0 K = 0.6K u T I T D = 0.5P u = P u 8

29 ECE4540/5540, DIGITAL CONTROLLER DESIGN : Direct design method of Ragazzini An interesting design method computes D(z) directly. Note: The closed-loop transfer function is T (z) = D(z)G(z) + D(z)G(z) ( + D(z)G(z))T (z) = D(z)G(z) D(z)G(z)(T (z) ) = T (z) Can control design be this simple? D(z) = T (z) G(z) T (z). The problem is that this technique may ask for the impossible: (non-causal, unstable... ). Causality: If D(z) is causal, then it has no poles at. D( ) must be finite or zero. Therefore, T (z) must have enough zeros at to cancel out poles at from G(z). T (z) must have a zero at infinity of the same order as the order of the zero of G(z) at infinity. Put another way, the delay in T (z) must be at least as long as the delay in G(z). Stability: If G(z) has unstable poles, they cannot be canceled directly by D(z) or there will be trouble!

30 ECE4540/5540, DIGITAL CONTROLLER DESIGN 5 30 The characteristic equation of the closed-loop system is Let D(z) = c(z) d(z) + D(z)G(z) = 0 b(z) and G(z) = a(z).then + c(z) b(z) d(z) a(z) = 0. Let the unstable pole in G(z) be at α, soa(z) = (z α)a(z). Tocancel it, c(z) = (z α)c(z), and (z α)a(z)d(z) + (z α)c(z)b(z) = 0 (z α)[a(z)d(z) + c(z)b(z)] = 0. The unstable root is still a factor of the characteristic equation! (oops). Unstable poles must be canceled via the feedback mechanism. This imposes constraints on T (z). [ T (z)] must contain as zeros all the poles of G(z) outside the unit circle. T (z) must contain as zeros all the zeros of G(z) outside the unit circle. Steady-state accuracy: Assume that the system is to be of type-i with velocity constant Kv. Note: E(z) =[ T (z)]r(z). We must have zero steady-state error to a step. Therefore or T () =. lim z z (z )[ T (z)] (z ) = 0

31 ECE4540/5540, DIGITAL CONTROLLER DESIGN 5 3 Must have /Kv error to a unit ramp. Therefore lim z Use l hôpital s rule to evaluate: Tz (z )[ T (z)] (z ) =. 2 K v T dt (z) dz =. z= K v [ EXAMPLE: Consider T = s,g(z) = z (z )(z ) Want T (z) to approximate s 2 + s + = 0, or,convertingtoz-plane, z z = 0. ]. So, T (z) = b 0 + b z + b 2 z z z 2. Causality requires T (z) z= = 0 because G( ) = 0, sob 0 = 0. Note that G(z) has no poles outside the unit circle, so don t need to worry about that. Zero steady-state error to a step requires b + b 2 + T () = =. Therefore, b + b 2 + = Steady-state error of /Kv to a unit ramp (let K v = ) dt (z) = K v dz =+ dt (z) dz z= z=

32 ECE4540/5540, DIGITAL CONTROLLER DESIGN 5 32 = (0.5820)[b + 2b 2 + 3b 3 + ] (0.5820)[ (2)] (0.5820) 2, or, b + 2b 2 + 3b 3 + = So, we have two constraints. We can satisfy these constraints with just b and b 2 : Then, and T (z) = b = b 2 = z z z D(z) = T (z) G(z) T (z) Output y(t) and control u(t)/ Step Response Time (sec.) ) (z ) = 3.07(z (z ) (z 0.48). Note that T (z) has two well damped poles. Why the oscillation? U(z) R(z) = D(z) + D(z)G(z) = T (z) G(z) (z ) = 3.07 (z z ) (z )(z ). (z ) This has a poorly damped pole at Aha!Thiscorrespondsto the zero of G(z) at Asolution:Useab3 term in T (z) and add the constraint that T (z) z= = 0.

STABILITY ANALYSIS TECHNIQUES

ECE4540/5540: Digital Control Systems 4 1 STABILITY ANALYSIS TECHNIQUES 41: Bilinear transformation Three main aspects to control-system design: 1 Stability, 2 Steady-state response, 3 Transient response