Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization

Transcription

1 Roust Timing-Awre Test Genertion Using Pseudo-Boolen Optimiztion Stephn Eggersglüß University of Bremen, Germny Germn Reserh Center for Artifiil Intelligene (DFKI), Bremen - Cyer-Physil Systems {Stephn.Eggersgluess@dfki.de} Mhmut Yilmz NVIDIA, Snt Clr, CA 95050, USA {myilmz@nvidi.om} Krishnendu Chkrrty Eletril nd Computer Engineering Duke University, NC 27708, USA {krish@ee.duke.edu} Astrt Advnes in the hip mnufturing proess impose new requirements for post-prodution test. Smll Dely Defets (SDDs) hve eome serious prolem during hip testing. Timing-wre ATPG is typilly used to generte tests for this kind of defets. Here, the fults re deteted through the longest pth. In this pper, novel timing-wre ATPG pproh is proposed whih is sed on Pseudo-Boolen Optimiztion (PBO) in order to leverge the reent dvnes in solving tehniques in this field. Additionlly, the PBO-sed pproh is le to ope with the genertion of hzrd-free roust tests y extending the prolem formultion. As result, the fults re deteted through the longest roustly testle pth, i.e. independently from other dely fults. Experimentl results show tht hzrd-free roust test n e effiiently found for most testle timing-ritil fults without muh redution in pth length. I. INTRODUCTION Dely testing is typilly performed to ensure tht produed hip meets its timing speifition. A serious issue during the post-prodution test is the growing distriution of Smll Dely Defets (SDDs). A SDD is defet with defet size not lrge enough to use timing filure on its own. However, SDDs might use timing violtion when mny of them re umulted. Due to the shrinking feture sizes nd the inresed speed of tody s iruits, the likelihood of filures used y SDDs inreses nd their detetion hs eome ritil issue [1]. An SDD might espe during test pplition when short pth is sensitized sine the umulted dely of the distriuted defet is not lrge enough to use timing violtion. In ontrst, the sme SDD might e deteted if long pth is sensitized [1], [2]. Unfortuntely, ommon ATPG lgorithms usully prefer short pths sine the sensitiztion of these pths is typilly muh esier. Timing-wre ATPG ws proposed in [3], [4]. Here, prelulted timing informtion is used during ATPG to gurntee sensitiztion of the longest pth. By this, the test is more likely to detet SDDs. However, timing-wre ATPG is omputtionlly intensive tsk, sine the serh spe is huge. As result, the run time of timing-wre ATPG inreses signifintly ompred to regulr ATPG s reported in [5]. Besides the length of pth, dely test n e lssified with respet to different qulity levels [6], e.g. non-roust nd roust. A (hzrd-free) roust test promises highest qulity sine it gurntees the detetion of the trget fult independently from other dely fults. Roust tests re more desirle ut typilly hrder to otin. Clssil timing-wre ATPG does not onsider roust test genertion. Therefore, the fult might not e deteted vi the longest pth sine it my e The work of K. Chkrrty ws supported in prt y the US Ntionl Siene Foundtion under grnt OISE msked y other dely fults present in the iruit. A drwk of ommeril ATPG tools is tht they do not provide roust tests. The fult model ALAPTF [2] ws proposed to lunh the trnsition vi one of the longest roust segments ending t the fult site. However, omputtionl intensive geneti lgorithm nd reursive struturl ATPG lgorithm were used to find long pths. A different metri to judge the qulity of test set is the sttistil dely qulity level (SDQL) metri [7]. It mesures the test espes for test set with respet to given dely defet proility. However, it nnot e used in n erly phse sine the olletion of dt from the testing nd mnufturing proesses is neessry. An lterntive to struturl ATPG s used in timing-wre ATPG is ATPG sed on Boolen Stisfiility (SAT) [8]. Here, the serh proess does not work on struturl netlist ut on Boolen formul typilly in Conjuntive Norml Form (CNF). Reent dvnes in SAT solving tehniques led to highly effiient SAT solvers. SAT-sed ATPG ws shown to e highly fult effiient nd the pplition results in signifintly inresed fult overge for lrge industril iruits [9], []. A key spet for the roustness of SATsed lgorithms is the inherent onflit-driven lerning whih effiiently prunes lrge prts of the serh spe. Therefore, it is desirle to employ these tehniques to timing-wre ATPG s well tht these enefits n e leverged. However, SAT solvers n not diretly e used sine they do not hve the ility to proess nturl numer whih is mndtory for inorporting timing informtion. The pprohes presented in [11], [12] use Boolen enoding to enode nturl numers into SAT instne. Then, series of SAT solver lls with different timing ssumptions is used in order to find the longest sensitizle pth through the fult site or ll pths in speified dely rnge, respetively. However, these pprohes re not le to generte hzrd-free roust tests. A different pproh is to pply solvers for Pseudo-Boolen (PB) SAT or Pseudo-Boolen Optimiztion (PBO) [13], respetively. Mny of the PBO solvers strongly rely on the effiient SAT tehniques ut in ddition re le to proess nturl numers in speifi mnner. In ft, SAT solvers often form the ore engine of stte-of-the-rt PBO solvers. The ppliility of PBO in the field of ATPG hs een shown in [14]. Here, As-Roust-As-Possile tests re generted for the pth dely fult model. An optimiztion funtion is used to stisfy s muh roust sensitiztion onditions s possile for speified pth. In this pper, we present novel PBO-sed timing-wre ATPG pproh whih is lso le to generte high-qulity hzrd-free roust tests for the trnsition fult model. PB-

2 1ns d Fig. 1. 4ns 2ns e f 2ns g fult site Exmple iruit for timing-wre ATPG SAT onstrints re used to model the iruit s logi ehvior, fult detetion nd the pth identifition while n optimiztion funtion is responsile for the longest pth lultion. Additionlly, the ility of enoding stti vlues whih is neessry for the roust sensitiztion ondition is integrted into the prolem formultion nd oupled with the pth identifition. As result, the pproh is le for the first time to generte test sensitizing the longest roustly testle pth nd, y this, inreses the qulity of the test set. Experimentl results for roust nd lssil PBO-sed timing-wre ATPG show tht roust tests n e otined with only smll run time overhed or even speed-up. The pper is strutured s follows. Setion II presents the timing-wre ATPG prolem, different sensitiztion onditions, nd introdues si informtion out PBO. Setion III shows how the PB onstrints nd the minimiztion funtion re derived for the timing-wre ATPG prolem. Stti vlue enoding nd the integrtion into the PBO-sed timing-wre ATPG formultion is presented in Setion IV. Setion V presents experimentl results nd Setion VI gives the summry of this pper s well s n outlook. II. PRELIMINARIES A. Timing-Awre ATPG Common ATPG lgorithms tend to sensitize short pths during test genertion due to resons of omplexity. However, this is disdvntgeous for deteting SDDs. Dely defets sed on SDDs re more likely to our on longer pths, sine more SDDs n e potentilly umulted nd the slk mrgin is smller. This is demonstrted y the following exmple. Exmple 1: Consider the simple exmple iruit shown in Figure 1. Eh gte is ssoited with speifi dely. Assume tht the fult site is line g. There re six possile pths through g on whih the trnsition ould e propgted: p 1 = d e g h j (ns) p 2 = e g h j (9ns) p 3 = d e g i k (8ns) p 4 = e g i k (7ns) p 5 = f g h j (7ns) p 6 = f g i k (5ns) Regulr ATPG tools try to find pth on whih the trnsition is propgted s fst s possile. So, it is most likely tht regulr ATPG lgorithm sensitizes the shortest pth p 6, sine this is the esiest pth to sensitize. If the vlue is smpled for exmple t 11ns, the slk mrgin is very high, i.e. the umulted defet size hs to e t lest 7ns for p 6 to detet dely defet. However, if the ATPG lgorithm hooses pth p 1, the defet size hs to e only 2ns for detetion. Timing-wre ATPG [4] ws developed to enhne the qulity of the dely test. Here, test is generted to detet the trnsition fult through the longest pth y using timing l h i 1ns 3ns j k TABLE I SENSITIZATION CRITERIA FOR ROBUST AND NON-ROBUST TESTS Roust Non-roust Gte type rising flling AND/NAND X1 S1 X1 OR/NOR S0 X0 X0 informtion during the serh. The lgorithm proposed in [4] is sed on struturl ATPG nd onsists of two tsks: fult propgtion nd fult tivtion. Eh tsk uses the pth dely timing informtion s heuristi to propgte (tivte) the fult through the pth with mximl stti propgtion dely (mximl stti rrivl time). However, due to omplexity resons, oth tsks re rried out independently nd the longest pth might e missed. Furthermore, simplifitions re ssumed to further redue the omplexity. This motivtes the need for new tehniques tht n ope with the high omplexity. B. Sensitiztion Criteri A test for dely fult hs to onsider two time frmes t 1, t 2. In order to generte test for pth dely fult on pth p, the desired trnsition hs to e lunhed t the input nd p hs to e sensitized to propgte the trnsition. For this, the side inputs of p, i.e. ll onnetions whih re not on the pth ut feed gte on pth, hve to e onstrined to speifi vlues ording to the desired sensitiztion riterion. The sensitiztion riterion used is responsile for the test qulity. Tle I shows the onditions for non-roust s well s roust sensitiztion [6]. For non-roust test, it is suffiient tht ll side inputs of p hve to ssume the non-ontrolling vlue of the gte in t 2 only (denoted y X0/X1). In order to void tht other dely fults msk the fult on p, stti vlues hve to e gurnteed for roust test if the trnsition goes from nonontrolling vlue to ontrolling vlue (denoted y S0/S1). Note tht often two Boolen vriles re used to denote the vlues of signl in two disrete points of time, i.e. t t 1 nd t 2. Setting oth vlues to either 0 or 1 is not suffiient for the roust sensitiztion riterion, sine the time etween t 1 nd t 2 is not onsidered nd hzrds or glithes ould msk the dely fult. C. Pseudo-Boolen Optimiztion In this setion, si informtion out Pseudo Boolen Optimiztion (PBO) nd the relted Pseudo-Boolen (PB)-SAT prolem is given [15] (f. [14]). A pseudo-boolen formul Ψ is onjuntion of pseudo-boolen onstrints. A pseudo- Boolen onstrint ψ over Boolen vriles x 0,..., x n 1 is n inequlity of the form: n 1 i x i n, i=0 where 0,..., n Z nd x i {0, 1}. A pseudo-boolen onstrint ψ is stisfied if nd only if the sum of the oeffiients i with 0 i < n for whih the ssoited vrile x i is tivted, tht is x i = 1, is greter or equl thn n. A pseudo-boolen formul Ψ PB is stisfied if nd only if eh onstrint ψ Ψ is stisfied. The PB-SAT prolem is to find n ssignment tht stisfies Ψ PB or to prove tht no suh ssignment exists. The PBO prolem is to find the stisfying ssignment of Ψ PB whih

3 TABLE II PB AND CNF REPRESENTATION FOR AN AND GATE = PB CNF ((1 ) + (1 ) + 1) ( + + ) ( + (1 ) 1) ( + ) ( + (1 ) 1) ( + ) is optiml, e.g. miniml, with respet to given ojetive funtion F: n 1 F(x 0,..., x n 1 ) = m i x i, where m 0,..., m n 1 Z. The tsk of PBO solver is therefore to find the ssignment whih stisfies Ψ PB nd, t the sme time, minimizes F or to prove tht no stisfying ssignment exists. A iruit-oriented prolem n e formulted s PB-SAT prolem s follows (similr to the SAT trnsformtion [8]): eh signl s j in iruit is ssigned Boolen vrile x j. Then, the iruit s logi hs to e trnsformed into PB onstrints gte y gte y reting set of onstrints ψ g for eh gte g. The similrity to SAT trnsformtion is shown in Tle II, where the CNF s well s the PB-SAT representtion of n AND gte is given. Eh CNF luse orresponds to PB onstrint. Note tht negtive literl x i is represented y the term (1 x i ). The PB representtion Ψ C for iruit C with gtes g 1,..., g k is given y the following formul: Ψ C = k j=0 ψ gj i=0 In prtie, Ψ C is then extended with prolem-speifi onstrints Ψ F whih re for exmple needed for fult propgtion nd tivtion. Then, the derived PB-SAT instne Ψ PB whih n e given to PB-SAT solver to ompute test is s follows: Ψ PB = Ψ C Ψ F Typilly, PBO solvers like lsp [16] internlly trnslte the prolem into SAT instne nd work in itertive mnner: PBO solver lultes n initil solution t first (orresponding to PB-SAT solution) whih is then improved in the following until no etter solution n e found. Generlly, the serh spe of suh prolem is huge nd typilly mny itertions re needed to find the miniml solution. However, PBO solvers use effiient onflit-sed lerning tehniques nd effetive heuristis during the serh. As result, the serh spe n typilly e trversed very quikly, sine lrge prt n e pruned y lerned informtion. Therefore, PBO solvers hve the potentil to ope with the high omplexity of the timingwre ATPG prolem. III. PBO-BASED TIMING-AWARE ATPG This setion desries how the timing-wre ATPG prolem is represented s PBO prolem, i.e. s PB-SAT instne Ψ PB nd minimiztion funtion F. We first desrie in Setion III-A how the PB-SAT instne is omposed nd how the minimiztion funtion is derived. Afterwrds, Setion III-B presents detils out the implitions nd onstrints whih hve to dded to the PB-SAT instne in order to gurntee onsistent pth representtion. A. PB-SAT nd Minimiztion Funtion The use of PB-SAT nd PBO, respetively, hs the dvntge tht the effiient solving nd serh spe pruning tehniques of stte-of-the-rt solvers n e pplied to solve the speifi prolem. However, the orret nd omplete formultion s PBO prolem instne is ruil for the effiient pplition. As stted ove, the use of PBO solver requires the retion of PB-SAT instne Ψ PB nd minimiztion funtion F. The proposed PB-SAT formultion is sed on the SAT formultion for ATPG proposed in TEGUS [17]. As shown ove, ny SAT instne n e trnsformed into PB- SAT instne in strightforwrd mnner ut not vie vers. The test genertion formultion onsists of the following prts: Ψ C desries the logi of the neessry iruit prts. Note tht two onseutive time frmes t 1, t 2 hve to e onsidered for trnsition test genertion. A signl x is therefore ssoited with two vriles x 1, x 2 representing the vlue of the line in the orresponding time frme. Ψ F desries the fulty prt of the iruit. Tht is the fult site s well s the logi of the fulty output one. An dditionl vrile y f is ssigned to eh signl y in the fulty output one whih represents the vlue of y in the fulty prt. Ψ D desries dditionl onstrints neessry for fult propgtion nd fult oservtion. In prtiulr, these onstrints mke sure tht D-hin exists, i.e. there exists pth from the fult site to n oservtion point long whih the fult is propgted. An dditionl vrile y D (lso lled D vrile) is ssoited with eh signl y in the fulty output one. This vrile is 1 if the fult is propgted to n oservtion point long this line. This formultion is extended for the prolem of finding the longest pth through the fult site. Here, ler pth representtion is needed for identifying the longest pth utomtilly y the solver used. The lst prt of the formultion, i.e. Ψ D lredy inludes propgtion pth representtion y the D vriles of the output one. When the vrile y D of signl y is ssigned to 1, the fult is propgted long line y. Therefore, the propgtion pth is represented y the set of lines whose D vrile is 1. More formlly, let Y e the set of lines in the output one of the fult site, then the propgtion pth P p is represented s follows: P p = {y Y : y D = 1} However, this representtion hs to e extended, sine it overs the propgtion pth only. The tivtion pth hs to e onsidered for identifying the longest pth, too. Generlly, setting the desired trnsition vlue t the fult site is suffiient for the solver used to rete n tivtion pth. However, dditionl informtion is required for pth identifition. Therefore, J vrile z J is ssigned to eh line z in the support of the fult site. This is illustrted in Figure 2. Note tht the signl line of the fult site is ssigned D vrile s well s J vrile. Both vriles of the fult site re fixed to 1 in the prolem formultion to trigger the serh. The J vrile z J of line z is 1 if the line rries trnsition long the tivtion pth. Therefore, similr to the representtion of the propgtion pth P p, the tivtion pth P is represented y those lines whose J vrile is ssigned to 1. More formlly, let Z e the set of lines in the support of the fult site, then the tivtion pth P is represented s

4 Fult Site X0 Trnsitive Fnin Cone J vriles D vriles () Trnsition fult X1 () Non roust follows: Fig. 2. D nd J Vriles in PB-SAT trnsformtion P = {z Z : z J = 1} Note tht the onstrints whih gurntee the orret ssignment of the D nd J vrile re given in Setion III-B. Eventully, the omplete pth P f for fult tivtion s well s for fult propgtion is derived y the union of P nd P p : P f = P P p This pth representtion llows the solver to identify the pth y heking the ssignment of the D nd J vriles. This is then used to rete the minimiztion funtion whih is responsile for identifying the longest pth. Therefore, the minimiztion funtion F onsists of the D s well s of the J vriles of the given instne. In ddition, to inorporte the dely spet, eh vrile x in the minimiztion funtion is ssoited with stti dely vlue d x (otined for instne y stti timing nlysis) whih represents the dely of the line s well s the dely of the predeessor gte: 1 n m F(Y D, Z J ) = d yi yi D + d zj zj J i=1 j=1 The result of F is the umultion of the dely vlues of the tivted vriles, i.e. those vriles whih re ssigned to 1 in the urrent ssignment. Given to PBO solver, the ultimte solution is the ssignment whih minimizes F. This diretly orresponds to the longest pth through whih the trnsition fult is deteted. B. Constrints for Consistent Pth Representtion This setion shows whih onstrints or implitions hve to e dded to the PB-SAT instne to gurntee orret nd onsistent pth representtion. This inludes the following properties: It hs to e gurnteed tht the trnsition is tivted nd propgted long t lest one pth. These onstrints re needed for fult detetion nd re desried y Ψ pth. It hs to e ensured tht the D nd J vriles of extly one pth re ssigned to 1, lthough there exist multiple pths long whih the trnsition is propgted or tivted, respetively. This is espeilly importnt sine the minimiztion funtion F is defined over ll D nd J vriles. The solver tries to ssign s mny s possile of these vriles with the vlue 1. These onstrints re desried y Ψ one. Different rrivl times of trnsitions t gte inputs hve to e onsidered in order to mke sure tht the orret 1 Note tht the dely vlue is given in F s negtive vlue, sine stteof-the-rt PBO solvers typilly perform minimiztion ut not mximiztion. 11 () "Semi roust" Fig. 3. S1 (d) Roust (hzrd free) Different sensitiztion exmples pth whih uses the trnsition t the output is identified. This is desried y Ψ trn. In summry, the PB-SAT instne Ψ PB whih inorportes these properties is derived s follows: Ψ PB = Ψ C Ψ F Ψ pth Ψ one Ψ trn The preise implitions or onstrints, respetively, in PB form inluded in Ψ pth, Ψ one nd Ψ trn nnot e given here due to pge limittion. IV. LONGEST ROBUSTLY TESTABLE PATHS Although the longest pth hs een sensitized, different dely fult present in the iruit might msk the trgeted dely fult on the longest pth. Different sensitiztion riteri were developed to prevent this. This is demonstrted in the following exmple. Exmple 2: Consider the AND gte = in Figure 3. Here, different sensitiztion possiilities nd the ssoited prolems re presented. Typilly, trnsition fult testing () onstrins the output only. Tht is, only trnsition hs to e ssumed t the output. In prtiulr, this leds to the possiility tht dely fult on the pth is msked if the trnsition on the side input rrives erlier thn the trnsition on the on-pth input. Non-roust sensitiztion () ignores the ehvior on the side input during the initil time frme. Therefore, dely fult on ould e msked y dely fult on side input. Semi-roust sensitiztion () is often used to prevent the invlidtion of the test y other dely fults. Here, the initil nd the finl vlue of the side inputs re onstrined to the nonontrolling vlue. However, the ehvior etween the initil nd finl time points is unknown. Therefore, glith is le to invlidte the test s shown in Figure 3(). Here, the glith (originted from the side input ) is propgted on nd the orret vlue is (wrongly) smpled t the output. Roust sensitiztion (d) requires the gurntee of stti vlue on ll side inputs. By this, the test nnot e invlidted nor msked out y other dely fults or glithes ( hzrd-free ). In [18], third Boolen vrile x S is ssigned to eh signl line x (S vrile). If x S = 1, the signl is gurnteed to e stti. Constrints Ψ S re dded to ensure tht no glith or hzrd ours y mens of stti vlue justifition. Bsilly, these onstrints gurntee tht stti vlue on the output of gte is used y its gte input ssignment. Tht is either y stti non-ontrolling vlues on ll gte inputs for nonontrolling stti vlue on the output or y stti ontrolling vlue t lest on one gte input for ontrolling vlue on the gte output. By this, the stti vlues re justified y the

5 ssignment of the primry or pseudo primry inputs. However, roust test genertion is typilly pplied for the pth dely fult model where the pth under test is ompletely speified s in [14]. For timing-wre ATPG, the pth is not speified. The serh for the longest pth is expliitly prt of the prolem. The following formultion is proposed to integrte the roust sensitiztion onditions into the proposed PBO-sed timingwre ATPG pproh in order produe test with the longest roustly testle pth through the fult site. At first, eh gte g in the onsidered iruit prt is ssigned n dditionl vrile g S s desried ove. The onstrints Ψ S re dded for eh gte to the iruit formul in order to enle stti vlue representtion. Note tht Ψ S is enpsulted from the originl iruit formul nd serves only for the orret lultion of the S vriles. The im is now to ouple the pth representtion proposed in the previous setion with the ility to gurntee nd justify stti vlues in order to enle the roust sensitiztion riterion. Tht mens, whenever gte is on sensitized pth, the roust sensitiztion ondition hs to e stisfied in ddition to the onditions for fult detetion presented in the previous setion. Sine onsistent pth representtion exists, i.e. whenever D or J vrile is ssigned with 1, the pth segment is sensitized, then this vrile hs to e linked with the roust sensitiztion ondition. In other words, if gte g or the orresponding output onnetion, respetively, is on sensitized pth nd the trnsition is from the non-ontrolling vlue to the ontrolling vlue of the suessor gte h, then ll other side inputs of h hve to ssume stti nonontrolling vlue. More formlly, given onnetion g nd suessor gte h. Let Q e the set of gte inputs of h nd P = Q \ {g} = {p 1,..., p n 1 }, the following implitions hve to e dded to the prolem instne 2 : (g 2 = v) (g D = 1) (p S 1 )... (p S n 1) The trnsformtion of this implition for gte h with n inputs results in n (n 1) PB-SAT onstrints nd is denoted y Ψ R. The prolem formultion for otining the longest roustly testle pth is therefore given y the following formul. The prentheses re used to highlight the enpsultion of the prolem into fult detetion prt nd roust sensitiztion prt. Ψ PB = (Ψ C Ψ F Ψ pth Ψ one Ψ trn ) (Ψ S Ψ R ) Beuse the formultion of the roust sensitiztion onditions is enpsulted, the optimiztion funtion hs not to e modified, sine the pth representtion hs not een hnged in the prolem instne. In order to keep the fult overge high, it is esily possile to detivte the onstrints Ψ R y inrementl ssumptions [19] if the fult is generlly testle ut roustly untestle. By this, lssil timing-wre test n e generted using the informtion lerned in the previous serh proess. V. EXPERIMENTAL RESULTS This setion presents the experimentl results for the proposed PBO-sed timing-wre ATPG pproh. The pproh ws implemented in C++ nd lsp [16] ws used s 2 The implition is given for the propgtion pth only. However, the implition for the tivtion pth is otined y simply sustituting the D vrile y the J vrile. underlying PBO solver. The experiments were onduted on n AMD Phenom (3400MHz, 8192MB, GNU/Linux) using the IWLS 2005 enhmrks without ny test-relted modifitions, e.g. test point insertion. Timing informtion for these iruits were otined y HSpie nd Monte Crlo simultion using 45 nm tehnology. Test genertion ws performed using the lunh-on-pture sheme (rodside tests). Tle III shows the experimentl results. Two different setups were used. The upper prt shows results for performing test genertion for ll trgets, i.e. trnsition fults on inputs nd rnhes. Fult dropping is disled, i.e. 263,440 trgets for iruit ethernet orresponds to 263,440 ATPG lls. The integrtion of timing-wre fult dropping nd test set omption is future work. The lower prt shows the results for timing-ritil fults only s proposed in [20]. Here, only trnsition fults re trgeted tht lie on struturl longest pths within 25% of the lok yle. The timing of the struturl longest pth is ssumed to e the durtion of lok yle (olumn lk in ps). The verge (v.) nd the mximum (mx) length of the sensitized pth for lssil trnsition fult test genertion re given in olumn Clssi TF for omprison. Results of (PBO-sed) timing-wre ATPG re given in olumn Clssi Timing-wre while olumn Roust Timing-wre shows the results for the pproh using roust sensitiztion to inrese the qulity. Column test. gives the perentge of testle fults, while olumn. presents the numer of orts, i.e. those fults for whih no test ould e generted within the limit of,000 onflits. Column opt. gives the perentge of testle fults for whih no gurntee is given tht the optiml solution ws found. Note tht this does not imply tht the generted test is not the optiml solution, i.e. not the longest pth. This mens tht the proof tht there is no etter solution hs not een finished. The totl run time in pu seonds is given in olumn pu. The perentge of roustly testle fults is given in ro. The results show tht PBO-sed timing-wre ATPG is very roust. Only very few fults were orted. The perentge of tests for whih the proof of optimlity hs not een finished is lso low. 3 Conerning the verge nd mximl pth length, timing-wre tests re s expeted signifintly longer thn lssil trnsition tests. Conerning roust timing-wre test genertion, it hs to e pointed out tht the numer of testle fults is deresed only slightly for most iruits. Another importnt pereption is tht the pth length of roust timing-wre tests is only mrginlly deresed in terms of verge s well s mximum length ompred to lssil timing-wre tests. In few ses, roust tests re even longer thn lssil timing-wre tests, e.g. for mem trl. Here, lssil timing-wre ATPG ould not find the optiml solution. Also, the pu time is redued for few iruits, i.e. tv80 nd us funt lthough there is lrge overhed in terms of formul size. This n e explined euse the solving proess hs to trverse the omplete solution spe. Typilly, the solution spe for roust tests is muh smller thn the solution spe for lssil tests. If only the timing-ritil fults re trgeted s often done in prtie, similr oservtions n e mde. Although, the num- 3 For those iruits where the opt. vlue is higher, e.g. systemes nd es ore, inresing resoures led to higher run time nd to signifintly deresed opt. vlue. However, the pth length ould only mrginlly improved. This indites tht often the optiml solution hs lredy een found ut not proven to e optiml.

6 TABLE III EXPERIMENTAL RESULTS ON ATPG RUNS All fults trgeted Clssi TF Clssi Timing-wre (proposed, PBO-sed) Roust timing-wre (proposed) ir. trgets lk v. mx. test.. opt. v. mx pu ro.. opt. v. mx pu tv80 26,228 7,677 2,201 5, % 7 9.1% 2,899 6,960 6, % 0 4.2% 2,773 6,960 4,490 systemes 31,758 12,078 2,740, % % 3,697 11,890 8, % % 3,398 11,890 11,904 mem trl 43,924 5,780 1,1 4, % 0 0.8% 1,526 5,000 3,916 42,6% 0 0,1% 1,506 5,150 4, trl 47,796 5, , % 0 <0.1% 982 5, % 0 0% 981 5, us funt 48,878 5,284 1,7 5, % 0 1.0% 1,389 5, % 0.3% 1,372 5, pi ridge32 73,978 7,432 1,150 6,660 65,6% 5 1.4% 1,423 7,432 2,520 64,2% 0 1.0% 1,401 7,432 2,756 DMA 75,364 6,650 1,585 4, % % 2,137 6,430 17, % % 2,094 6,490 27,116 w onmx 120,322 4,528 1,407 4, % 5 3.0% 1,650 4,528 8, % 0 2.7% 1,673 4,528 11,382 ethernet 263,440 12,192 1,819 11, % % 1,945 11, , % 5 0.4% 1,932 11, ,750 des perf 292,020 6,386 1,141 6,240 0% 0 0,3% 1,983 6,240 21,2 99.7% 0 0.2% 1,969 6,240 34,358 Timing-ritil fults only tv80 3,414 7,677 2, % % 3,312 6,960 1, % 0 5.8% 3,379 6,960 1,081 systemes ,078 6,862, % % 9,862 11, % % 9,3 11, mem trl 2,564 5,780 1,486 4, % 0 6.2% 2,377 5,000 1,302 33,5% 0 0,7% 2,358 5, trl 670 5,664 5,664 5, % 0 0% 5,664 5,664 <1 50.0% 0 0% 5,664 5,664 <1 us funt 1,296 5,284 4,377 5, % 0 <0.1% 4,514 5, % 0 0% 4,514 5,284 8 pi ridge ,432 4,768 6, % 0 2.8% 5,546 7, % 0 1.8% 5,654 7,370 6 DMA 3,090 6,650 2,888 4, % % 4,371 6,430 2, % 0 7.8% 4,362 6,430 4,432 w onmx 14,584 4,528 3,035 4, % 0 3.1% 3,479 4,420 1, % 0 6.4% 3,746 4,420 2,482 ethernet 1,544 12,192 9,936 11, % 0 0%,448 11, % 0 <0.1%,464 11, des perf 550 6,386 4,744 6,240 0% 0 4.7% 4,967 6,240 2,799 0% 0 3.6% 4,976 6,240 4,899 er of trgets is signifintly deresed, the totl run time is quite high sine timing-ritil fults re often hrd-to-detet. However, the numer of orted fults is negligile. Therefore, the time onsuming prt is the optimiztion proedure for these fults. The opt. vlue is lso inresed ompred to the upper prt. It is lso shown tht most of the testle timing-ritil fults re roustly testle nd the verge nd the mximum pth length of lssil timing-wre test genertion nd roust timing-wre test genertion is very similr. Therefore, the roustness of the test set is signifintly strengthened while the ility to detet SDDs is hrdly ompromised. VI. CONCLUSIONS Timing-wre ATPG is importnt to detet smll dely defets. This pper presents timing-wre ATPG pproh sed on Pseudo-Boolen Optimiztion (PBO) in order to leverge the powerful solving tehniques in this field. A PBO formultion for the timing-wre ATPG prolem is given. Furthermore, it is shown how stti vlues neessry for generting roust tests n e integrted in this formultion. As result, the pproh is le to generte tests whih detet the fult through the longest roustly testle pth. The experimentl results show tht for most testle timing-ritil fults roust test n e effiiently generted with few or even no impt on the pth length. By omining timing-wre ATPG nd roust test genertion, the qulity of the test set n e signifintly inresed. Future work is the development of novel fult dropping shemes sed on timing nd sensitiztion riterion s well s novel ATPG-speifi PBO solving tehniques in order elerte to the serh proess nd diminish the time to find the optiml solution. REFERENCES [1] B. Krusemn, A. K. Mjhi, G. Gronthoud, nd S. Eihenerger, On hzrd-free ptterns for fine-dely fult testing, in Int l Test Conf., 2004, pp [2] P. Gupt nd M. S. Hsio, ALAPTF: A new trnsition fult model nd the ATPG lgorithm, in Int l Test Conf., 2004, pp [3] E. S. Prk, M. R. Merer, nd T. W. Willims, The totl dely fult model nd sttistil dely fult overge, IEEE Trns. on Computers, vol. 41, no. 6, pp , [4] X. Lin, K.-H. Tsi, C. Wng, M. Kss, J. Rjski, T. Koyshi, R. Klingenerg, Y. Sto, S. Hmd, nd T. Aikyo, Timing-wre ATPG for high qulity t-speed testing of smll dely defets, in IEEE Asin Test Symp., 2006, pp [5] M. Yilmz, K. Chkrrty, nd M. Tehrnipoor, Test pttern seletion for sreening smll-dely defets in very-deep sumiron integrted iruits, IEEE Trns. on Computer-Aided Design of Integrted Ciruits nd Systems, vol. 29, no. 5, pp , 20. [6] A. Krstić nd K.-T. Cheng, Dely Fult Testing for VLSI Ciruits. Kluwer Ademi Pulishers, Boston, MA, [7] Y. Sto, S. Hmd, T. Med, A. Tktori, Y. Nozuym, nd S. Kjihr, Invisile dely qulity SDQM model lights up wht ould not e seen, in Int l Test Conf., 2005, pp [8] T. Lrree, Test pttern genertion using Boolen stisfiility, IEEE Trns. on Computer-Aided Design of Integrted Ciruits nd Systems, vol. 11, no. 1, pp. 4 15, [9] R. Drehsler, S. Eggersglüß, G. Fey, A. Glowtz, F. Hpke, J. Shloeffel, nd D. Tille, On elertion of SAT-sed ATPG for industril designs, IEEE Trns. on Computer-Aided Design of Integrted Ciruits nd Systems, vol. 27, no. 7, pp , [] S. Eggersglüß nd R. Drehsler, Effiient dt strutures nd methodologies for SAT-sed ATPG providing high fult overge in industril pplition, IEEE Trns. on Computer-Aided Design of Integrted Ciruits nd Systems, vol. 30, no. 9, pp , [11] M. Suer, A. Czutro, T. Shuert, S. Hillereht, I. Polin, nd B. Beker, SAT-sed nlysis of sensitisle pths, in IEEE Symp. on Design nd Dignosis of Eletroni Ciruits nd Systems, 2011, pp [12] M. Suer, J. Jing, A. Czutro, I. Polin, nd B. Beker, Effiient SATsed serh for longest sensitisle pths, in IEEE Asin Test Symp., 2011, pp [13] E. Boros nd P. L. Hmmer, Pseudo-Boolen optimiztion, Disrete Applied Mthemtis, vol. 123, no. 1 3, pp , [14] S. Eggersglüß nd R. Drehsler, As-Roust-As-Possile test genertion in the presene of smll dely defets using pseudo-boolen optimiztion, in Design, Automtion nd Test in Europe, 2011, pp [15] M. Anjos, Pseudo-Boolen forms, in Hndook of Stisfiility, ser. Frontiers in Artifiil Intelligene nd Applitions, A. Biere, M. Heule, H. v. Mren, nd T. Wlsh, Eds. IOS Press, 2009, pp [16] M. Geser, B. Kufmnn, A. Neumnn, nd T. Shu, Conflit-driven nswer set solving, in Int l Joint Conf. on Artifiil Intelligene, 2007, pp [17] P. Stephn, R. K. Bryton, nd A. L. Sngiovnni-Vinentelli, Comintionl test genertion using stisfiility, IEEE Trns. on Computer- Aided Design of Integrted Ciruits nd Systems, vol. 15, no. 9, pp , [18] S. Eggersglüß, G. Fey, A. Glowtz, F. Hpke, J. Shloeffel, nd R. Drehsler, MONSOON: SAT-sed ATPG for pth dely fults using multiple-vlued logis, Journl of Eletroni Testing: Theory nd Applitions, vol. 26, no. 3, pp , 20. [19] N. Eén nd N. Sörensson, An extensile SAT solver, in Int l Conf. on Theory nd Applitions of Stisfiility Testing, ser. Leture Notes in Computer Siene, vol. 2919, 2004, pp [20] X. Lin, M. Kss, nd J. Rjski, Test genertion for timing-ritil trnsition fults, in IEEE Asin Test Symp., 2007, pp