Towards Fully Integrated Power Management
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1 Towards Fully Integrated Power Management Jeffrey Morroni General Manager Kilby Power &D Texas Instruments
2 The Power Management EndGame Invisible 100% Efficiency, 0 Volume EasytoUse omplete power management in 1 chip, no EMI Power Supply On a hip VIN Devices onduction osses harge osses Passives Magnetics apacitors Parasitics Device inging IV Overlap everse ecovery 2
3 Typical oss Breakdown Buck onverter onduction 26% IV Overlap osses 37% Device Switching osses 21% 16% Overlap qrr/diode switching conduction Q Topologies an Improve Upon Some or All of the Above
4 Topology lasses Standard onverters Hybrid onverters esonant onverters 1 AUX Q 3 2 S AUX Q 4 Simple and proven ow ost X Hard Switched X Full VIN rated devices educed Device Voltage Stresses educed Energy Storage In Inductors X Hard Switched X Additional omponent(s) educed or eliminated switching losses Majority of energy storage still in X Additional omponent(s)
5 Hybrid onverter Example 1 Q 3 2 Q 4 Advantages More energy storage in caps, less in inductors ower switch ratings and stress Smaller current ripple Disadvantages Added component Duty cycle limitation 17x smaller footprint 34X smaller volume [Nishijima, 2005] [Shenoy], 2015
6 Hybrid onverter Example V 1 Q 3 2 I 1 I 2 Q 4 V Q1 V Q2 V IN /2 V IN V Applied to 1 V charged through phase 1 path 2 current decreases V Q3 V Q4 V IN /2 [Nishijima, 2005] [Shenoy], 2015
7 Hybrid onverter Example V 1 Q 3 2 I 1 I 2 Q 4 V Q1 V Q2 V IN /2 urrent in both inductors decreases No current flowing through V c V Q3 V Q4 V IN /2 [Nishijima, 2005] [Shenoy], 2015
8 Hybrid onverter Example Q 3 V 1 2 I 1 I 2 Q 4 1 current decreases V Applied to 2 Becomes Phase 2 source 2 current increases V Q1 V Q2 V Q3 V Q4 V IN /2 V IN /2 [Nishijima, 2005] [Shenoy], 2015
9 Hybrid onverter Example V 1 Q 3 2 I 1 I 2 Q 4 urrent in both inductors decreases No current flowing through V c V Q1 V Q2 V Q3 V Q4 V IN /2 V IN /2 [Nishijima, 2005] [Shenoy], 2015
10 Hybrid onverter Example V 1 Q 3 2 I 1 I 2 Q 4 V Q1 V Q2 apacitor Voltage and Inductor currents naturally balanced More energy storage in the capacitor, less in inductors Device rated for V IN /2 X Hard Switched X Additional omponent(s) X Duty ycle imitation V Q3 V Q4
11 Advantages apacitors vs. Inductors V 1 Q 3 2 Q 4 apacitor Voltage and Inductor currents naturally balanced More energy storage in the capacitor, less in inductors Device rated for V IN /2 X Hard Switched X Additional omponent(s) X Duty ycle imitation
12 sp Advantages *B. ElKareh,. Hutter, Silicon Analog omponents V 1 Q 3 2 Q 4 apacitor Voltage and Inductor currents naturally balanced More energy storage in the capacitor, less in inductors Device rated for V IN /2 X Hard Switched X Additional omponent(s) X Duty ycle imitation ~8V ated ~0.1mΩmm 2 ~16V ated ~0.6mΩmm 2 Enables Smaller Die Area $$ Savings
13 BVDSS ating (V) FOM Advantages 14 V 1 12 Q Q Normalized FOM (QG * dson) apacitor Voltage and Inductor currents naturally balanced More energy storage in the capacitor, less in inductors Device rated for V IN /2 X Hard Switched X Additional omponent(s) X Duty ycle imitation ~8V ated ~16V ated ~3x5x better FOM in this example
14 V 2 and IV Overlap osses Q 3 V Q 4 apacitor Voltage and Inductor currents naturally balanced More energy storage in the capacitor, less in inductors Device rated for V IN /2 X Hard Switched X Additional omponent(s) X Duty ycle imitation 1 2 Hard Switching osses educed 1/2V 2 V/2 and decreases w/fom improvements IV Overlap 1 2 V IN 2 I t r Assume same DV/DT and DI/DT as a Buck t halves, 2x more transitions, 1/4 the transition losses
15 Buck onverter vs. S Buck onduction 26% IV Overlap osses 37% Device Switching osses 21% 16% Overlap qrr/diode switching Q conduction
16 Adding It All Up Q 3 V 1 2 Vs. Q 4 Dramatic Size eduction Efficiency the same or better than comparison points Major downside of duty cycle limitations
17 Topology lasses Standard onverters Hybrid onverters esonant onverters 1 AUX Q 3 2 S AUX Q 4 Simple and proven ow ost X Hard Switched X Full VIN rated devices educed Device Voltage Stresses educed Energy Storage In Inductors X Hard Switched X Additional omponent(s) educed or eliminated switching losses Majority of energy storage still in X Additional omponent(s)
18 esonant onverter Example AUX S AUX. Nan,. Ayyanar, A 1 MHz Bidirectional Softswitching DD onverter with Planar oupled Inductor for Dual Voltage Automotive Systems
19 esonant onverter Example AUX ~ S AUX I 1 I AUX Typical Buck Operation Inductor current slews down V AUX V SW
20 ~ esonant onverter Example AUX S AUX I 1 I AUX Q2 remains ON holding switched node at ground SAUX turns ON ramping up current in AUX Once AUX current is greater than current, Q1 oss conducts V AUX V SW
21 esonant onverter Example AUX ~ S AUX I 1 I AUX Turn ON Q1 with ZVS AUX current ramps down to zero after which SAUX is turned off V AUX V SW
22 esonant onverter Example AUX ~ S AUX I 1 I AUX Q1 conducts remainder of interval as in typical buck converter V AUX V SW
23 esonant onverter Example AUX ~ S AUX I 1 I AUX V AUX ZVS turn on of ZS turn off of S AUX No IV turn on losses for X Added conduction losses for S AUX X Added die area for S AUX X Extra component losses V SW
24 Analysis and omparison AUX S AUX Vs. 20% Smaller Die oss Breakdown Buck (1MHz) ZVT (1MHz) ond. oss AUX 1.0x ~2.3x Q OSS 1.0x 0.5x Q rr 1.0x 0x IVOverlap (ON) 1.0x 0x IVOverlap (OFF) 1.0x 1.0x D ond. 1.0x 0.2x P GATE 1.0x 1.2x P TOT 1.0x 0.96x
25 Buck onverter Vs. ZVT onduction 26% IV Overlap osses 37% Device Switching osses 21% 16% Overlap qrr/diode switching Q conduction
26 Opportunities AUX S AUX Vs. 20% Smaller Die If cost is a nonfactor (usually isn't), large efficiency gains possible Other main challenge The Magnetic element onduction osses ore losses ost Size
27 Summary New Topologies offer opportunity to move towards full power supply on a chip Options and alternatives with various pros and cons Still need improvements on: Inductor integration apacitor integration Better FETs Better packages 27
28 Questions
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