Active Clamp Flyback (Part I) Pei-Hsin Liu
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1 Active Clamp Flyback (Part I) Pei-Hsin Liu 1
2 What will I get out of this session? Purpose: Relevant End Equipments: 1. Demo TI s knowledge base on highdensity adapter 2. Fundamental of ACF operation and challenge on ZVS control 1. High Density AC Adapter or Charger 2. USB Power Delivery Chargers 3. AC/DC or DC/DC Auxiliary Power Supply
3 Agenda Introduction of Active Clamp Flyback (ACF) Impact of Nonlinear Capacitance of switching device on ACF 1) Impact on ZVS Voltage Transition 2) Impact on Resonance Clamp Current Summary
4 Cable-end Eff. (%) Adapter Density and Eff Comparison Flyback: PCF or ACF Three-level LLC 20V/65W output 3-level LLC (C) ᵑ ACF (B) ACF PCF(A) (B) 3-Level LLC (A) V ac (V) Soft switching 65W Adapter Topology Power Density f sw (khz) Primary Switches High-side drivers Switching Devices A Passive-clamp Flyback (PCF) 11W/in 3 150~260 1 pcs 0 pcs Si B Active-clamp Flyback (ACF) 14W/in 3 120~165 2 pcs 1 pcs SiC/Si C Three-level LLC 17W/in 3 300~500 4 pcs 3 pcs Si
5 Percentage (%) Issues of DCM Flyback + Passive Clamp Clamp Loss: V 1 P L i f clamp 2 clamp k m( ) sw Vclamp NVo 2 Switching Loss: 1 P C V f 2 2 Switching sw bulk sw V clamp NV o RM6 XFMR (N=3.25, L k =3uH), 650V/650mΩ Silicon FET V clamp =130V, 20V/30W, V bulk =230 2V f sw V bulk i m(+) NVo 7 6 P Clamp /30W P Switching /30W k 200k 300k f sw (Hz)
6 Transition Mode (TM) + Active Clamp P Clamp P Switching P Core P Winding A High Higher Higher Mid B High Mid Lower Lower C 0 (to output) 0 (ZVS) Middle Higher Due to higher i m(-) and (A) Passive-clamp + DCM (B) Passive-clamp + TM (C) Active-clamp + TM V bulk
7 Operation of Active Clamp Flyback (ACF) I II III IV V VII VI I Region I Region II V sw V gs(qh) V gs(ql) i m Region I : As Q L on, i m peak increases and L m stores energy i QL i sec Region II : After Q L off, i m charges C oss(ql) and discharge C oss(qh) so V sw rises to V bulk +V clamp before Q H turns on
8 Operation of ACF: (III to IV) II III I IV V VII VI I Region III Region IV V sw V gs(qh) V gs(ql) i m Region III : i m forces Q H body diode on, so V clamp charges to N V o i QL i sec Region IV : After Q H on, N V o demagnetizes L m, so i m decades. C clamp resonating with L k stores L k energy. L m releases energy to output, i sec = (i m - )N
9 Operation of ACF: (V to VI) II III I IV V VII VI I Region V Region VI V sw V gs(qh) V gs(ql) i m i QL i sec Region V : C clamp resonating with L k releases L k energy to output. Region VI : Output diode switches off as i sec resonating to 0A (ZCS). V clamp demagnetizes L m, so i m decades more negatively.
10 Operation of ACF: (VII to I) II III I IV V VII VI I Region VII Region I V sw V gs(qh) V gs(ql) i m i QL i sec i m(-) ZVS criteria: 1 1 L i C V m m( ) sw sw Region VII : After Q H off, i m(-) discharges C oss(ql) and charges C oss(qh) so V sw falls from V bulk +V clamp to 0V Region I : Q L turns on as V sw close to 0V (zero voltage switching, ZVS)
11 C oss (pf) Junction Capacitance of Si and GaN ZVS criteria: C oss = 47pF (680mΩ +1.8A Si FET) +1.8A i m(pk-pk) =2.25A 1 1 L i C V m m( ) sw ds (RMS) =810mA -0.5A (RMS) =686mA C oss = 15pF (500mΩ GaN FET) +1.44A i m(pk-pk) =1.74A (RMS) =612mA -0.3A (RMS) =530mA Effect on C oss Nonlinearity: Si FET 680mΩ Si FET 180mΩ GaN FET 500mΩ GaN FET 150mΩ V ds (V) For GaN: Linear scaling between R ds(on) and C oss For Si: lower R ds(on) more C oss nonlinearity
12 Agenda Introduction of Active Clamp Flyback (ACF) Impact of Nonlinear Capacitance of switching device on ACF 1) Impact on ZVS Voltage Transition 2) Impact on Resonance Clamp Current Summary
13 C oss (pf) (1) Impact on ZVS Voltage Transition V sw Si FET (680mΩ) GaN FET (500mΩ) From Q H Affect: (1) Longer dead time f sw limitation (Q H off to Q L on) GaN FET (500mΩ) From Q L Si FET (680mΩ) (2) Virtual short as gate off Higher i m(-) V ds (V)
14 Voltage (V) Voltage (V) Current (A) Current (A) V gs(qh) ZVS Criteria: C clamp design to Reduce Upper Flat Area Improve: Resonance > Q H on time to reduce its nonlinear cap effect (C clamp =100nF) (C clamp =600nF) i m i m(-) -0.9A V sw (180mΩ Si FET) 340ns 1 1 L i C V m m( ) sw ds V gs(qh) ZVS Criteria: i m V sw (180mΩ Si FET) 340ns i m(-) -0.8A (-) L i L i C V m m( ) k clamp( ) sw ds
15 DC/DC Efficiency C oss (pf) Partial ZVS to Reduce Lower Flat Area Condition: 20V/30W, RM6, C3/C3 (SPP02N60C3), Secondary SR (BSC360N15NS3) (RMS=0.717A) (RMS=0.626A) Full ZVS V sw Partial ZVS V sw Partial ZVS Full ZVS V bulk (V) nF Si FET 680mΩ 26.2% less conduction loss!! 263pF V ds (V)
16 P Switching (W) Loss Reduction (W) (RMS) (A) Trade-off of Partial ZVS for Si FET Condition: 20V/30W, RM6, C3/C3 (SPP02N60C3), Secondary SR (BSC360N15NS3) (gain) Conduction loss reduction V sw V sw 0.57 ZVS point (V) V bulk =375V ZVS point (V) For Si, larger loss reduction at 10V; Peak at 20V For GaN, full ZVS gives best efficiency (Lost) Turn-on loss increasing ZVS point (V)
17 (2) Impact on Resonance Clamp Current vs. Schottky Condition: V bulk =325V, V o =20V/30W Primary Switch Secondary Rectifier Schottky diode Sync. Rectifier (SR) Silicon vs. GaN SR Silicon FET (650mΩ) -0.5A -0.55A Observation: (RMS) =686mA (RMS) =600mA Loss C oss on primary (GaN) + Higher C oss on secondary (SR) Significant less Primary RMS current GaN FET (500mΩ) -0.3A (RMS) =530mA -0.35A (RMS) =349mA
18 C oss (pf) 1A/div Si FET: Slower dv sw /dt, Less d /dt di pri dt 1 [ N Vsec Vpri ] L k Voltage polarity change on L k eliminates the current dip. (A) 1.6 i m 1.2 Silicon C C oss(sr) /N 2 oss(qh) : Si V pri < N V sec as higher C oss(qh) 10 (V) μs/div 0.8 (low C oss(qh) ) (V) V pri NV sec (high C oss(qh) ) (high C oss(sr) ) 10ns/div
19 C oss (pf) 1A/div GaN FET: Faster dv sw /dt, Larger d /dt GaN C oss(sr) /N 2 C oss(qh) : GaN di pri dt 10 (V) [ N Vsec Vpri ] L k 1μs/div V pri > N V sec as V sw rising (V) Negative di/dt reduces, so (A) 1.3 more i m is delivered to output V pri i m (high C oss(sr) ) NV sec 10ns/div
20 AC/DC Efficiency Trade-off of C oss(sr) to GaN-based ACF Condition: V o =20V/30W, RM6, 650V/500mΩ GaN R ds(on) C oss(sr) Q g 0.95 SR1 36mΩ 106pF (@75V) 12nC SR1 SR2 Schottky 0.89 V ac SR2 16mΩ 214pF (@75V) 23nC +1.32A +1.4A -0.35A -0.4A SR1 (V bulk =325V) Higher C oss(sr) : (Pros) Less resonance energy for less RMS current (Cons) - Larger ZVS energy results in higher i m(pk-pk), higher core loss - Larger driving loss from higher Q g i m(pk-pk) =1.67A (RMS)=443mA SR2 (V bulk =325V) i m(pk-pk) =1.8A (RMS) =432mA
21 (RMS) (A) DC/DC Efficiency (%) Full-Load Eff Comparison: GaN vs. Si Condition: 20V/30W, RM6, SR (BSC360N15NS3), Si FET(600V, 680mΩ) ; GaN (650V, 500mΩ) 600V Si+ Partial ZVS 650V GaN+ Full ZVS 2% 600V Si+ + Partial ZVS 650V GaN+ Full ZVS 3% V bulk (V) V bulk (V) Eff difference at low line will >2% as including input stage!
22 Conclusion Clamping and switching losses are the limitation of passive clamp flyback converter. Active clamp flyback (ACF) eliminates clamping and switching losses in tradeoff with conduction loss and transformer core loss. GaN-based ACF has advantage over silicon due to less winding loss and core loss. C oss nonlinearity impact and potential solutions using Si FET are addressed. (a) Clamp cap design to overcome high C oss on the high-side switch (b) Partial ZVS to overcome high C oss on the low-side switch
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