Parasitics in Power Electronics Avoid them or Turn Enemies into Friends

Transcription

1 ECPE Workshop Future Trends or Power Semiconductors ETH Zürich, Parasitics in Power Electronics Avoid them or Turn Enemies into Friends Fraunhoer Institute or Integrated Systems and Device Technology (FhG-IISB) Schottkystrasse Erlangen / Germany Tel /

2 Are Modern Power Semiconductors too Fast? Snapped up Statements. we had to extra slow-down our latest power semiconductors... Help, the new power semiconductors are uncontrollable why itching so ast?... the passive components can not keep pace with this development the expense or EMC measures will over-compensate other earnings in system perormance... 2

3 Ultra-ast Switching with Modern Power Semiconductors Unipolar Devices allow itches without a orward threshold voltage also with wide band-gap (WBG) materials like SiC or GaN; eature an inner control mechanism that can be considered as ininite ast or nearly any power electronics application; show dynamic properties that are basically deined by the parasitic elements on chip and package level. G chip D R d C gd C ds R g C gs S MOSFET, JFET, Schottky-Diode (SBD) etc. are device concepts basically without any relevant restriction in dynamic perormance. 3

4 Eiciency Ultra-ast Switching with Modern Power Semiconductors Power Density vs. Eiciency Perormance Factor 1) FOM QP Q P P Power Quality Factor Q P W FOM QP in cm Power Density P [W/cm 3 ] Power Quality Factor Q P Eiciency P loss QP Q 1 P P out Power Density P out W P 3 Vol cm 1) FOM: Figure-o-Merit 4

5 Ultra-ast Switching with Modern Power Semiconductors What s most important? Controllability 1) Parasitics 2) EMI 1) o the active devices 2) on device and system level 5

6 Feedback Capacitance C gd [pf] Ultra-ast Switching with Modern Power Semiconductors Controllability Controlling the dv/dt D 1. V gs V gs,th C gd 1. 1 SJ-MOSFET D-MOSFET G R g I g S V ds I d t 1 dv ds dt t 3 t 3 t 4 t 5 t 6 t 7 t 8 t 1 I d t Drain-Source Voltage V ds [V] dvds( t) dt C gd I g ( V ds ) Controllability is lost i C gd becomes too small but also i t 5 - t 1 >> t 3 - t 3 1) 1) because pulse timing becomes no longer manageable in real applications using simple gate resistors or dv/dt control. 6

7 Ultra-ast Switching with Modern Power Semiconductors Controllability di/dt Limitations load I g R G I d I d V q,g V gs R G load current L S V LS driver current V gs V q, G R G I g L S did ( t) dt di g ( t) dt Even very small source inductance values severly limit the itching speed! = 3 L S = 1 nh und di/dt = 3 A/nsec 7

8 Ultra-ast Switching with Modern Power Semiconductors... without leaving beaten tracks, it becomes a losing battle against parasitics drain package L d chip C gd R d C ds gate L g R g C gs L s R s source Typ. Package Inductances Module TO-247 TO-22 L d [nh] 2...4** 4..7 (<1)* 3..5 (<1)* L g [nh] L s [nh] * via tab ** total inductance (Ld+Ls) 8

9 Limitations o Hard itching Commutation Cell Impedance L S V (t) V V L S di dt (1) I V V t With the itching time t and the relative over-voltage k 1 V V it ollows rom eq. (1): k1 V LS tsw I or V Z I! LS k t 1 SW Example k L S 1 t SW 1nH 1% 1nsec 1 V A I the commutation cell impedance drops in the range o a ew Ohms or below, it becomes more and more impracticable to realize the low loop inductance necessary or very ast itching. 9

10 Limitations o Hard itching Commutation Cell Impedance Example: 3 A DC/DC Converter L S Z V 3V 1 I 3 A Z V 3V 1 I 3 A n = 1 I V I L! S Z k1 t SW V 1 x I The realization o a 1 nsec itching time would require a total loop inductance (L s ) o 1 nh or below,. which is obviously impracticable! Multiphase concepts are a powerul approach to overcome the problems o a to low commutation cell impedance, but are not deployable in all applications. 1

11 Limitations o Hard itching Dynamic Node Impedance Even with dynamically ideal 1) power semiconductors intrinsic losses occur under hard itching conditions: P To keep the intrinsic dynamic losses below a certain percentage k 2 o the processed power 2), i.e. 1 2 v,int C R oss, e on I V 2 2 e E the ollowing impedance constraint must be ulilled: k 2 oss V 2 I I e V I Example C oss,e o a 19m/6V CoolMOS: 8 pf Z V I! C k2 oss, e C oss, e k 5% 8 pf1mhz 2 V 625 A Note: The intrinsic dynamic losses are present also under no-load conditions 3). 1) unipolar behaviour in the 1. and 3. quadrant 2) Coss,e: (energy) eective output capacitance; here: total capacitance loading the node (consider actor 2 in a hal-bridge topology) 3) k2 must be less than a ew percent thereore to get an acceptable part-load eiciency 11

12 Limitations o Hard itching Impedance Constraints in Hard Switched Topologies The window o best perormance becomes smaller with increasing requency LS k t 1 SW Z Z C k2 oss, e Impedance [V/A] Z opt R on Coss, e Multi-Phase Topologies The alternative: Sot or Resonant Switching Multi-Level Topologies 12

13 Power Losses [W] Limitations o Hard itching Intrinsic Losses in Hard Switched Topologies Total Losses P R A ( A) on 2 ( A) v, total( A) Ie Eoss A dynamic P v,min 2 I e R ( A) on E ( A) oss static 2 I e R on E oss Active Chip Area A [mm 2 ] Circuit FOM o power semiconductor technology 1) A opt I e R E ( A) on ( A) oss 1) as a Figure-o-Merit (FOM) this term characterizes a technology not only a certain device! 13

14 Power Losses [W] Limitations o Hard itching Intrinsic Losses in Hard Switched Topologies Total Losses dynamic static Active Chip Area A [mm 2 ] P v,min Using R ( A) on P E C v,min oss ( A) oss, e I e 1 2 C R on V oss, e C max V oss, e 2 max and the output cut-o requency 1 2 the loss minimum can be written as resulting in an upper eiciency limit o approximately: max 1 2 * 22 1) 22 * considers total node capacitance 14

15 Limitations o Hard itching Intrinsic Losses in Hard Switched Topologies Example Output cut-o requency o CoolMOS C3 technology: 1 2 C oss R 1 2 8pF,5 22, e on,15 C 4,GHz I e V I With no additional capacitive loading o the dynamic node, the upper eiciency limit is: ideal diode max 1 P v,min P in ,9% @ 1kHz 1 khz 1MHz with P in V I 2 V e max I e 2 Even in an ideal circuit environment it is not possible to exceed this eiciency under hard itching conditions! 1) values taken rom a SPP2N6C3 15

16 Eiciency [%] Limitations o Hard itching Comparison o DC/DC converter solutions using dierent PS 1) technologies Bipolar / Bipolar Si-IGBT / Si-Diode (6 V) Output power: 1 kw (max.) Switching requency: 17,5 khz Eiciency: 99% (max.) Topology: Multiphase Buck/Boost Power density: ca. 1 kw/liter Boost mode: 24 V 38 V Output Power [kw] 1) Power Semiconductor 16

17 Eiciency [%] Limitations o Hard itching Comparison o DC/DC converter solutions using dierent PS 1) technologies Bipolar / Unipolar Si-IGBT / SiC-Diode (6 V) Output power: 1 kw (max.) Switching requency: 1 khz Eiciency: 97,5% (max.) Topology: Multiphase Buck/Boost Power density: 25 kw/liter 1 95 Buck mode: V HV = 45 V, V LV = 3 V with phase removal w/o phase removal 9 number o active phases Output Current I LV [A] 1) Power Semiconductor 17

18 Eiciency [%] Limitations o Hard itching Comparison o DC/DC converter solutions using dierent PS 1) technologies Unipolar / Unipolar Si-MOSFET / SiC-Diode I unipolar Output power: 12 kw (max.) Switching requency: 2 khz Eiciency: 98,75% (max.) Topology: Multiphase Buck/Boost Power density: 4 kw/liter 1 99 unipolar U 98 V HV Buck/Boost Mode V LV = 333 V V HV = 4 V V HV = 45 V V LV Output Power [kw] 1) Power Semiconductor 18 A project in cooperation o and

19 Current I L [A] Voltage V HS [V] Limitations o Hard itching Comparison o DC/DC converter solutions Unipolar / Unipolar Si-MOSFET / SiC-Diode 5 4 Turn o V HS 5 4 Switching requency: 2 khz overvoltage 45V (@35A) dv HS /dt ca. 2 V/ns 3 3 I L 2 1 Mode: Buck Time base [1 µs/div] Even in the 1 kw power range the current and voltage transients are controllable with a well-designed set-up. Note the low turn-o overvoltage and oszillations. 2 1 Volt Turn on di D /dt ca. 3 A/ns dv HS /dt ca. 17 V/ns Time base [2 ns/div] 19

20 Eiciency Limitations o Hard itching Better Perormance by Faster Switching Power Quality Factor Q P bipolar/bipolar 17,5 khz 1 kw DC/DC converters in comparison bipolar/unipolar 1 khz unipolar/unipolar 2 khz FOM QP 1 3 W in 3 cm Power Density P [W/cm 3 ] Perormance Factor 1) FOM QP Q Power Quality Factor Q P P P out P loss Power Density P out W P 3 Vol cm P 1) FOM: Figure-o-Merit 2

21 Ultra-ast Switching with Modern Power Semiconductors RF-like Device and System Designs are Mandatory Key success actors are minimization o parasitics capacitors with exceptional high current rating eective cooling o active and passive devices high robustness (thermo/mechanical) 21

22 Ultra-ast Switching with Modern Power Semiconductors EMI Encapsulation DC DC DC/DC converters relatively easy to perorm eective ilters, shields and damping materials available DC AC DC/AC inverters 1) more critical due to accessible AC node ilters at the AC terminal i necessary can become quite expensive 1) like inverters or drives, PV, welding, induction heating, lamp ballast, etc. 22

23 Ultra-ast Switching with Modern Power Semiconductors Resonant and Sot Switching Hard Switching Zero Voltage Switching Basic Cell V DS V DS I d I L I L I cap itching losses I channel itching losses I cap V DS ZVS ideally its to the intrinsic properties o unipolar power semiconductors Especially interesting i requency can be chosen so high that resonant elements can be realized by circuit parasitics (turn enemies into riends) Allows itching requencies up to deep in the megahertz range when using a pure unipolare PS 1) design 1) Power Semiconductor 23

24 Ultra-ast Switching with Modern Power Semiconductors Take Care o Parasitic Resonances Circuit L σ C dgs Package Chip Basic ZVS cell =? Unwanted oscillations are preprogrammed C ext The ZVS basic cell structure is no carte blanche or oering ultra-ast power semiconductors in unsuitable packages! 1) C dgs : Feedback stray capacitance o circuit layout 24

25 Are Modern Power Semiconductors too Fast? Conclusion Power Semiconductors can never be too ast! but their controllability must be preserved and optimized by the manuacturers, they must be provided in appropriate packages, and must be operated in suitable circuit topologies and system environments. Unipolar devices then allow to enter new regions in the trade-o between eiciency and power density. Modern unipolar WBG 1) devices allow the extension o the perormance level reached in the application ields o 6V Si devices towards much higher voltages. 1) Wide band gap 25

26 Power [W] Electron Vacuum Tubes Ultra-ast Switching with Modern Power Semiconductors Fields o Application Inductive Heating hardening, welding, cooking Dielectric Heating Plasma Generation lasers, plasma treatment Drives Power Supplies DC/DC Converters Microwave oven Power Semiconductors 1,1, Frequency [MHz] 26

27 ECPE Workshop Future Trends or Power Semiconductors ETH Zürich, Thank You or Your attention! Fraunhoer-IISB Your best resource or all aspects o power electronics 27