AUDIO PROCESSOR with Subwoofer Output

Transcription

1 AUDIO PROCESSOR with Subwoofer Output GENERAL DESCRIPTION The NJW1163 is a sound processor with subwoofer output includes all of functions processing audio signal for TV, such as tone control, balance, volume, mute, and AGC functions. Also the NJW1163 includes the LPF for subwoofer output and bass boost function. The original surround system reproduces natural surround sound and clear vocal orientation. All of internal status and variables are controlled by I 2 C BUS interface. PACKAGE OUTLINE NJW1163V FEATURES Operating Voltage 7.5 to 13V 3ch Output(Lch, Rch, Subwoofer ch) / 2ch Output(Lch, Rch) LPF Filter (Adjustable cut off frequency by external parts) AGC Circuit (It reduces volume difference among input sources.) Adjustable AGC boost level by external parts and AGC compression level by I 2 C BUS eala(njrc Original Surround System) Simulated Stereo I 2 C BUS Interface Bi-CMOS Technology Package Outline SSOP32 BLOCK DIAGRAM AGC1 SS-FIL TONE -Ha TONE -La LF1 LF2 LF3 OUTa SCL SDA ADR IN a IN b AGC VOL1 VOL1 eala & Simulated Stereo TONE TONE LPF VOL2 VOL2 VOL2 Trimmer I 2 CBUS Interface Bias CVA CVB CVW CTH CTL CSR PORT1 PORT0 AUX1 AUX0 GND V+ AGC2 SR-FIL TONE -Hb TONE -Lb OUTb OUTw Vref - 1 -

2 PIN CONFIGURATION 1 INa INb 32 2 SR-FIL LF SS-FIL LF TONE-Ha LF TONE-La TONE-Hb 28 6 OUTW TONE-Lb 27 7 OUTa OUTb 26 8 AGC1 AGC AUX0 CVA AUX1 CVB PORT0 CVW PORT1 CTH ADR CTL SDA CSR SCL Vref GND V+ 17 No. Symbol Function No. Symbol Function 1 INa Ach input terminal 17 V+ Supply voltage terminal 2 SR-FIL Surround filter terminal 18 Vref Reference voltage terminal 3 SS-FIL Simulated stereo filter terminal 19 CSR DAC output terminal for surround control 4 TONE-Ha Ach tone control (treble) filter terminal 20 CTL DAC output terminal for tone control (bass) 5 TONE-La Ach tone control (bass) filter terminal 21 CTH DAC output terminal for tone control (treble) 6 OUTw Subwoofer output terminal 22 CVW Bch DAC output terminal for LPF trimmer 7 OUTa Ach output terminal 23 CVB Bch DAC output terminal for volume and balance 8 AGC1 AGC attack and recovery time setting terminal 24 CVA Ach DAC output terminal for volume and balance ( ) Auxiliary 3 values voltage output terminal 9 AUX0 (0.0V, 2.5V, 5V) Auxiliary 2 values voltage output terminal 10 AUX1 (0.0V, V+) 25 AGC2 AGC boost level setting terminal 26 OUTb Bch output terminal 11 PORT0 Logic input terminal 27 TONE-Lb Bch tone control (bass) filter terminal 12 PORT1 Logic input terminal 28 TONE-Hb Bch tone control (treble) filter terminal 13 ADR Slave address setting terminal 29 LF1 LPF filter1 terminal 14 SDA I 2 C data terminal 30 LF3 LPF filter3 terminal 15 SCL I 2 C cock terminal 31 LF2 LPF filter2 terminal 16 GND Ground terminal 32 INb Bch input terminal ( ) The AUX0 terminal should be connected via the protection resistance to 5V device

3 ABSOLUTE MAXIMUM RATING (Ta=25 C) PARAMETER SYMBOL RATING UNIT Supply Voltage V + 15 V Power Dissipation P D SSOP32 ; 800 NOTE: EIA/JEDEC STANDARD Test board (76.2x114.3x1.6mm, 2layer, FR-4) mounting Operating Temperature Range Topr -20 to +75 C Storage Temperature Range Tstg -40 to +125 C ELECTRICAL CHARACTERISTICS ( Ta=25 C, V+=9V, Rg=600, R L=47k, Vin=100mVrms/1kHz unless otherwise specified) Condition PARAMETER SYMBOL Input Output INa INb mw MIN. TYP. MAX. UNIT Operating Voltage V V Supply Current I CC No Signal ma Reference Voltage V REF No Signal V Maximum Input Voltage V IM VOL=-20dB,THD=1% Maximum Output Voltage Vrms V OM VOL=0dB, THD=1% Vrms Channel Balance G CB VOL=0dB db Balance Boost A BA BST CHS= 0,BAL= V in V in OUTa db Balance Cut A BA CUT CHS= 1, BAL= Vin = 1Vrms V in V in OUTa db Balance Boost B BB BST CHS= 1,BAL= V in V in OUTb db Balance Cut B BB CUT CHS= 0, BAL= Vin = 1Vrms V in V in OUTb db Trimmer Boost TR BST VOL=0dB TRIM = +18dB V in V in OUTw db Trimmer Cut TR CUT VOL=0dB TRIM = -44dB V in V in OUTw db Total Harmonic Distortion THD Maximum Gain G VMAX VOL=0dB Minimum Gain Channel Separation Output Noise 1 Output Noise 2 Output Noise 3 G VMIN CS V NO1 V NO2 V NO3 Vo=0.5Vrms, BW=400Hz to 30kHz VOL=MUTE Vin=1Vrms Vin=1Vrms BW=400Hz to 30kHz VOL=0dB BW=400Hz to 30kHz VOL=MUTE BW=400Hz to 30kHz VOL=MUTE,TRIM=MUTE BW=400Hz to 30kHz V in - OUTb - V in OUTa % db db db -90 (31.6) -106 (5.0) -100 (10.0) -85 (56.2) -96 (15.8) -90 (30.0) dbv ( Vrms) dbv ( Vrms) dbv ( Vrms) BW : Band Width - 3 -

4 ELECTRICAL CHARACTERISTICS (Ta=25 C, V+=9V, Rg=600, R L=47k, Vin=100mVrms/1kHz unless otherwise specified) Condition PARAMETER SYMBOL Input Output INa INb TONE High Frequency Boost HF BST BCT= 1 TREB=+15dB, f=10khz High Frequency Flat HF FLT TREB=0, f=10khz High Frequency Cut Low Frequency Boost HF CUT LF BST BCT= 0 TREB=-15dB, f=10khz BCB= 1 BASS=+15dB, f=100hz Low Frequency Flat LF FLT BASS=0, f=100hz Low Frequency Cut AGC AGC Boost AGC Flat1 AGC Flat2 AGC Flat3 AGC Flat4 AGC Cut SURROUND Surround Gain1 Surround Gain2 Surround Gain3 LF CUT AGC BST AGC FLT1 AGC FLT2 AGC FLT3 AGC FLT4 AGC CUT SR GAIN1 SR GAIN2 SR GAIN3 BCB= 0 BASS=-15dB, f=100hz Vin=50mVrms, f=1khz AGC= 1 Vin=100mVrms,f=1kHz AGC= 1, AGCL= 00 Vin=200mVrms, f=1khz AGC= 1, AGCL= 01 Vin=300mVrms, f=1khz AGC= 1, AGCL= 10 Vin=400mVrms, f=1khz AGC= 1, AGCL= 11 Vin=2Vrms, f=1khz AGC= 1 f=100hz Surround Effect1 f=100hz Surround Effect1 f=100 Hz Surround Effect2 f=100hz Surround Effect2 V in OUTa V in V in OUTb V in V in OUTa V in V in OUTb V in V in OUTa V in V in OUTb V in V in OUTa V in V in OUTb V in V in OUTa V in V in OUTb V in V in OUTa V in V in OUTb V in - OUTb - V in OUTa V in - OUTb MIN. TYP. MAX. UNIT db db db db db db db db db db db db db db db Surround Gain4 SR GAIN 4 - V in OUTa db Simulated Stereo1 SR SIM1 f=1khz, Simulated Stereo V in V in OUTa db Simulated Stereo2 SR SIM2 f=1khz, Simulated Stereo V in V in OUTb db PORT, AUX PORT0,1 Input Voltage AUX0 Output Voltage AUX1 Output Voltage ADR Input Voltage V PTIN V AUX0 V AUX1 V ADR Input : High Input : Low Logic Output : High Logic Output : Mid Logic Output : Low Logic Output : High V Logic Output : Low Input : High Input : Low V V V V - 4 -

5 TIMING ON THE I 2 C BUS (SDA,SCL) SDA t f t r t f t HD:STA t SP t r t BUF t SU:DAT SCL t HD:STA t SU:STA t SU:STO S t LOW t HD:DAT t HIGH Sr P S CHARACTERISTICS OF I/O STAGES FOR I 2 C BUS (SDA,SCL) I 2 C BUS Load Conditions STANDARD MODE: Pull up resistance 4k (Connected to +5V), Load capacitance 200pF (Connected to GND) PARAMETER SYMBOL Standard mode MIN. TYP. MAX. Low Level Input Voltage V IL V High Level Input Voltage V IH V Low level output voltage (3mA at SDA pin) V OL V Input current each I/O pin with an input voltage between 0.1V DD and 0.9V DDmax UNIT I i µa - 5 -

6 CHARACTERISTICS OF BUS LINES (SDA,SCL) FOR I 2 C-BUS DEVICES PARAMETER SYMBOL Standard mode MIN. TYP. MAX. UNIT SCL clock frequency f SCL khz Hold time (repeated) START condition. t HD:STA µs Low period of the SCL clock t LOW µs High period of the SCL clock t HIGH µs Set-up time for a repeated START condition t SU:STA µs Data hold time NOTE) t HD:DAT µs Data set-up time t SU:DAT ns Rise time of both SDA and SCL signals t r ns Fall time of both SDA and SCL signals t f ns Set-up time for STOP condition t SU:STO µs Bus free time between a STOP and START condition t BUF µs Capacitive load for each bus line C b pf Noise margin at the Low level V nl V Noise margin at the High level V nh V C b ; total capacitance of one bus line in pf. NOTE). Data hold time : t HD:DAT Please hold the Data Hold Time (t HD:DAT) to 300ns or more to avoid status of unstable at SCL falling edge. The SDA block in the NJW1163 does not hold data. Add external data-delay-circuit of the SDA terminal, in case of not providing a hold time of at least 300nsec for the SDA in the master device. The time-consists of the data-delay-circuit of the SDA terminal are as follows. (a) Low level High level: (b) High level Low level: T LH R P*C D T HL R D*C D In addition, Schottky barrier diode (SBD) influences a Low level at the Acknowledge. Therefore choose the low forward voltage (Vf) as much as possible. V DD R P R P SCL MASTER SBD SDA NJW1163 R D C D - 6 -

7 TERMINAL DESCRIPTION No. SYMBOL FUNCTION EQUIVALENT CIRCUIT VOLTAGE V INa INb Ach input terminal Bch input terminal 1,32 pin 20k 80k V+/2 Vref OUTw OUTa OUTb Subwoofer output terminal Ach output terminal Bch output terminal FB 100 6, 7, 26pin V+/2 1.8k 2pin 2 SRFIL Surround filter terminal FB V+/2 3pin 5.3k 3 SSFIL Simulated stereo filter terminal FB V+/ TONE-Ha TONE-Hb Treble(tone control) filter terminal FB 18k 4, 28pin V+/2-7 -

8 TERMINAL DESCRIPTION No. SYMBOL FUNCTION EQUIVALENT CIRCUIT VOLTAGE 5 27 TONE-La TONE-Lb Bass(tone control) filter terminal FB 12k 12k 5, 27pin V+/2 8 AGC1 Capacitor connection terminal for AGC attack and recovery time setting 12k pin AGC; OFF=0.65V ON=1.4V 1k 9 AUX0 Auxiliary 3 values voltage output terminal FB 9pin Low=0V Mid=2.5V High= 5.0V 10 AUX1 Auxiliary 2 values voltage output terminal (Open collector type output) 10pin Low=0V High=3.5V to V+ 12k 5V PORT0 PORT1 ADR Logic input terminal Logic input terminal Slave address setting terminal (Don t apply over 5V to these terminals) 11, 12, 13pin

9 TERMINAL DESCRIPTION No. SYMBOL FUNCTION EQUIVALENT CIRCUIT VOLTAGE D1 D2 14 SDA I 2 C data terminal - 14pin 4k D13 D14 8k D1 D2 15 SCL I 2 C clock terminal - 15pin 4k D13 D14 8k GND V+ Ground terminal Supply voltage terminal - V+/2 18pin 200k 18 Vref Reference voltage terminal V+/2 200k 19pin 19 CSR DAC output for surround control terminal 0V 32k - 9 -

10 TERMINAL DESCRIPTION No. SYMBOL FUNCTION EQUIVALENT CIRCUIT VOLTAGE CTL CTH DAC output for tone control terminal 20, 21pin 36k V+/ CVW CVB CVA DAC output terminal for trimmer control DAC output terminal for Bch volume control DAC output terminal for Ach volume control 22, 23, 24pin 8k V+/2 25 AGC2 Resistance connection terminal for AGC boost level setting 25pin 0V LF3 LF2 LPF filter terminal 4k 30,31pin V+/2+0.7V 29 LF1 LPF filter terminal V+/2 29pin 24k

11 MEASUREMENT CIRCUIT Input Ach 0.47µ 1 INa INb µ Input Bch Vin Output Wch Output Ach 47k 47k AUX0 AUX1 ( 1) PORT0 PORT1 ADR SDA V PTIN0 V PTIN1 V ADRIN ( 2) 100n 100n 2.2n 100n 330nF SR-FIL SS-FIL TONE-Ha TONE-La OUTw OUTa AGC1 AUX0 AUX1 PORT0 PORT1 ADR SDA SCL LF2 LF3 LF1 TONE-Hb TONE-Lb OUTb AGC2 CVA CVB CVW CTH CTL CSR Vref µ 0.022µ 0.033µ 2.2n 100n 100k Vin Output Bch 47k Vref SCL ( 3) 16 GND V µ V+ Icc V+ ( 1) ( 2) ( 3) V AUX0 Output High Output Low V AUX1 Output Low V OL Output Low I AUX0 +2mA -120 A I AUX1-3mA I OL -3mA

12 APPLICATION CIRCUIT 0.47µ 1 INa INb µ 100n 2 SR-FIL LF µ 100n 3 SS-FIL LF µ 2.2n 4 TONE-Ha LF µ 100n 5 TONE-La TONE-Hb 28 6 OUTw TONE-Lb 27 7 OUTa OUTb n 100n 5V 330nF 8 AGC1 AGC k 4.7k 9 AUX0 CVA AUX1 PORT0 PORT1 CVB CVW CTH ( 4) ADR SDA SCL CTL CSR Vref GND V µ ( 4) Set the Slave Address by ADR terminal. ADR I 2 C Slave Address (Pin 13) Read mode Write mode GND 80h 81h +5V 82h 83h ( 5) Separate the I 2 C bus line and Signal line from the following terminals for avoiding digital noise problem and cross talk. Pin No. Symbol Pin No. Symbol Pin No. Symbol 2 SR-FIL 27 TONE-Lb 31 LF2 3 SS-FL 28 TONE-Hb 4 TONE-Ha 29 LF1 5 TONE-La 30 LF3-12 -

13 Gain[dB] Gain[dB] G a NJW1163 LPF Characteristics Secondary LPF Primary LPF GmAmp2 Buffer2 GmAmp3 Buffer3 R1 24k LF2 C2 LF3 C3 LF1 C1 LPF Block Diagram The NJW1163 includes the LPF for subwoofer output and bass boost function. The LPF consists of primary and secondary LPF and it is enable to adjust cut off frequency, Q and Roll off. The expression of LPF characteristics is as follows. <Primary LPF> f c * R* C1 2 *24*10 * C1 Q 0. <Secondary LPF> f c C3 Q2 1.46* 2 C2 C3 C2 <LPF Frequency Response> C2 = 47nF, C3 = 22nF C1=15nF C1=22nF C1=33nF C1=47nF C1=68nF C2=47nF C2=68nF C2=100nF C1 = 33nF, C C2=33nF C C1 = 33nF, C2 = 47nF C3=47nF C3=33nF C3=22nF C3=15nF C3=10nF Frequency [khz] Fr quency [khz] Frequency [khz]

14 DEFINITION OF I 2 C REGISTER I 2 C BUS FORMAT MSB LSB MSB LSB MSB LSB S Slave Address A Select Address A Data A P 1bit 8bit 1bit 8bit 1bit 8bit 1bit 1bit S: Starting Term A: Acknowledge Bit P: Ending Term SLAVE ADDRESS R/W : Set the Write Mode or Read Mode. ADR : Set the Slave Address by ADR terminal. (See Application Circuit) Slave Address MSB LSB ADR R/W - R/W = 0 : Write Mode, ADR = 0/1 - Hex (h) (h) R/W = 1 : Read Mode, ADR = 0/ (h) (h) CONTROL REGISTER TABLE The select address sets each function (Volume, Balance, Bass Boost Select, AGC, Surround, Tone Control, AUX). The auto increment function cycles the select address as follows. 00H 01H 02H 03H 04H 05H 00H <Write Mode> Select Address BIT D7 D6 D5 D4 D3 D2 D1 D0 00H VOL 01H CHS BAL BBSW 02H TRIM 03H BCB BASS 04H BCT TREB 05H SUR AUX1 AUX0 AGCL AGC : Don t Care <Read Mode> BIT D7 D6 D5 D4 D3 D2 D1 D PORT1 PORT0 PORT1, PORT0 terminal setting D1/D0 Remarks 0 D1/D0 output 0 at PORT1/PORT0 terminal receive High signal 1 (more than 3.5V) 1 D1/D0 output 1 at PORT1/PORT0 terminal receive Low signal 0 (less than 1.0V) CONTROL REGISTER DEFAULT VALUE Control register default value is all 0. Select BIT Address D7 D6 D5 D4 D3 D2 D1 D0 00H H H H H H

15 INSTRUCTION CODE a) MASTER VOLUME SETTING Select Address 00H BIT D7 D6 D5 D4 D3 D2 D1 D0 VOL VOL Attenuation level : 0 to 80dB(0.33dB/step), MUTE The attenuator is consisted of both the VOL1(0.165dB/step)and VOL2(0.165dB/step) and is enable to adjust 0.33dB/step. The attenuation for both the VOL1and VOL2 are always synchronized to have the same attenuation levels for each other, and are not controllable independently for each other. ex) VOL(-30dB) = VOL1(-15dB) + VOL2(-15dB) b) BALANCE AND BASS BOOST FUNCTION SETTING Select Address BIT D7 D6 D5 D4 D3 D2 D1 D0 01H CHS BAL BBSW CHS : Channel select for balance control 0 : Ach Bch is attenuated 1 : Bch Ach is attenuated BAL : Balance control for both Ach and Bch Balance Level : 0 to 60dB (1dB/Step), MUTE BBSW : Bass Boost ON/OFF Switch 0 = Bass Boost OFF 1 = Bass Boost ON c) TRIMMER LEVEL SETTING Select Address BIT D7 D6 D5 D4 D3 D2 D1 D0 02H TRIM Don t Care TRIM : Trimmer Level Trimmer Level : +18 to 44dB (0.5dB/Step), MUTE d) TONE CONTROL BASS SETTING Select Address BIT D7 D6 D5 D4 D3 D2 D1 D0 03H BCB BASS Don t Care BCB : Boost cut select for Bass control 0 : Cut 1 : Boost BASS : BASS Level Setting Cut Level : -15 to 0dB(0.5dB/Step) Boost Level : 0 to +15dB(0.5dB/Step) d) TONE CONTROL TREBLE SETTING Select Address BIT D7 D6 D5 D4 D3 D2 D1 D0 04H BCT TREB Don t Care BCT : Boost cut select for Treble control 0 : Cut 1 : Boost TREB : TREBLE Level Setting Cut Level : -15 to 0dB(0.5dB/Step) Boost Level : 0 to +15dB(0.5dB/Step)

16 d) SURROUND, AUXILIARY, AGC LEVEL SETTING Select Address BIT D7 D6 D5 D4 D3 D2 D1 D0 05H SUR AUX1 AUX0 AGCL AGC <SUR : Surround Level Setting> Surround Setting D7 D6 Remarks Surround Off 0 0 Surround Off Simulated Stereo 0 1 Simulated Stereo Surround Effect1 1 0 Surround Effect Low(8.3dB typ.) Surround Effect2 1 1 Surround Effect High(12.7dB typ.) <AUX1 : AUX1 Terminal Setting> Auxiliary Setting D5 Low (0.0V) 0 High (5.0V) 1 <AUX0 : AUX0 Terminal Setting> Auxiliary Setting D4 D3 Low (0.0V) - 0 Mid (2.5V) 0 1 High (5.0V) 1 1 <AGCL : AGC Level Setting> AGC Level Setting D2 D1 100mVrms mVrms mVrms mVrms 1 1 <AGC : AGC Setting> AGC Setting D0 OFF 0 ON

17 Master Volume (Select Address : 00H) Gain(dB) HEX D7 D6 D5 D4 D3 D2 D1 D0 0 FF FC F F F F ED EA E E E DE DB D D D CF CC C C C C BD BA B B B AE AB A A A F C D A VOL

18 Gain(dB) HEX D7 D6 D5 D4 D3 D2 D1 D0-43 7E B F C D A E B F C D A E B F MUTE VOL : Default Value

19 Balance, Bass Boost Setting (Select Address : 01H) Channel Setting (CHS) D7 Decrease Bch Gain 0 Decrease Ach Gain 1 Gain(dB) BAL D6 D5 D4 D3 D2 D : Default Value

20 Gain(dB) BAL D6 D5 D4 D3 D2 D MUTE Bass Boost Setting (BBSW) D0 Bass Boost Off 0 Bass Boost On 1 : Default Value

21 Trimmer Setting (Select Address: 02H) TRIM Gain(dB) D7 D6 D5 D4 D3 D2 D

22 TRIM Gain(dB) D7 D6 D5 D4 D3 D2 D

23 TRIM Gain(dB) D7 D6 D5 D4 D3 D2 D MUTE : Default value

24 Tone Control(Bass Setting) (Select Address : 03H) Bass Cut or Boost BCB D7 Cut 0 Boost 1 BASS Cut Gain(dB) Boost Gain(dB) D6 D5 D4 D3 D : Default value

25 Tone Control(Treble Setting) (Select Address : 04H) Treble Cut or Boost BCT D7 Cut 0 Boost 1 TREB Cut Gain(dB) Boost Gain(dB) D6 D5 D4 D3 D : Default value [CAUTION] The specifications on this databook are only given for information, without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights