Case Outline(s). The case outlines shall be designated in Mil-Std-1835 and as follows:

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1 SCOPE: CMOS, BUFFERED, MULTIPLYING 8-BIT D/A CONVERTER Device Type Generic Number Circuit Function 0 MX7528S(x)/883B DAC with ±4 LSB 02 MX7528T(x)/883B DAC with ±2 LSB 03 MX7528U(x)/883B DAC with ± LSB Case Outline(s). The case outlines shall be designated in Mil-Std-835 and as follows: Outline Letter Mil-Std-835 Case Outline Package Code Q GDIP-T20 or CDIP2-T20 20 LEAD CERDIP J20 Absolute Maximum Ratings: V DD to AGND V, + 7V V DD to DGND.... 0V, + 7V V RFBA, V RFBB to DGND.... ±25V V REFA, V REFB to AGND.... ±25V Digital Input Voltage to DGND V to V DD +0.3V V pin to DGND V to V DD V pin 2, V pin 20 to AGND V to V DD +0.3V AGND to DGND V, V DD +0.3V DGND to AGND V Lead Temperature (soldering, seconds) C Storage Temperature C to +50 C Continuous Power Dissipation T A =+70 C 20 pin CERDIP(derate.mW/ C above +70 C) mW Junction Temperature T J C Thermal Resistance, Junction to Case, ΘJC 20 pin CERDIP C/W Thermal Resistance, Junction to Ambient, ΘJA: 6 pin CERDIP C/W Recommended Operating Conditio Ambient Operating Range (T A ) C to +25 C Supply Voltage Range (V DD ) V to +5.25V and +4.25V to +5.75V V REF DAC A=V REF DAC B.... +V OUT DAC A=OUT DAC B... 0V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of the specificatio is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. Page 2 of 7

2 TABLE. ELECTRICAL TESTS: TEST Symbol CONDITIONS -55 C <=T A <= +25 C / Unless otherwise specified Group A Subgroup Device type Min Max Units ACCURACY Resolution NOTE 4 RES and, All 8.0 Bits, All 2.0 Relative Accuracy RA and, 0 ±.0 LSB Relative Accuracy RA and, 02,03 ±0.5 LSB Differential Nonlinearity DNL and Monotonic to 8-Bits, All - LSB Gain Error NOTE 2 AE and 0 ±4.0 LSB DAC register loaded with 02 ± ±.0 Gain Error NOTE 2 AE 0 ±6.0 LSB ±5.0 Gain Error NOTE 2 AE 02 ±4.0 LSB ±3.0 Gain Error NOTE 2 AE 03 ±3.0 ±.0 LSB Power Supply Rejection PSRR, V DD =±5% All ±0.02 %/% ±0.04 Power Supply Rejection PSRR, V DD =±5% All ±0.0 %/% ±0.02 Output Leakage Current I OL, DAC latches loaded All ±50 na OUTA, OUTB with ±400 Output Leakage Current I OL, DAC latches loaded All ±50 na OUTA, OUTB with ±200 Reference Input R IN and +5V 4,5,6 All 8 5 kω Resistance VREFA, VREFB Digital Input High V IH, All 2.4 V Voltage 3.5 Digital Input Low V IL, All 0.8 V Voltage.5 Digital Input Leakage I IN All ±.0 µa Current V IN =0V or V DD ± Digital Input Leakage Current I IN V IN =0V or V DD All ±.0 ± µa Supply Current I DD All digital inputs ma V IL or V IH 2.0 Supply Current I DD & +5V. All digital All 0 inputs 0V or V DD 500 µa Gain Temperature Coefficient NOTE 3 TC AE, All ±70 ±35 Feedthrough Error V REF A to OUTA and V REF B to OUTB FT REF A or, V REF =+V, 0kHz sinewave, DAC latches loaded with NOTE 3, NOTE 5 4,5,6 All -55 db ppm/ C Page 3 of 7

3 TEST Symbol CONDITIONS -55 C <=T A <= +25 C / Unless otherwise specified Group A Subgroup Device type Min Max Units Digital Input Capacitance NOTE 3, 6 Digital Input Capacitance NOTE 3, 6 ANALOG INPUTS Digital Output pin 2 Capacitance 3/ pin 20 Digital Output pin 2 Capacitance 3/ pin 20 TIMING Chip select to write Chip select to write Write pulse width Data valid to write Data valid to write Data select to write NOTE 3,7 Data select to write NOTE 7 Reference input resistance match Channel to Channel isolation NOTE 3 V REF A to OUTB Channel to Channel isolation NOTE 3 V REF B to OUTA Output Current Settling Time NOTE 3, NOTE 8 C IN C IN C OUTA C OUTB C OUTA C OUTB t CS t CH t WR t DS t DH t AS t AH RMIN V REF CHISO CHISO t SL and, DB0-DB7 & WR, CS, DACA/DACB and 5V, DAC latches loaded with and 5V, DAC latches loaded with, t CS t WR, t CH 0, t CS t WR, t CH 0 or +5V. V REF A=±V, 0kHz sinewave, V REF B=0V or +5V. V REF B=±V, 0kHz sinewave, DAC, V REF A=0V 4 All pf 4 All 5 pf 4 All 4 All pf pf ± 4,5,6 All % ± 4,5,6 All -60 db 4,5,6 All -60 db NOTE : V OUT =0V; VREF=+V, AGND=DGND unless otherwise specified. NOTE 2: Measured using internal RFBA and RFBB. Gain error is adjustable. NOTE 3: Characteristics supplied for use as a typical design limit, but not production tested Page 4 of 7

4 NOTE 4: Guaranteed, if not tested. NOTE 5: Feedthrough error can be reduced by connecting the metal lid to ground. NOTE 6: Subgroup 4 (C IN and C OUT measurements) shall be measured only for the inital test and after process or design changes which may affect capacitance. NOTE 7: Timing in accordance with Write Cycle Timing Diagram in Commercial Data Sheet. NOTE 8: To 0.5LSB, OUTA/OUTB=0Ω in parallel with 3pF. DB0-DB7=0V to V DD or V DD to 0V, WR=CS=0V MODE SELECTION TABLE: CS WR DACA/DACB DACA DACB L L L Write Hold L L H Hold Write H X X Hold Hold X H X Hold Hold L = Low state, H = High state, X = Don t care ORDERING INFORMATION: Package Pkg. Code 0 20 pin CERDIP J20 MX7528SQ/883B pin CERDIP J20 MX7528TQ/883B pin CERDIP J20 MX7528UQ/883B TERMINAL CONNECTIONS: J20 Pin AGND 2 OUTA 3 RFBA 4 VREFA 5 DGND 6 DACA/DACB 7 (MSB)DB7 8 DB6 9 DB5 DB4 DB3 2 DB2 3 DB 4 DB0(LSB) 5 CS 6 WR 7 V DD 8 VREFB 9 RFBB 20 OUTB Page 5 of 7

5 QUALITY ASSURANCE Sampling and ipection procedures shall be in accordance with MIL-Prf-38535, Appendix A as specified in Mil- Std-883. Screening shall be in accordance with Method 5004 of Mil-Std-883. Burn-in test Method 5:. Test Condition, A, B, C, or D. 2. TA = +25 C minimum. 3. Interim and final electrical test requirements shall be specified in Table 2. Quality conformance ipection shall be in accordance with of Mil-Std-883, including Groups A, B, C, and D ipection. Group A ipection:. Tests as specified in Table Selected subgroups in Table, of Mil-Std-883 shall be omitted. Group C and D ipectio: a. End-point electrical parameters shall be specified in Table. b. Steady-state life test, Method 05 of Mil-Std-883:. Test condition A, B, C, D. 2. TA = +25 C, minimum. 3. Test duration, 00 hours, except as permitted by Method 05 of Mil-Std-883. TABLE 2. ELECTRICAL TEST REQUIREMENTS Mil-Std-883 Test Requirements Interim Electric Parameters Method 5004 Final Electrical Parameters Group A Test Requirements Group C and D End-Point Electrical Parameters Subgroups per, Table *, 2, 3, 2, 3, 4, 5, 6, 9**, **, ** * PDA applies to Subgroup only. ** Subgroups 9, and, if not tested shall be guaranteed to the limits specified in Table. Page 6 of 7

Case Outline(s). The case outlines shall be designated in Mil-Std-1835 and as follows:

Case Outline(s). The case outlines shall be designated in Mil-Std-1835 and as follows: SCOPE: CMOS, BUFFERED, MULTIPLYING 8-BIT D/A CONVERTER Type Generic Number Circuit Function 0 MX7528S(x)/883B DAC with ±4 LSB 02 MX7528T(x)/883B DAC with ±2 LSB 03 MX7528U(x)/883B DAC with ± LSB Case Outline(s).