NJW CHANNEL ELECTRONIC VOLUME

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Lora Warner
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1 2-CHANNEL ELECTRONIC VOLUME GENERAL DESCRIPTION NJW9 is a two channel electronic volume IC. It is included output buffer amplifier and also resistor output terminal for using external amplifier to customize for your application. These functions are controlled by three-wired serial data. And the chip selector is available for using four chips on same serial bus line. It s available for two-channel stereo and or multi-channel audio volume. PACKAGE OUTLINE NJW9V NJW9M NJW9D FEATURES Operating Voltage Three-Wired Serial Data Control Chip Selector Volume Bi-CMOS Technology Package Outline ±. to ±7.V available for using four chips on same serial bus line. 0 to -9dB/dBstep, MUTE SSOP6, DMP6, DIP6 BLOCK DIAGRAM B OUT L IN L OUT L VOL B OUT R IN R OUT R CE0 CE VOL 2 Inter-face & Logic Bias V GND 3 Wired Control Data V-

2 PIN ASSIGNMENT 6 ABSOLUTE MAXIMUM RATING (Ta=2 C) PARAMETER SYMBOL RATING UNIT Power Supply Voltage V /V - 8/-8 V Maximum Input Voltage V IM V /V - ( ) Power Dissipation P D SSOP6 ; 300 DMP6 ; 300 DIP6 ; 00 Operating Temperature Range Topr -0 to 8 C Storage Temperature Range Tstg -0 to 2 C ELECTRICAL CHARACTERISTICS (Ta=2 C,V/V- = 7V/-7V, R L=7kΩ) V mw ( ) For the maximum input voltage less than V /V - PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT Power Supply 8 9 No. Symbol Function OUTL Lch External Opamp Input Connection Terminal 2 BOUTL Lch Output 3 VDD_OUT Internal VDD Noise Rejection Capacitor Terminal BOUTR Rch Output OUTR Rch External Opamp Input Connection Terminal 6 VSS_OUT Internal VSS Noise Rejection Capacitor Terminal 7 V Power supply voltage input 8 V- - Power supply voltage input 9 INL Lch Input 0 INR Rch Input CE0 Chip Enable Terminal 0 2 CE Chip Enable Terminal 3 DATA Control data signal input CLOCK Clock signal input LACTH Latch signal input 6 GND Ground Operating Voltage V V Operating Voltage 2 V V Supply Current I CC No signal ma Supply Current 2 I EE No signal ma Input/Output Characteristics (BOUTL : 2pin, BOUTR : pin) Maximum Output Voltage Voltage Gain Channel Gain Balance Channel Gain Balance 2 Maximum Attenuation Mute Level Output Noise Voltage Total Harmonic Distortion Channel Separation V OM G V G V G V2 A TT Mute V NO THD CS f=khz,thd=% Volume=0dB V IN=Vrms, f=khz Volume=0dB V IN=Vrms, f=khz Volume=0dB V IN=Vrms, f=khz Volume=-60dB V IN=Vrms, f=khz Volume=-9dB, A-weight V IN=Vrms, f=khz Volume=Mute, A-weight Volume=0dB, Rg=0Ω, A-weight Vo=Vrms, f=khz, Volume=0dB, BW=00-30kHz Vo=Vrms, f=khz, A-weight Volume=0dB, Rg=0Ω Vrms db db db db db - -0 (.6µ) -9 (7.8µ) dbv (Vrms) % db 2

3 ELECTRICAL CHARACTERISTICS (Ta=2 C,V/V- = 7V/-7V) PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT Logic Control Characteristics High Level Input Voltage V IH DATA, CLOCK, LATCH, CE0, CE Terminal Input V Low Level Input Voltage V IL DATA, CLOCK, LATCH, CE0, CE Terminal Input 0 -. V CONTROL DATA FORMAT t7 t t t8 LATCH t2 t3 CLOCK MSB LSB DATA D D D3 D2 D D0 D9 D8 D7 D6 D D D3 D2 D D0 ( ) MSB First t t6 SYMBOL PARAMETER MIN TYP MAX UNIT t CLOCK Clock Width µsec t2 CLOCK Pulse Width (High) µsec t3 CLOCK Pulse Width (Low) µsec t LATCH Rise Hold Time µsec t DATA Setup Time µsec t6 DATA Hold Time µsec t7 CLOCK Setup Time µsec t8 LATCH High Pulse Width µsec 3

4 ! TERMINAL DESCRIPTION PIN NO. SYMBOL FUNCTION EQUIVALENT CIRCUIT TERMINAL DC VOLTAGE V 3 6 VDD_OUT VSS_OUT Internal VDD Noise Rejection Capacitor Terminal Internal VSS Noise Rejection Capacitor Terminal 2.V (VDD_OUT) -2.V (VSS_OUT) OUTL OUTR Lch External Opamp Input Connection Terminal Rch External Opamp Input Connection Terminal 0K 300 V 0V 0V V V 00 2 BOUTL BOUTR Lch Output Rch Output 0V 0V 7 V Power Supply Voltage Input V

5 ! TERMINAL DESCRIPTION PIN NO. SYMBOL FUNCTION EQUIVALENT CIRCUIT TERMINAL DC VOLTAGE V 9 0 INL INR Lch Input Rch Input 300 0K 0V V 2 3 CE0 CE DATA CLOCK LATCH Chip Enable Terminal 0 Chip Enable Terminal Control data signal input Clock signal input Latch signal input 8K 0V V 6 GND Ground 0V

6 APPLICATION CIRCUIT. Internal Output Buffer Application GND 6 BOUTL µ F 2 LATCH 0 µ F 3 VDD_OUT CLOCK BOUTR µ F Interface & Logic 3 DATA 2 CE 0 µ F 6 VSS_OUT CE0 V=7V V-=-7V 00 µf 00 µf 7 8 Bias 0 9 µ F µ F INR INL ( ) DATA, CLOCK, LATCH are digital lines. Separate the DATA, CLOCK, LATCH lines and Analog signal terminals (especially, pin, pin, 9pin, 0pin) for avoiding digital noise problem and cross talk. 6

7 2. External Output Buffer Application (JFET Input type OP Amp.) Ex.) Gv=dB 7k Ω 0k Ω 2V OUTL J-FET Input Type NJM2082, NJM072/082, NJM33,., etc. OUTR µ F µ F -2V 7k Ω 2V -2V 0 µ F 0k Ω 0 µ F VDD_OUT VSS_OUT Interface & Logic GND LATCH CLOCK DATA CE CE0 V=7V V-=-7V 00 µ F 00 µ F 7 8 Bias 0 9 µ F µ F INR INL ( ) DATA, CLOCK, LATCH are digital lines. Separate the DATA, CLOCK, LATCH lines and Analog signal terminals (especially, pin, pin, 9pin, 0pin) for avoiding digital noise problem and cross talk. 7

8 ! CONTROL DATA NJW9 is controlled by 6-bits serial data. MSB LSB D D D3 D2 D D0 D9 D8 D7 D6 D D D3 D2 D D0 Data Select Address Chip Address OUT L BOUT L Chip Enable CE CE0 IN L Volume Interface & Logic Control Data IN R Volume 2 Bias Power Supply OUT R BOUT R MSB LSB D D D3 D2 D D0 D9 D8 D7 D6 D D D3 D2 D D0 Don t Volume Care * * * * Don t Volume 2 Care * * * * * Chip address is set by chip enable terminal (CE0, CE) status. Chip enable Terminal Chip Address CE CE0 D3 D2 D D ! INITIAL CONDITION MSB LSB D D D3 D2 D D0 D9 D8 D7 D6 D D D3 D2 D D * * * * * * * * 8

9 ! DEFINITION OF RESISTOR Volume, Volume 2 : 0 to -9dB(dB/step) D D D3 D2 D D0 D9 D8 D7 D6 D D D3 D2 D D0 Volume Volume 2 Don t Care * * * * Don t Care * * * * < Volume Control > Data D D D3 D2 D D0 D9 Setting dB db dB dB db db dB dB dB dB dB db dB dB db db dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB 0 0-3dB dB dB dB dB dB dB dB dB dB db dB dB db db dB 0 0-7dB dB dB dB 9

10 Data D D D3 D2 D D0 D9 Setting db dB dB db 0 0 -db dB dB dB 0 0-9dB dB 0 0-6dB dB 0-63dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB 0 0-9dB dB dB 0 0-9dB 0-9dB MUTE ( ) ( ) Initial Setting 0

11 ! TYPICAL CHARACTERISTICS Operating Current vs. Power Supply voltage Operating Current vs. Ambient temparature V/V-=±7V,ICC. Operating Current [ma] C Operating Current [ma]. 2 C -0 C Pow er Supply Voltage [V] Ambient temparature [ o C] Maximum Output Voltage vs. Frequency V/V-=±7V,THD=% Maximum Output Voltage vs. Ambient temparature V/V-=±7V,THD=% Maximum Output Voltage [Vrms] C 8 C -0 C Maximum Output Voltage [Vrms] Frequency [Hz] Ambient temparature [ o C] 20 0 Voltage Gain vs. Ambient temparature V/V-=±7V,Vin=0dBV,f=kHz,RL=0kΩ 0dB 0-0 Voltage Gain vs. Gain set level V/V-=±7V,Vin=0dBV,f=kHz,RL=0kΩ Voltage Gain [db] dB -9dB Voltage Gain [db] C,2 C,8 C -00 Mute Ambient temparature [ o C] Gain set level [db]

12 ! TYPICAL CHARACTERISTICS Output Noise Voltage vs. Ambient temparaure V/V-=±7V,Rg=0Ω, A-Weighted THDN vs. Input Level V/V-=±7V,RL=0kΩ,BW: 0Hz-80kHz Outpu Noise Voltage [db] THDN [%] kHz Hz khz Ambient temparature [ o C] Input Level [Vrms] 0 THDN vs. Input Level V/V-=±7V,f=kHz,RL=0kΩ,BW: 00Hz-30kHz 0 THDN vs. Input Level V/V-=±7V,f=kHz,RL=0kΩ,BW: 00Hz-30kHz -20dB -30dB THDN [%] THDN [%] C -0dB dB C -0 C Input Level [Vrms] Input Level [Vrms] 0 THDN vs. Ambient temparature V/V-=±7V,f=kHz,RL=0kΩ,BW: 00Hz-30kHz 0 THDN vs. Frequency V/V-=±7V,f=kHz,RL=0kΩ,BW: 00Hz-30kHz THDN [%] THDN [%] C 8 C C Ambient temparature [ o C] Frequency [Hz] 2

13 [CAUTION] The specifications on this databook are only given for information, without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. 3

4-Channel Electronic Volume with Input Selector. Available for using four chips on same serial bus line

4-Channel Electronic Volume with Input Selector GENERAL DESCRIPTION The NJW1195A is a 4-channel electronic volume with 4-in 2-out stereo audio selector. It performs low noise and low distortion characteristics