D/A Converters and Iterated Function Systems

Transcription

1 D/A Converters and Iterated Function ystems Toshimichi aito Junya himakawa and Hiroyuki Torikai Department of Electronics, Electrical and Computer Engineering, HOEI University, Koganei-shi, Tokyo , Japan Abstract. This paper discusses A/D and D/A converters as applications of iterated function systems. We describe operation of basic converters in terms of iterate function systems and introduce typical examples for binary and Gray encodings/decodings. We then comment that converters in the field of analog signal processing have different character from iterated function systems in the field of nonlinear dynamical systems. imple implementation circuits for the basic D/A converters are also shown. Keywords: Analog-to-digital converters, Digital-to-analog converters, Iterated function systems, Chaos game representation, witched capacitors Abbreviations: ADC Analog-to-digital converter; DAC Digital-to-analog converter; IF Iterated function systems; CGR Chaos game representation; DNA deoxyribonucleic acid. Table of Contents Introduction 2 2 ADCs and expanding IFs 2 3 DACs and contractive IFs 4 4 Test Circuits 7 5 Conclusions 8 References 8 c 26 Kluwer Academic Publishers. Printed in the Netherlands. saito.tex; 4//26; 4:56; p.

2 2 aito, himakawa and Torikai. Introduction Cyclic A/D converters ( ab. ADCs) and D/A converters ( ab. DACs ) are essential parts in order to communicate between real analog world and digital signal processing systems. There exist a variety of ADC architectures including binary-encoder, Gray-encoder and their analogues []-[3]. The architectures of DACs are usually based on inverse operation of the ADCs [4], [5]. On the other hand, iterated function systems ( ab. IFs [6] ) have been studied as interesting dynamical systems with rich phenomena. Roughly speaking IFs are dynamical systems consisting of plural maps and switching rules among them. The IFs include various interesting examples such as ierpinski triangle generators and have various applications including DNA sequence analysis, image information compression and encryption [6]-[8]. Also, cyclic ADCs and DACs can be regarded as a class of IFs and analysis of their nonlinear dynamics can contribute to design of efficient ADCs and DACs. However, there exits a problem: citation of ADCs and DACs is not sufficient in the field of nonlinear dynamics and citation of IFs is not sufficient in the field of analog signal processing. For example, Refs. []-[5] discuss cyclic ADCs and DACs but they do not cite IFs. This paper discusses cyclic ADCs and DACs as applications of IFs. First, we describe operation of cyclic ADCs in terms of IFs consisting of expanding maps [9]. Noting two basic ADCs for binary and Gray encodings []-[2], we compare cyclic ADCs with the expanding IFs. econd, we describe operation of the cyclic DACs in terms of IFs consisting of contractive maps and show basic DACs for binary and Gray decodings []-[2]. We also introduce an interesting application of the IFs: the chaos game representation ( ab. CGR [7]) for analysis of DNA structures. Noting this example we compare the cyclic DACs with IFs. Third, simple implementation circuits of the basic DACs are shown. The circuit is based on intermittently coupled switched capacitors [5], [], []. This paper provides basic information to develop efficient converters and to introduce new researchers to the field of nonlinear dynamics. 2. ADCs and expanding IFs Here we introduce basic cyclic ADCs in terms of IFs []. Let us consider ADCs which convert a constant analog input X I [, ] to a digital output sequence y {y(),,y(l)}, y i {, }, where l is a saito.tex; 4//26; 4:56; p.2

3 DAC and IF 3 finite code length. The operation is described by Equation (). { f (x(n)) for x(n) I x(n +)=f(x(n)) = f (x(n)) for x(n) I { for x(n) I y(n) =Q(x(n)) = for x(n) I x() = X, n l< () where f is an IF consisting of expanding affine mappings f and f : f : I I, f : I I, I I I, I I =. d dx f (x) > for x I d dx f (x) > for x I It should be noted that n denotes discrete time up to the finite value l, the input X is applied as an initial value x() and the output is given via one-bit quantizer Q. incef is expanding, it can generate chaos if l = : such an IF is often referred to as chaotic -D return map [9]. We introduce two examples included in Equation (). Fig. (a) shows the first example described by Equation (2). { 2x(n) for x(n) I x(n +)=, y(n) =Q(x(n)) (2) 2x(n) for x(n) I where I =[,.5) and I =[.5, ].AsshowninFig.(a),codesand are assigned when an orbit hits left and right branch, respectively. In the figure 2 3 binary codes are assigned for 2 3 bins for code length l =3.Forl< this IF is used as an binary encoder []. For l = this IF generates chaos and is called the cut map [9]. Fig. (b) shows the second example described by Equation (3). { 2x(n)+ forx(n) I x(n +)=, y(n) =Q(x(n)) (3) 2x(n) for x(n) I where I =[,.5) and I =[.5, ]. As shown in Fig. (b), codes and are assigned when an orbit hits left and right branch, respectively. In the figure 2 3 Gray codes are assigned for 2 3 bins for code length l =3. For l< this IF is used as a Gray encoder []. For l = this IF generates chaos. We refer to this chaotic map as the valley map that is an analogue of the tent map [9]. Comparing such cyclic ADCs with chaotic maps, we should note at least the following two points. First, dynamics of ADCs is considered for finite time ( n<l< ) and dynamics of chaotic map is considered for infinite time ( n ). econd, in the ADCs, we pay our attention saito.tex; 4//26; 4:56; p.3

4 4 aito, himakawa and Torikai x n+ x n+ (a) (b).5.5 f.5 3 ( x n ).5 x n 3 f ( x n ) x n x n Figure. Cyclic ADCs based on chaotic maps where x n x(n). (a) Cut map and its 3-fold composition f 3, (b) Valley map and its 3-fold composition f 3. x n to an finite output sequence y depending on some initial state X that is an analog input. In the chaotic maps, we pay our attention to statistic properties of an infinite sequence {x(n)} which is independent of initial state [9]. 3. DACs and contractive IFs DACs use inverse operation of ADCs in principle. As an ADC is described by an expanding IF as in ection 2, a corresponding DAC can be described by a contractive IF. Let an ADC of Equation () convert an analog value X into a digital sequence y with finite length l. In order to decode y, the DAC uses the following digital input Y that is the inverse sequence of y: Y {Y (),,Y(l)} = {y(l),,y()}, Y(n) {, } or equivalently Y (i) =y(l i + ) for i l. (4) saito.tex; 4//26; 4:56; p.4

5 DAC and IF 5 X n+ (a) (b) "" "" " " " " X n X n+ X n Figure 2. (a) DAC for binary decoding for for (,, ). (,, ), (b) DAC for Gray decoding Let X I denote an output of the DAC. X is often referred to as an estimation of X. The operation of the DAC can be described by { f X(n +)= (X(n)) for Y (n) = f (X(n)) for Y (n) =, X = X(l) (5) where n l<.ifaninitialvaluex() and an input Y are given, Equation (5) is updated and the final value X(l) is to be the output. ince f and f are affine mappings, we can guarantee existence of their inverse mappings f : I I and f : I I. It should be noted that f and f are contractive since f and f are expanding: Equation (5) is an IF consisting of contractive mappings. Based on Equation (5), we can give two DACs corresponding to two ADCs in Equations (2) and (3). If Y is given by Equation (2) for binary encoding, the decoding is realized by the following DAC..5(X(n) + ) for Y (n) = X(n +)= (6).5(X(n) + ) for Y (n) = Fig. 2 (a) shows dynamics of this DAC for input Y =(,, ). ince this IF is contractive with ratio.5, the output can satisfy X(3) ( 8, 2 8 ) for any initial value X() (, ). If Y is given by Equation (3) for Gray encoding, the decoding is realized by the following DAC..5( X(n) + ) for Y (n) = X(n +)= (7).5(X(n) + ) for Y (n) = Fig. 2 (b) shows dynamics of this DAC for input Y =(,, ). For any initial value X() (, ) this DAC outputs X(3) ( 8, 2 8 ). saito.tex; 4//26; 4:56; p.5

6 6 aito, himakawa and Torikai For these two DACs with contractive ratio.5 we have the following estimation error criterion. X X < 2 l for any X() I. (8) This criterion is basic to evaluate performance of these DACs, however, it is hard to give such a criterion for generalized cases of Equation (5). As suggested in ection I, contractive IFs have many applications. Here we introduce an interesting example: the chaos game representation ( ab. CGR [7] ) for analysis of DNA sequences. The dynamics of the CGR is two dimensional analogue of Equation (6): X(n +)=.5(X(n)+Y (n)) (9) where X (X,X 2 )andy (Y,Y 2 ). Y can take four values corresponding to four bases of a DNA sequence: Y {a, t, c, g}, where a (, ), t (, ), c (, ) and g (, ). As a DNA sequence is applied to the CGR, the sequence {X(n)} for n l may construct aproperimageforanyx() I I that can be used to investigate patterns in the DNA sequence. In addition, if one element of the four baseslacks,e.g.,y {a, t, g}, the image is to be the ierpinski triangle as shown in Fig. 3: it corresponds to the chaos game [7]. Comparing such cyclic DACs with CGR as a typical contractive IF, we should note at least the following two points. First, Y is an encoded digital input in the DACs and is a DNA data in the CGR. econd, the output is a point X(l) at finite time l in the DACs and is a limit set {X(n)} such as ierpinski triangle in the CGR. c (,) g(, ) a (,) t(,) Figure 3. The result of the chaos game on three points ( ierpinski triangle ) saito.tex; 4//26; 4:56; p.6

7 DAC and IF 7 4. Test Circuits We now consider implementation examples of basic DACs based on intermittently coupled switched capacitors [5], [], []. Fig. 4 (a) shows a simple test circuit of binary decoder. In the figure two capacitors are controlled by switch with period T such that =on for the first half period (n.5)t t<nt, =off for the second half period nt t<(n +.5)T. The switch operates in inverse phase of. In the experiment, we.. have used analog switches 466 with V DD =8VandV = -8V. An digital input y {,E} is applied to the circuit as a voltage source with clock period T.Letv ((n.5)t )=v (n) where n l. If y(t) = during one period (n.5)t t<(n +.5)T ( Y (n) =) then the capacitor voltages are given by v 2 (t) =, v (t) =v (n) for =on () v 2 (t) =v (t) =.5(v (n) + ) = v (n +) for =off If y(t) =E during one period ( Y (n) = ) then the capacitor voltages are given by v 2 (t) =E, v (t) =v (n) for =on () v 2 (t) =v (t) =.5(v (n)+e) =v (n +) for =off Using transformations X(n) = v (n) y(nt ) E and Y (n) = E, Equations () and () are transformed into Equation (6): this circuit can realize binary decoding. Fig. 4 (b) shows a simple test circuit of a DAC for Gray decoding. Operations of and are the same as Fig. 4 (a). Let v 3 ((n.5)t )= v (n). An digital input y {V,V DD } is applied to the circuit via switch u with clock period T.Ify(t) =V during one period (n.5)t t<(n +.5)T ( Y (n) = ) then u =on and the capacitor voltages are given by v (t) = v 3 (t) = v (n), v 2 (t) =E for =on v (t) =v 2 (t) =.5( v (n)+e) =v 3 (t) =v (n +) for =off (2) If y(t) =V DD during one period ( Y (n) = ) then u =off and the capacitor voltages are given by v (t) =v (n), v 2 (t) =E for =on v (t) =v 2 (t) =.5(v (n)+e) =v 3 (t) =v (n +) for =off (3) saito.tex; 4//26; 4:56; p.7

8 8 aito, himakawa and Torikai (a) y C v2 C v (b) y =V E C v 2 C v u C h v 3 Figure 4. Test circuits. (a) DAC for binary decoding (cut map), (b) DAC for Gray decoding (valley map) Using transformations X(n) = v (n) E and Y (n) = y(nt ) V V DD V,Equations (2) and (3) are transformed into Equation (7): this circuit can realize Gray decoding. It should be noted that these circuits are robust because they are based on contractive IFs. Fig. 5 shows laboratory measurement by these test circuits. In the figure the output y corresponds to 4-bit sequences () or () and we can see that capacitor voltage v enters alternately into two bins corresponding to () and (). These data confirm operation of binary and Gray decodings. 5. Conclusions We have considered cyclic ADCs and DACs as applications of IFs. Dynamics of ADCs and DACs are described in terms of IFs. Noting typical examples, character of ADCs and DACs are compared with that od IFs. Basic implementation circuits of DACs are also showns. Here we may say that requests of researchers of ADCs and DACs include simple and concrete circuit implementation with efficient performances such as high-resolution and low-distortion. On the other hand, interests of IFs researchers include generalized system description and classification of the phenomena. We should try to make up these gaps in order to develop study of analog signal processing and nonlinear dynamical systems. saito.tex; 4//26; 4:56; p.8

9 DAC and IF 9 y v v t (a ) (b ) Figure 5. Laboratory measurements ( T. =[ms],e. = [v], C. =66[nF]).(a)DAC for binary decoding, (b) DAC for Gray decoding. References. Jespers, P. G. A., Integrated converters, Oxford, ignell,, Jonsson, B., tenstrom, H. and Tan, N., New A/D converter architectures based on Gray coding, Proceedings of the IEEE International ymposium on Circuits and ystems, Hong Kong, June 9-2, 997, pp Chiaburu, L. and ignell,., An improved binary algorithmic A/D converter architecture, Proceedings of the IEEE International ymposium on Circuits and ystems, Bangkok, May 25-28, 23, pp Cauwenberghs, G., A micropower CMO algorithmic A/D/A converter, IEEE Transactions on Circuits and ystems, I, 42, 995, Weyton, L. and Audenaert,., Two-capacitor DAC with compensative switching, Electronics Letters, 3, 995, Barnsley, M. F., Fractals everywhere, pringler-verlag, New York, Jeffrey, H. J., Chaos game representation of gene structure, Nucleic Acids Research, 8, 99, Habutsu, T., Nishio, Y., asase. I. and Mori,., A secret key cryptosystem using a chaotic map, Transactions of the IEICE Fundamentals, E73-A, 99, Ott, E., Chaos in dynamical systems, Cambridge, 993. saito.tex; 4//26; 4:56; p.9

10 aito, himakawa and Torikai. Matsushita, T, aito, T. and Torikai, H., Basic synchronous phenomena by intermittently coupled capacitors, IEEE Transactions on Circuits and ystems, I, 47, 7, 2, himakawa, J. and aito, T., Cyclic D/A converters based on iterated function systems, Transactions of the IEICE Fundamentals, E87-A,, 24, saito.tex; 4//26; 4:56; p.