Programmable Logic Devices II

Transcription

1 Lecture 04: Efficient Design of Sequential Circuits Prof. Arliones Hoeller Prof. Marcos Moecke 1 / 94

2 Reference These slides are based on the material made available by the author of the book in the reference bellow Pong P. Chu, Chapter 8 Efficient Design of Sequential Circuits, In RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability. Wiley-IEEE Press, Hoboken, 2006, Pages 1-22, ISBN / 94

3 Outline Overview on sequential circuits Synchronous circuits Danger of synthesizing asynchronous circuit Inference of basic memory elements Simple design examples Timing analysis Alternative one-segment coding style Use of variable for sequential circuit 3 / 94

4 Overview on sequential circuit Combinational vs sequential circuit Sequential circuit: output is a function of current input and state (memory) Basic memory elements D latch D FF (Flip-Flop) RAM Synchronous vs asynchronous circuit 4 / 94

5 D latch: level sensitive D FF: edge sensitive 5 / 94

6 6 / 94

7 Problem wit D latch: Can the two D latches swap data? 7 / 94

8 Timing of a D FF: Clock-to-q delay Constraint: setup time and hold time 8 / 94

9 Synch vs asynch circuits Globally synchronous circuit: all memory elements (D FFs) controlled (synchronized) by a common global clock signal Globally asynchronous but locally synchronous circuit (GALS). Globally asynchronous circuit Use D FF but not a global clock Use no clock signal 9 / 94

10 Synchronous circuit One of the most difficult design aspects of a sequential circuit: How to satisfy the timing constraints The Big idea: Synchronous methodology Group all D FFs together with a single clock: Synchronous methodology Only need to deal with the timing constraint of one memory element 10 / 94

11 Basic block diagram State register (memory elements) Next-state logic (combinational circuit) Output logic (combinational circuit) Operation At the rising edge of the clock, state_next sampled and stored into the register (and becomes the new value of state_reg The next-state logic determines the new value (new state_next) and the output logic generates the output At the rising edge of the clock, the new value of state_next sampled and stored into the register Glitches has no effects as long as the state_next is stabled at the sampling edge 11 / 94

12 12 / 94

13 Sync circuit and EDA Synthesis: reduce to combinational circuit synthesis Timing analysis: involve only a single closed feedback loop (others reduce to combinational circuit analysis) Simulation: support cycle-based simulation Testing: can facilitate scan-chain 13 / 94

14 Types of sync circuits Not formally defined, Just for coding Three types: Regular sequential circuit Random sequential circuit (FSM) Combined sequential circuit (FSM with a Data path, FSMD) 14 / 94

15 Danger of synthesizing asynchronous circuit D Latch/DFF Are combinational circuits with feedback loop Design is different from normal combinational circuits (it is delay-sensitive) Should not be synthesized from scratch Should use pre-designed cells from device library 15 / 94

16 E.g., a D latch from scratch 16 / 94

17 17 / 94

18 Inference of basic memory elements VHDL code should be clear so that the pre-designed cells can be inferred VHDL code D Latch Positive edge-triggered D FF Negative edge-triggered D FF D FF with asynchronous reset 18 / 94

19 D Latch No else branch D latch will be inferred 19 / 94

20 Pos edge-triggered D FF No else branch Note the sensitivity list 20 / 94

21 Neg edge-triggered D FF 21 / 94

22 D FF with async reset No else branch Note the sensitivity list 22 / 94

23 Register Multiple D FFs with same clock and reset 23 / 94

24 Simple design examples Follow the block diagram Register Next-state logic (combinational circuit) Output logic (combinational circuit) 24 / 94

25 D FF with sync enable Note that the en is controlled by clock Note the sensitivity list 25 / 94

26 26 / 94

27 27 / 94

28 T FF 28 / 94

29 29 / 94

30 30 / 94

31 Free-running shift register 31 / 94

32 32 / 94

33 33 / 94

34 34 / 94

35 Universal shift register 4 ops: parallel load, shift right, shift left, pause 35 / 94

36 36 / 94

37 37 / 94

38 Arbitrary sequence counter 38 / 94

39 39 / 94

40 Free-running binary counter Count in binary sequence With a max_pulse output: asserted when counter is in state 40 / 94

41 41 / 94

42 Wrapped around automatically Poor practice: 42 / 94

43 Binary counter with bells & whistles 43 / 94

44 44 / 94

45 Decade (mod-10) counter 45 / 94

46 46 / 94

47 Timing analysis Combinational circuit: characterized by propagation delay Sequential circuit: Has to satisfy setup/hold time constraint Characterized by maximal clock rate (e.g., 200 MHz counter, 2.4 GHz Pentium II) Setup time and clock-to-q delay of register and the propagation delay of next-state logic are embedded in clock rate 47 / 94

48 state_next must satisfy the constraint Must consider effect of state_reg: can be controlled synchronized external input (from a subsystem of same clock) unsynchronized external input Approach First 2: adjust clock rate to prevent violation Last: use synchronization circuit to resolve violation 48 / 94

49 Setup time violation and maximal clock rate 49 / 94

50 50 / 94

51 E.g., shift register; let Tcq=1.0ns Tsetup=0.5ns 51 / 94

52 E.g., Binary counter; let Tcq=1.0ns Tsetup=0.5ns 52 / 94

53 53 / 94

54 Hold time violation 54 / 94

55 55 / 94

56 Output delay 56 / 94

57 D FF with sync enable 57 / 94

58 58 / 94

59 59 / 94

60 Interpretation: any left-hand-side signal within the clk event and clik= 1 branch infers a D FF 60 / 94

61 D FF with sync enable (FPGA) 61 / 94

62 T FF 62 / 94

63 63 / 94

64 64 / 94

65 65 / 94

66 T FF (FPGA) 66 / 94

67 Binary counter with bells & whistles 67 / 94

68 68 / 94

69 69 / 94

70 Contador binário com pulso em max 70 / 94

71 71 / 94

72 72 / 94

73 73 / 94

74 74 / 94

75 Uso de Variable: Inference of FF/Register Signal assignment on rising(falling) edge of the clock => Inference of FF/Register. Variable assignment on rising(falling) edge of the clock: If assigned a value before it is used, it will get a value every time when the process is invoked and there is no need to keep its previous value => no memory is inferred if used before it is assigned a value, it will use the value from the previous process execution. The variable has to memorize the value between the process invocations => FF/register will be inferred. 75 / 94

76 Uso de Variable: (a AND b) registrado 76 / 94

77 77 / 94

78 78 / 94

79 Tentativa 2 - OK Tentativa 1 signal NOK Tentativa 3 variable NOK 79 / 94

80 Contador programável mod-m 80 / 94

81 81 / 94

82 82 / 94

83 83 / 94

84 84 / 94

85 85 / 94

86 86 / 94

87 87 / 94

88 88 / 94

89 89 / 94

90 90 / 94

91 91 / 94

92 Two-segment X One-segment Two-segment code Separate memory segment from the rest Can be little cumbersome Has a clear mapping to hardware component One-segment code Mix memory segment and next-state logic / output logic Can sometimes be more compact No clear hardware mapping Error prone Two-segment code is preferred 92 / 94

93 Timing constraints combinational circuit => desired maximal propagation delay. sequential circuit => desired maximal clock rate. In a synchronous design, maximal clock rate => maximal propagation delay of the combinational next-state logic 93 / 94

94 Synthesis guidelines Strictly follow the synchronous design methodology; => all registers should be synchronized by a common global clock signal. Isolate the memory components => code them in a separate segment. The memory components should be coded clearly => predesigned cell can be inferred from the device library. Asynchronous reset, only for system initialization. Unless there is a compelling reason, a variable should not be used to infer a memory component. 94 / 94