數位系統設計 Digital System Design

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1 數位系統設計 Digital System Design Instructor: Kuan Jen Lin ( 林寬仁 ) kjlin@mails.fju.edu.tw Web: Room: SF 727B 1

2 電子電機產業消費性通訊控制生醫多媒體綠能作業系統開發工具驅動程式 PCB System board IC 元件感測元件半導體產業 2

3 職能類型軟體工程師韌體工程師數位硬體工程師 (IC 系統 ) 類比硬體工程師 (IC 系統 ) 3

4 數位系統設計相關課程邏輯設計 ( 大一下 ) 邏輯設計實驗 ( 大二上 ) 數位系統設計 (Verilog HDL, 大二上 ) 微算機概論 ( 大三上 ) 可程式系統晶片設計實習 ( 大三下 ) 4

5 Textbook Main textbook 1. Michael D. Ciletti, Advanced Digital Design with the Verilog HDL, Prentice Hall, 2003 References 1. Samir Palnitkar, Verilog HDL A Guide to Gidital Design and Synthesis, Prentice Hall. 2. Thomas & Moorby s, The Verilog Hardware Description Language, 5th edition, KAP,

6 Contents Verilog HDL Logic design with behavioral models Synthesis of combinational and sequential logic Design and Synthesis of Datapath controller Data path Controller Chapter 4~ 7 6

7 Grading 期中考 30% 期末考 40% 作業其他 30% 曠課一次扣總分 10 分, 滿 3 次即不及格遲到一次扣總分 3 分, 病假需有醫師之診斷證明 7

8 Design Flow Specification RTL design and Simulation Logic Synthesis Gate Level Simulation ASIC Layout FPGA Implementation 8

9 9

10 System-level design RTL-level design gate-level design (cell-based) Transistor-level design Physical design (layout) 微算機系統晶片設計實驗邏輯設計數位系統設計可程式系統晶片實習數位晶片設計概論 ( 含實驗 ) VLSI 電路設計導論電子學數位積體電路設計類比機體電路設計 10

11 Review of Logic Design 11

12 Boolean Algebra 12

13 13

14 Boolean Algebra A set of elements B and two binary operators + and 1. Closure w.r.t. the operator + ( ) x, y B x+y B 2. An identity element w.r.t. + ( ) 0+x = x+0 = x 1 x = x 1= x 3. Commutative w.r.t. + ( ) x+y = y+x x y = y x 14

15 Boolean Algebra 4. is distributive over +: x (y+z)=(x y)+(x z) + is distributive over : x+(y z)=(x+y) (x+z) 5. x B, x' B (complement of x) x+x'=1 and x x'=0 6. at least two elements x, y B x y What are the differences from general algebraic structure? 15

16 Boolean Cube 16

17 Boolean Function 17

18 Algebraic Simplification Multiplying out and factoring a(b+c) = ab+ac Combining terms abc d+abcd = abd Eliminating terms ab+abd = ab Eliminating literals a+a b = a+b Adding redundant terms ab+a c+bc = ab+a c +bc(a+a ) 18

19 xy + x'z + yz = xy + x'z + yz(x+x') = xy + x'z + yzx + yzx' =xy(1+z) + x'z(1+y) =xy +x'z (Consensus Theorem) DeMorgan's Theorems (x+y)' = x' y' (x y)' = x' + y' 19

20 Minterm and Maxterm A B C Minterms A B C = m 0 A B C = m 1 A B C = m 2 A B C = m 3 A B C = m 4 A B C = m 5 A B C = m 6 A B C = m 7 A B C Maxterms A + B + C = M 0 A + B + C = M 1 A + B + C = M 2 A + B + C = M 3 A + B + C = M 4 A + B + C = M 5 A + B + C = M 6 A + B + C = M 7 m j = M j A maxterm is a set of 2 n-1 minterms 20

21 Canonical form An Boolean function can be expressed by A truth table Sum of minterms Product of maxterms F(x, y, z) = Σ(1, 3, 6, 7) F(x, y, z) = Π (0, 2, 4, 6) 21

22 Standard Forms Canonical forms are seldom used Standard forms: Sum of products (SOP) Product of sums (POS) Sum of products F 1 = y' + zy+ x'yz' Product of sums F 2 = x(y'+z)(x'+y+z'+w) 22

23 Logic minimization using K-map 23

24 Example 3-2 F(x,y,z) = Σ(3,4,6,7) = yz+ xz' 24

25 Example 3-6 Simplify the Boolean function F = A B C + B CD + A B C D + AB C 25

26 F = yz + w'x'; F = yz + w'z F = Σ(0,1,2,3,7,11,15) ; F = Σ(1,3,5,7,11,15) either expression is acceptable f 26

27 Prime Implicants Implicant: A product term only covers the minterm of a function. A prime implicant: a product term obtained by combining the maximum possible number of adjacent squares (combining all possible maximum numbers of squares) Essential implicant: a minterm is covered by only one prime implicant The essential P.I. must be included 27

28 Consider F( A, B, C, D ) = (0, 2,3,5,7,8,9,10,11,13,15) the simplified expression may not be unique F = BD+B'D'+CD+AD = BD+B'D'+CD+AB = BD+B'D'+B'C+AD = BD+B'D'+B'C+AB' 28

29 Two-level Implementation Three ways to implement F = AB + CD 29

30 Combinational Circuit Module 30

31 Full Adder 31

32 Four Bits Binary adder 32

33 Reduce the carry propagation delay Employ faster gates Look-ahead carry (more complex mechanism, yet faster) carry propagate: P i = A i B i carry generate: G i = A i B i sum: S i = P i C i carry: C i+1 = G i +P i C i C 1 = G 0 +P 0 C 0 C 2 = G 1 +P 1 C 1 = G 1 +P 1 (G 0 +P 0 C 0 ) = G 1 +P 1 G 0 +P 1 P 0 C 0 C 3 = G 2 +P 2 C 2 = G 2 +P 2 G 1 +P 2 P 1 G 0 + P 2 P 1 P 0 C 0 33

34 Logic diagram 34

35 4-bit carrylook ahead adder 35

36 3-to-8 Decoder Fig Three-to-eight-line decoder. 36

37 A decoder with an enable input Receive information on a single line and transmits it on one of 2 n possible output lines Fig Two-to-four-line decoder with enable input 37

38 Expansion Fig decoder constructed with two 3 8 decoders 38

39 Priority Encoder resolve the ambiguity of illegal inputs only one of the input is encoded D 3 has the highest priority D 0 has the lowest priority X: don't-care conditions V: valid output indicator 39

40 Multiplexers select binary information from one of many input lines and direct it to a single output line 2 n input lines, n selection lines and one output line e.g.: 2-to-1-line multiplexer Fig. 4.24: Two-to-one-line multiplexer 40

41 4-to-1-line multiplexer Fig Four-to-one-line multiplexer 41

42 Sequential Circuit 42

43 D Latch One way to eliminate the undesirable condition of the indeterminate state in the SR latch is to ensure that inputs S and R are never equal to 1 at the same time. Transparency latch 43

44 Race X D Q Y clk 44

45 Edge-Triggered D Flip-Flop Transparency latch, level triggered Transparency latch This is a Negative-Edge-Triggered Flip-Flop Note the timing constraint between clock and D 45

46 JK Flip-Flop The J input sets the flip-flop to 1, the K input reset it to 0, and when both inputs are enabled, the output is complemented. D = JQ + K Q 46

47 T Flip-Flop D = T Q = TQ + T Q 47

48 Characteristic Tables and Equations 48

49 Fig. 5.21: Block diagram of Mealy and Moore state machine 49

50 Design Procedure the word description of the circuit behavior (a state diagram) state reduction if necessary assign binary values to the states obtain the binary-coded state table choose the type of flip-flops derive the simplified flip-flop input equations and output equations draw the logic diagram 50

51 Synthesis using D flip-flops An example state diagram and state table Fig State diagram for sequence detector 51

52 The flip-flop input equations A(t+1) = D A (A,B,x) = Σ(3,5,7) B(t+1) = D B (A,B,x) = Σ(1,5,7) The output equation y(a,b,x) = Σ(6,7) Logic minimization using the K map D A = Ax + Bx D B = Ax + B'x y = AB 52

53 Fig Maps for sequence detector 53

54 Sequence detector The logic diagram Fig Logic diagram of sequence detector 54

55 Excitation tables A state diagram flip-flop input functions straightforward for D flip-flops we need excitation tables for JK and T flip-flops Q(t) Q(t+1) D X 0 0 X

56 Synthesis using JK flip-flops The same example The state table and JK flip-flop inputs 56

57 J A = Bx'; K A = Bx J B = x; K B = (A x) y =? Fig Maps for J and K input equations 57

58 Fig Logic diagram for sequential circuit with JK flip-flops 58

59 Sequential Circuit Module 59

60 Logic design 6, Dept. of EE, Fu Jen Catholic University, Taiwan 60

61 Waveform of 4-Bit Synchronous Counter Clock A0 A1 A2 A3 Logic design 6, Dept. of EE, Fu Jen Catholic University, Taiwan 61

62 1 0 1 Up-Down Counter Up: 0000=>0001=>0010.=>1111=> Down: 1111=>1110=>1101=>.=>0000=>

63 Ring Counter Logic design 6, Dept. of EE, Fu Jen Catholic University, Taiwan 63

65 SERIAL LINE CODE FORMATS Logic design 6, Dept. of EE, Fu Jen Catholic University, Taiwan 65

EEA051 - Digital Logic 數位邏輯吳俊興高雄大學資訊工程學系. September 2004

EEA051 - Digital Logic 數位邏輯吳俊興高雄大學資訊工程學系. September 2004 EEA051 - Digital Logic 數位邏輯吳俊興高雄大學資訊工程學系 September 2004 Boolean Algebra (formulated by E.V. Huntington, 1904) A set of elements B={0,1} and two binary operators + and Huntington postulates 1. Closure