CVD-3 MFSIN-HU-1 SiN x Mixed Frequency Process
|
|
- Marsha Hopkins
- 6 years ago
- Views:
Transcription
1 CVD-3 MFSIN-HU-1 SiN x Mixed Frequency Process Standard MFSIN-HU-1 Process Top C Bottom C Pump to Base Time (s) SiH 4 Flow HF/ LF NH 3 Flow HF/LF N 2 HF/LF HF (watts) LF (watts) HF Time LF Time Pressure (mtorr) Dep. Time min:s.s Pump to Base Time (s) Wafer Size (in) a /35 40/ / s 2s 900 Variable Slide Outline Click to navigate Optical properties Growth Rate and Uniformity Roughness, Stress, Etch Electrical Data Quantox Electrical Data Probe station Elemental Composition Baseline Statistics Optical Model Roughness Data detail XRR Data Quantox SPV-V/Q-V Curve Expanded Probe station data Parameter Extraction method (probe station data) a) Samples smaller than 5mm across will not match the results in this dataset because of edge effects samples other than whole 6 wafers should be placed on aluminum carrier 6/9/14 P. de Rouffignac 1
2 Optical Properties Wavelength, nm Refractive Index, n a Absorption Coefficient, k b Transmission Optical Model c TBD cauchy a, b) Taken from the optical constants vs wavelength curve; Woollam WVASE 32; nm 3nm steps; 55,65,75 c) Click on link for detailed description of model 6/9/14 P. de Rouffignac 2
3 Growth Rate and Uniformity: HFSIN Run # a Growth Rate b (nm/min) Std. Uniformity c 6 wafer Max/min Uniformity d Linear or non-linear w/time % 4.1 % linear % 4.2% linear a) Run 1 is the first run after a chamber clean, run 2 is a subsequent run. b) Thickness data from Gaertner Scientific single wavelength (632.8nm) scanning ellipsometer using optical data from page 2 c) (1 sigma / mean ) 100 from the 49 point scanning ellipsometer ((Max Min) / mean) 100 6/9/14 P. de Rouffignac 3
4 Roughness, Stress, Etch, and Density Stress a, MPa Etch Rate dil. HF b (nm/min) Etch Rate BOE 5:1 c (nm/min) Ra Roughness, nm d Roughness % (Ra/T*100) Density g/cm 3 Density g/cm 3 post-anneal f 190 ± 20 TBD 210 ± % 2.41 e 2.52 a) Measured on FLX-2320-S Thin Film Stress (MET-1) at room temperature using 6 USA ring; tensile b) Diluted HF solution made by mixing 1 part 49% pure HF with 3 parts DI water (20mL HF + 60mL DI) yielding a HF solution of 15% w/w HF c) 49 % w/w HF; 3 samples d) 74nm film; Measured on SPM-5, Veeco NanoMan AFM, tapping mode, standard tip or Optical profiler e) Measured on a Rigaku Ultima III X-Ray Diffractometer at San Jose State, follow link to report f) Film annealed at 650C for 4 hours- based off of a thickness decrease of 4.5% 6/9/14 P. de Rouffignac 4
5 Electrical Data Quantox non-contact measurement 74nm SiNx; As-deposited Wafer Type Q eff a (e10 #/cm 2 ) V fb b Q total c (e10 #/cm 2 ) V t d V mid e D it f (e10 #/cm 2 ) Resistivity g (ohmcm) E tunnel h (MV/cm) Dielectric Constant p- type; 11 ohmcm e no data wafer broken Data averaged over 13 sites Wafer Type Q eff a (e10 #/cm 2 ) V fb b Q total c (e10 #/cm 2 ) V t d V mid e D it f (e10 #/cm 2 ) Resistivity g (ohmcm) E tunnel h (MV/cm) Dielectric Constant p- type; 11 ohmcm Click here for example Q-V and SPV-V Curves Data averaged over 13 sites on 1 run a) Q eff = total charge that acts to shift V fb from ideal b) V fb = potential where surface photovoltage is zero c) Q tot = sum of all charges from Si interface through film; charge at V fb from Q-V curve d) V t = Theoretical transistor turn on voltage e) V mid = potential at halfway point between max and min SPV voltage f) D it = density of fixed charges and non-charge based traps at Si-dielectric interface (negative values imply levels are < 1e10 #/cm 2) g) Dielectric Resistivity = Oxide is biased then turned off then voltage is tracked as a function of time h) E tunnel = similar but not same as breakdown; field where any additional charge on dielectric immediately leaks to silicon 6/9/14 P. de Rouffignac 5
6 Electrical Data MIS Devices on Probe Station Electrical Parameter As-Deposited b Annealed c Leakage Current Density (A/cm 2 at 2MV/cm) a ± ± Breakdown Field (MV/cm) 9.4 ± ± 0.3 ε (10 khz) 5.78 ± ± 0.01 ε (100 khz) 5.57 ± ± 0.02 ε (1 MHz) 4.52 ± ± 0.7 V FB (@100kHz) d ± ± 0.01 More data here Q eff (@100kHz) d ± ± N eff (e10) d 719 ± 4 71 ± 1 Q m d ± ± N m (e10) d 133 ± ± 0.4 a) Measured using probe station connected to Agilent 4156c and B1500 analyzers; aluminum pad sizes of cm 2 created using the liftoff technique All values listed derived from averages of at least three measurements per sample b) 1 Wafer batch on 02/21/14; run 15A deposition time 4 min; 6 p-type prime wafers, HF cleaned; 74 nm c) Wafer annealed at 425C in forming gas for 4 hours with contact pads present aluminum pad sizes of cm 2 ; backside contact sputtered gold d) V FB, Q eff, N eff, Q m, N m calculation method on Parameter Extraction Method slide 6/9/14 P. de Rouffignac 6
7 Film Composition and Contaminants VPD-ICPMS Al a Ca Cr Cu Fe Mg Ni K Na Ti Zn XPS b Si N O SiN 0.9 O 0.1 a) Surface trace metal analysis by VPD-ICPMS; 7mm edge exclusion; values in ppm (by weight) b) Measured on XPS (05/21/2014), after 45s sputter 200eV (depth profile) using survey results Carbon less than 1 % Higher than normal oxygen level, not sure if it was contamination during or after deposition 6/9/14 P. de Rouffignac 7
8 Baseline Statistics TBD a) d b) Blue line = running average c) Red lines = 1 sigma above and below avg 6/9/14 P. de Rouffignac 8
9 Optical Model Spectroscopic Ellipsometer Model An Bn Cn Ak Ideal or non-ideal MSE cauchy non-ideal < 6 0.3nm SiO2 at interface in the model Woollam WVASE 32; nm 3nm steps; 55,65,75 6/9/14 P. de Rouffignac 9
10 AFM Data Set Typical MFSINHU1 Run a) Sample: Run 15B, 4 min - 74 nm 6 wafer b) Roughness, Ra = 0.18nm c) Strange pits on surface, could be large pinholes Not sure if this process consistently displays this surface feature 6/9/14 P. de Rouffignac 10
11 XRR Data ANALYSIS CONDITION Wavelength (A): CuKa ( ) Divergence (deg): theta offset (deg): 0.0[--] Scale factor: (5) Background parameter: 1.e-7[--] Material Thickness (nm) Density Roughness (nm) SiN x /9/14 P. de Rouffignac 11
12 Quantox Data Example a) Site (40,-20) b) Sample 15B (4 min deposition, 74 nm), as-deposited 6/9/14 P. de Rouffignac 12
13 Expanded Probe Station Data 100 khz CV Curves IV Curves As'deposited% Annealed% 4.00E'10% 3.50E'10% 3.00E'10% 2.50E'10% 2.00E'10% 1.50E'10% 1.00E'10% 5.00E'11% '25% '20% '15% '10% '5% 0% 5% 0.00E+00% a) Sample 15A, 74nm b) X axis of IV curve in MV/cm c) Annealing reduced V FB shift, ΔV FB, and frequency related capacitance drop (frequency dispersion) d) Annealing did not change leakage significantly e) Much less frequency dispersion seen in CV curves post anneal 6/9/14 P. de Rouffignac 13
14 Parameter Extraction Method Er vacuum permivity C FB flat band capacitance d film thickness in meters λ Debye length (cm) A gate area (m 2 ) ε s permivity of Si (F/cm) 11.7*ε 0 C ox Oxide capacitance A gate area (cm 2 ) ε F/cm κt thermal RT (293K*1.3806e- 23 J/K) W MS metal semiconductor work funcon q electron charge (coulombs) V FB Forward flat band voltage N D (Nbulk) Bulk doping concentraon (cm - 3 ) Q eff effecve dielectric charge (coul/cm 2 ) N i Intrinsic carrier concentraon (cm - 3 ) N eff effecve charge concentraon #/cm 2 Dopetype +1 ptype / - 1 ntype' N m mobile charge concentraon Eq. 1 Eq. 2 Eq. 3 W ms = 0.61 kt q ln " N % BULK $ '(dopetype) # & C FB = C oxε s A / λ C ox +ε s A / λ Q eff = C ox(w ms V FB ) A! λ = ε kt $ s # & " q 2 N % Eq. 4 Eq. 5 Eq. 6 N eff = Q eff q Q m = C oxδv FB A The flat band capacitance is calculated in order to extract the flat band voltage, V FB, from the experimental C-V curves. Equations 1 and 2 The forward V FB is then used to determine the effective charge in the dielectric, Q eff. Equations 3 and 4 Equation 5 extracts the density (#/cm 2 ) of effective charges from Q eff and the charge of an electron, q. The effective mobile charge, Q m, in the dielectric is determined using the change in V FB between the forward and backward CV curves using equation 6. The mobile charge density is determined using equation 7. 6/9/14 P. de Rouffignac 14 N i Eq. 7 N m = Q m q
CVD-3 MFSIN-HU-2 SiN x Mixed Frequency Process
CVD-3 MFSIN-HU-2 SiN x Mixed Frequency Process Standard MFSIN-HU-2 Process Top C Bottom C Pump to Base Time (s) SiH 4 Flow HF/ LF NH 3 Flow HF/LF N 2 HF/LF HF (watts) LF (watts) HF Time LF Time Pressure
More informationCVD-3 SIO-HU SiO 2 Process
CVD-3 SIO-HU SiO 2 Process Top Electrode, C Bottom Electrode, C Pump to Base Time (s) SiH 4 Flow Standard SIO-HU Process N 2 O Flow N 2 HF (watts) LF (watts) Pressure (mtorr Deposition Time min:s.s Pump
More informationCVD-3 LFSIN SiN x Process
CVD-3 LFSIN SiN x Process Top Electrode, C Bottom Electrode, C Pump to Base Time (s) SiH 4 Flow Standard LFSIN Process NH 3 Flow N 2 HF (watts) LF (watts) Pressure (mtorr Deposition Time min:s.s Pump to
More informationPlasma Enhanced Chemical Vapor Deposition (PECVD) of Silicon Dioxide (SiO2) Using Oxford Instruments System 100 PECVD
University of Pennsylvania ScholarlyCommons Tool Data Browse by Type 2-7-2017 Plasma Enhanced Chemical Vapor Deposition (PECVD) of Silicon Dioxide (SiO2) Using Oxford Instruments System 100 PECVD Meredith
More informationSemiconductor Devices. C. Hu: Modern Semiconductor Devices for Integrated Circuits Chapter 5
Semiconductor Devices C. Hu: Modern Semiconductor Devices for Integrated Circuits Chapter 5 Global leader in environmental and industrial measurement Wednesday 3.2. afternoon Tour around facilities & lecture
More informationXPS/UPS and EFM. Brent Gila. XPS/UPS Ryan Davies EFM Andy Gerger
XPS/UPS and EFM Brent Gila XPS/UPS Ryan Davies EFM Andy Gerger XPS/ESCA X-ray photoelectron spectroscopy (XPS) also called Electron Spectroscopy for Chemical Analysis (ESCA) is a chemical surface analysis
More informationMENA9510 characterization course: Capacitance-voltage (CV) measurements
MENA9510 characterization course: Capacitance-voltage (CV) measurements 30.10.2017 Halvard Haug Outline Overview of interesting sample structures Ohmic and schottky contacts Why C-V for solar cells? The
More informationECE 340 Lecture 39 : MOS Capacitor II
ECE 340 Lecture 39 : MOS Capacitor II Class Outline: Effects of Real Surfaces Threshold Voltage MOS Capacitance-Voltage Analysis Things you should know when you leave Key Questions What are the effects
More information3B: Review. Nina Hong. U Penn, February J.A. Woollam Co., Inc. 1
2014 J.A. Woollam Co., Inc. www.jawoollam.com 1 3B: Review Nina Hong U Penn, February 2014 2014 J.A. Woollam Co., Inc. www.jawoollam.com 2 Review 1A: Introduction to WVASE: Fun Quiz! 1B: Cauchy 2A: Pt-by-Pt
More informationMS482 Materials Characterization ( 재료분석 ) Lecture Note 12: Summary. Byungha Shin Dept. of MSE, KAIST
2015 Fall Semester MS482 Materials Characterization ( 재료분석 ) Lecture Note 12: Summary Byungha Shin Dept. of MSE, KAIST 1 Course Information Syllabus 1. Overview of various characterization techniques (1
More informationJ. Price, 1,2 Y. Q. An, 1 M. C. Downer 1 1 The university of Texas at Austin, Department of Physics, Austin, TX
Understanding process-dependent oxygen vacancies in thin HfO 2 /SiO 2 stacked-films on Si (100) via competing electron-hole injection dynamic contributions to second harmonic generation. J. Price, 1,2
More informationCharacterization of Charge Trapping and Dielectric Breakdown of HfAlOx/SiON Dielectric Gate Stack
Characterization of Charge Trapping and Dielectric Breakdown of HfAlOx/SiON Dielectric Gate Stack Y. Pei, S. Nagamachi, H. Murakami, S. Higashi, S. Miyazaki, T. Kawahara and K. Torii Graduate School of
More informationMOS CAPACITOR AND MOSFET
EE336 Semiconductor Devices 1 MOS CAPACITOR AND MOSFET Dr. Mohammed M. Farag Ideal MOS Capacitor Semiconductor Devices Physics and Technology Chapter 5 EE336 Semiconductor Devices 2 MOS Capacitor Structure
More informationNormally-Off GaN Field Effect Power Transistors: Device Design and Process Technology Development
Center for High Performance Power Electronics Normally-Off GaN Field Effect Power Transistors: Device Design and Process Technology Development Dr. Wu Lu (614-292-3462, lu.173@osu.edu) Dr. Siddharth Rajan
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Professor Chenming Hu.
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EECS 130 Spring 2009 Professor Chenming Hu Midterm I Name: Closed book. One sheet of notes is
More informationFabrication and Characterization of Al/Al2O3/p-Si MOS Capacitors
Fabrication and Characterization of Al/Al2O3/p-Si MOS Capacitors 6 MOS capacitors were fabricated on silicon substrates. ALD deposited Aluminum Oxide was used as dielectric material. Various electrical
More informationDEPOSITION OF THIN TiO 2 FILMS BY DC MAGNETRON SPUTTERING METHOD
Chapter 4 DEPOSITION OF THIN TiO 2 FILMS BY DC MAGNETRON SPUTTERING METHOD 4.1 INTRODUCTION Sputter deposition process is another old technique being used in modern semiconductor industries. Sputtering
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Fall Exam 1
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EECS 143 Fall 2008 Exam 1 Professor Ali Javey Answer Key Name: SID: 1337 Closed book. One sheet
More informationPlasma-Surface Interactions in Patterning High-k k Dielectric Materials
Plasma-Surface Interactions in Patterning High-k k Dielectric Materials October 11, 4 Feature Level Compensation and Control Seminar Jane P. Chang Department of Chemical Engineering University of California,
More informationSupporting Information
Electronic Supplementary Material (ESI) for ChemComm. This journal is The Royal Society of Chemistry 2014 Supporting Information High-k Polymer/Graphene Oxide Dielectrics for Low-Voltage Flexible Nonvolatile
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals Bond Model of Electrons and Holes Si Si Si Si Si Si Si Si Si Silicon
More informationMS482 Materials Characterization ( 재료분석 ) Lecture Note 4: XRF
2016 Fall Semester MS482 Materials Characterization ( 재료분석 ) Lecture Note 4: XRF Byungha Shin Dept. of MSE, KAIST 1 Course Information Syllabus 1. Overview of various characterization techniques (1 lecture)
More informationThe interfacial study on the Cu 2 O/Ga 2 O 3 /AZO/TiO 2 photocathode for water splitting fabricated by pulsed laser deposition
Electronic Supplementary Material (ESI) for Catalysis Science & Technology. This journal is The Royal Society of Chemistry 2017 The interfacial study on the Cu 2 O/Ga 2 O 3 /AZO/TiO 2 photocathode for
More informationIn-situ Monitoring of Thin-Film Formation Processes by Spectroscopic Ellipsometry
In-situ Monitoring of Thin-Film Formation Processes by Spectroscopic Ellipsometry Alexey Kovalgin Chair of Semiconductor Components MESA+ Institute for Nanotechnology Motivation Advantages of in-situ over
More informationAn interfacial investigation of high-dielectric constant material hafnium oxide on Si substrate B
Thin Solid Films 488 (2005) 167 172 www.elsevier.com/locate/tsf An interfacial investigation of high-dielectric constant material hafnium oxide on Si substrate B S.C. Chen a, T, J.C. Lou a, C.H. Chien
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
More informationControl of Flat Band Voltage by Partial Incorporation of La 2 O 3 or Sc 2 O 3 into HfO 2 in Metal/HfO 2 /SiO 2 /Si MOS Capacitors
Control of Flat Band Voltage by Partial Incorporation of La 2 O 3 or Sc 2 O 3 into HfO 2 in Metal/HfO 2 /SiO 2 /Si MOS Capacitors M. Adachi 1, K. Okamoto 1, K. Kakushima 2, P. Ahmet 1, K. Tsutsui 2, N.
More informationAppendix 1: List of symbols
Appendix 1: List of symbols Symbol Description MKS Units a Acceleration m/s 2 a 0 Bohr radius m A Area m 2 A* Richardson constant m/s A C Collector area m 2 A E Emitter area m 2 b Bimolecular recombination
More informationScaling Issues in Planar FET: Dual Gate FET and FinFETs
Scaling Issues in Planar FET: Dual Gate FET and FinFETs Lecture 12 Dr. Amr Bayoumi Fall 2014 Advanced Devices (EC760) Arab Academy for Science and Technology - Cairo 1 Outline Scaling Issues for Planar
More informationSemilab Technologies for 450mm Wafer Metrology
Semilab Technologies for 450mm Wafer Metrology Tibor Pavelka Semilab Semiconductor Physics Laboratory Co. Ltd. Sem iconductorphysics Laboratory Co.Ltd. 1 Outline Short introduction to Semilab Technologies
More information1. The MOS Transistor. Electrical Conduction in Solids
Electrical Conduction in Solids!The band diagram describes the energy levels for electron in solids.!the lower filled band is named Valence Band.!The upper vacant band is named conduction band.!the distance
More informationan introduction to Semiconductor Devices
an introduction to Semiconductor Devices Donald A. Neamen Chapter 6 Fundamentals of the Metal-Oxide-Semiconductor Field-Effect Transistor Introduction: Chapter 6 1. MOSFET Structure 2. MOS Capacitor -
More informationElectronic Supplementary Information. Molecular Antenna Tailored Organic Thin-film Transistor for. Sensing Application
Electronic Supplementary Material (ESI) for Materials Horizons. This journal is The Royal Society of Chemistry 2017 Electronic Supplementary Information Molecular Antenna Tailored Organic Thin-film Transistor
More informationMSE 310/ECE 340: Electrical Properties of Materials Fall 2014 Department of Materials Science and Engineering Boise State University
MSE 310/ECE 340: Electrical Properties of Materials Fall 2014 Department of Materials Science and Engineering Boise State University Practice Final Exam 1 Read the questions carefully Label all figures
More informationLecture 6: 2D FET Electrostatics
Lecture 6: 2D FET Electrostatics 2016-02-01 Lecture 6, High Speed Devices 2014 1 Lecture 6: III-V FET DC I - MESFETs Reading Guide: Liu: 323-337 (he mainly focuses on the single heterostructure FET) Jena:
More informationCVD: General considerations.
CVD: General considerations. PVD: Move material from bulk to thin film form. Limited primarily to metals or simple materials. Limited by thermal stability/vapor pressure considerations. Typically requires
More information1 Name: Student number: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND. Fall :00-11:00
1 Name: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND Final Exam Physics 3000 December 11, 2012 Fall 2012 9:00-11:00 INSTRUCTIONS: 1. Answer all seven (7) questions.
More information(a) (b) Supplementary Figure 1. (a) (b) (a) Supplementary Figure 2. (a) (b) (c) (d) (e)
(a) (b) Supplementary Figure 1. (a) An AFM image of the device after the formation of the contact electrodes and the top gate dielectric Al 2 O 3. (b) A line scan performed along the white dashed line
More informationPlasma Deposition (Overview) Lecture 1
Plasma Deposition (Overview) Lecture 1 Material Processes Plasma Processing Plasma-assisted Deposition Implantation Surface Modification Development of Plasma-based processing Microelectronics needs (fabrication
More informationSemi-insulating SiC substrates for high frequency devices
Klausurtagung Silberbach, 19. - 21. Feb. 2002 Institut für Werkstoffwissenschaften - WW 6 Semi-insulating SiC substrates for high frequency devices Vortrag von Matthias Bickermann Semi-insulating SiC substrates
More informationECE 305 Exam 5 SOLUTIONS: Spring 2015 April 17, 2015 Mark Lundstrom Purdue University
NAME: PUID: : ECE 305 Exam 5 SOLUTIONS: April 17, 2015 Mark Lundstrom Purdue University This is a closed book exam. You may use a calculator and the formula sheet at the end of this exam. Following the
More informationStretching the Barriers An analysis of MOSFET Scaling. Presenters (in order) Zeinab Mousavi Stephanie Teich-McGoldrick Aseem Jain Jaspreet Wadhwa
Stretching the Barriers An analysis of MOSFET Scaling Presenters (in order) Zeinab Mousavi Stephanie Teich-McGoldrick Aseem Jain Jaspreet Wadhwa Why Small? Higher Current Lower Gate Capacitance Higher
More informationJFET/MESFET. JFET: small gate current (reverse leakage of the gate-to-channel junction) More gate leakage than MOSFET, less than bipolar.
JFET/MESFET JFET: small gate current (reverse leakage of the gate-to-channel junction) More gate leakage than MOSFET, less than bipolar. JFET has higher transconductance than the MOSFET. Used in low-noise,
More informationHybrid Wafer Level Bonding for 3D IC
Hybrid Wafer Level Bonding for 3D IC An Equipment Perspective Markus Wimplinger, Corporate Technology Development & IP Director History & Roadmap - BSI CIS Devices???? 2013 2 nd Generation 3D BSI CIS with
More informationLecture 12: MOS Capacitors, transistors. Context
Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those
More informationICP-MS Analysis of Bulk & Process Chemicals for Semiconductor Processes. Ann O Connell Chemical Analysis Eng Intel Corporation
ICPMS Analysis of Bulk & Process Chemicals for Semiconductor Processes Ann O Connell Chemical Analysis Eng Intel Corporation 1 Overview of Presentation Impact of Trace Metal contamination on Semiconductor
More informationFabrication Technology, Part I
EEL5225: Principles of MEMS Transducers (Fall 2004) Fabrication Technology, Part I Agenda: Microfabrication Overview Basic semiconductor devices Materials Key processes Oxidation Thin-film Deposition Reading:
More informationMaster Thesis. Effect of Alkali-earth-elements Incorporation on La 2 O 3 Dielectrics for Scaled Silicon MOS Device
Master Thesis Effect of Alkali-earth-elements Incorporation on Dielectrics for Scaled Silicon MOS Device Tomotsune Koyanagi Department of Electronics and Applied Physics Interdisciplinary Graduate School
More informationLecture 6 Plasmas. Chapters 10 &16 Wolf and Tauber. ECE611 / CHE611 Electronic Materials Processing Fall John Labram 1/68
Lecture 6 Plasmas Chapters 10 &16 Wolf and Tauber 1/68 Announcements Homework: Homework will be returned to you on Thursday (12 th October). Solutions will be also posted online on Thursday (12 th October)
More informationDISTRIBUTION OF POTENTIAL BARRIER HEIGHT LOCAL VALUES AT Al-SiO 2 AND Si-SiO 2 INTERFACES OF THE METAL-OXIDE-SEMICONDUCTOR (MOS) STRUCTURES
DISTRIBUTION OF POTENTIAL BARRIER HEIGHT LOCAL VALUES AT Al-SiO 2 AND Si-SiO 2 INTERFACES OF THE ETAL-OXIDE-SEICONDUCTOR (OS) STRUCTURES KRZYSZTOF PISKORSKI (kpisk@ite.waw.pl), HENRYK. PRZEWLOCKI Institute
More informationLarge Storage Window in a-sinx/nc-si/a-sinx Sandwiched Structure
2017 Asia-Pacific Engineering and Technology Conference (APETC 2017) ISBN: 978-1-60595-443-1 Large Storage Window in a-sinx/nc-si/a-sinx Sandwiched Structure Xiang Wang and Chao Song ABSTRACT The a-sin
More informationn i exp E g 2kT lnn i E g 2kT
HOMEWORK #10 12.19 For intrinsic semiconductors, the intrinsic carrier concentration n i depends on temperature as follows: n i exp E g 2kT (28.35a) or taking natural logarithms, lnn i E g 2kT (12.35b)
More informationFrequency dispersion effect and parameters. extraction method for novel HfO 2 as gate dielectric
048 SCIENCE CHINA Information Sciences April 2010 Vol. 53 No. 4: 878 884 doi: 10.1007/s11432-010-0079-8 Frequency dispersion effect and parameters extraction method for novel HfO 2 as gate dielectric LIU
More information3.155J/6.152J Microelectronic Processing Technology Fall Term, 2004
3.155J/6.152J Microelectronic Processing Technology Fall Term, 2004 Bob O'Handley Martin Schmidt Quiz Nov. 17, 2004 Ion implantation, diffusion [15] 1. a) Two identical p-type Si wafers (N a = 10 17 cm
More informationPHYSICAL ELECTRONICS(ECE3540) CHAPTER 9 METAL SEMICONDUCTOR AND SEMICONDUCTOR HETERO-JUNCTIONS
PHYSICAL ELECTRONICS(ECE3540) CHAPTER 9 METAL SEMICONDUCTOR AND SEMICONDUCTOR HETERO-JUNCTIONS Tennessee Technological University Wednesday, October 30, 013 1 Introduction Chapter 4: we considered the
More informationEllipsometric spectroscopy studies of compaction and decompaction of Si-SiO 2 systems
Ellipsometric spectroscopy studies of compaction and decompaction of Si-SiO 2 systems Paper Witold Rzodkiewicz and Andrzej Panas Abstract The influence of the strain on the optical properties of Si-SiO
More informationPHYSICAL ELECTRONICS(ECE3540) CHAPTER 9 METAL SEMICONDUCTOR AND SEMICONDUCTOR HETERO-JUNCTIONS
PHYSICAL ELECTRONICS(ECE3540) CHAPTER 9 METAL SEMICONDUCTOR AND SEMICONDUCTOR HETERO-JUNCTIONS Tennessee Technological University Monday, November 11, 013 1 Introduction Chapter 4: we considered the semiconductor
More informationESE 570 MOS TRANSISTOR THEORY Part 1. Kenneth R. Laker, University of Pennsylvania, updated 5Feb15
ESE 570 MOS TRANSISTOR THEORY Part 1 TwoTerminal MOS Structure 2 GATE Si Oxide interface n n Mass Action Law VB 2 Chemical Periodic Table Donors American Chemical Society (ACS) Acceptors Metalloids 3 Ideal
More informationPlasma Processing in the Microelectronics Industry. Bert Ellingboe Plasma Research Laboratory
Plasma Processing in the Microelectronics Industry Bert Ellingboe Plasma Research Laboratory Outline What has changed in the last 12 years? What is the relavant plasma physics? Sheath formation Sheath
More informationExtrinsic and Intrinsic Frequency Dispersion of High-k Materials in Capacitance-Voltage Measurements
Materials 01, 5, 1005-103; doi:10.3390/ma5061005 Review OPEN ACCESS materials ISSN 1996-1944 www.mdpi.com/journal/materials Extrinsic and Intrinsic Frequency Dispersion of High-k Materials in Capacitance-Voltage
More informationLecture 2. Introduction to semiconductors Structures and characteristics in semiconductors
Lecture 2 Introduction to semiconductors Structures and characteristics in semiconductors Semiconductor p-n junction Metal Oxide Silicon structure Semiconductor contact Literature Glen F. Knoll, Radiation
More informationEffects of plasma treatment on the precipitation of fluorine-doped silicon oxide
ARTICLE IN PRESS Journal of Physics and Chemistry of Solids 69 (2008) 555 560 www.elsevier.com/locate/jpcs Effects of plasma treatment on the precipitation of fluorine-doped silicon oxide Jun Wu a,, Ying-Lang
More informationELECTRON-cyclotron-resonance (ECR) plasma reactors
154 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 10, NO. 1, FEBRUARY 1997 Plasma-Parameter Dependence of Thin-Oxide Damage from Wafer Charging During Electron-Cyclotron-Resonance Plasma Processing
More informationCharacteristics and parameter extraction for NiGe/n-type Ge Schottky diode with variable annealing temperatures
034 Chin. Phys. B Vol. 19, No. 5 2010) 057303 Characteristics and parameter extraction for NiGe/n-type Ge Schottky diode with variable annealing temperatures Liu Hong-Xia ), Wu Xiao-Feng ), Hu Shi-Gang
More information! PN Junction. ! MOS Transistor Topology. ! Threshold. ! Operating Regions. " Resistive. " Saturation. " Subthreshold (next class)
ESE370: ircuitlevel Modeling, Design, and Optimization for Digital Systems Lec 7: September 20, 2017 MOS Transistor Operating Regions Part 1 Today! PN Junction! MOS Transistor Topology! Threshold! Operating
More informationHigh-Performance Semiconducting Polythiophenes for Organic Thin Film. Transistors by Beng S. Ong,* Yiliang Wu, Ping Liu and Sandra Gardner
Supplementary Materials for: High-Performance Semiconducting Polythiophenes for Organic Thin Film Transistors by Beng S. Ong,* Yiliang Wu, Ping Liu and Sandra Gardner 1. Materials and Instruments. All
More informationDevelopment of Radiation Hard Si Detectors
Development of Radiation Hard Si Detectors Dr. Ajay K. Srivastava On behalf of Detector Laboratory of the Institute for Experimental Physics University of Hamburg, D-22761, Germany. Ajay K. Srivastava
More informationCHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS
98 CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS In this chapter, the effect of gate electrode work function variation on DC
More informationElectrical Characteristics of MOS Devices
Electrical Characteristics of MOS Devices The MOS Capacitor Voltage components Accumulation, Depletion, Inversion Modes Effect of channel bias and substrate bias Effect of gate oide charges Threshold-voltage
More informationLecture 150 Basic IC Processes (10/10/01) Page ECE Analog Integrated Circuits and Systems P.E. Allen
Lecture 150 Basic IC Processes (10/10/01) Page 1501 LECTURE 150 BASIC IC PROCESSES (READING: TextSec. 2.2) INTRODUCTION Objective The objective of this presentation is: 1.) Introduce the fabrication of
More informationECEN 3320 Semiconductor Devices Final exam - Sunday December 17, 2000
Your Name: ECEN 3320 Semiconductor Devices Final exam - Sunday December 17, 2000 1. Review questions a) Illustrate the generation of a photocurrent in a p-n diode by drawing an energy band diagram. Indicate
More informationCHAPTER 18: Electrical properties
CHAPTER 18: Electrical properties ISSUES TO ADDRESS... How are electrical conductance and resistance characterized? What are the physical phenomena that distinguish conductors, semiconductors, and insulators?
More informationSupporting Information
Supporting Information Assembly and Densification of Nanowire Arrays via Shrinkage Jaehoon Bang, Jonghyun Choi, Fan Xia, Sun Sang Kwon, Ali Ashraf, Won Il Park, and SungWoo Nam*,, Department of Mechanical
More informationL ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling
L13 04202017 ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling Scaling laws: Generalized scaling (GS) p. 610 Design steps p.613 Nanotransistor issues (page 626) Degradation
More information! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 3, 018 MOS Transistor Theory, MOS Model Lecture Outline! CMOS Process Enhancements! Semiconductor Physics " Band gaps " Field Effects!
More informationLow temperature anodically grown silicon dioxide films for solar cell. Nicholas E. Grant
Low temperature anodically grown silicon dioxide films for solar cell applications Nicholas E. Grant Outline 1. Electrochemical cell design and properties. 2. Direct-current current anodic oxidations-part
More informationEE 560 MOS TRANSISTOR THEORY
1 EE 560 MOS TRANSISTOR THEORY PART 1 TWO TERMINAL MOS STRUCTURE V G (GATE VOLTAGE) 2 GATE OXIDE SiO 2 SUBSTRATE p-type doped Si (N A = 10 15 to 10 16 cm -3 ) t ox V B (SUBSTRATE VOLTAGE) EQUILIBRIUM:
More informationSupporting Information
Supporting Information Oh et al. 10.1073/pnas.0811923106 SI Text Hysteresis of BPE-PTCDI MW-TFTs. Fig. S9 represents bidirectional transfer plots at V DS 100VinN 2 atmosphere for transistors constructed
More informationAuger Electron Spectroscopy (AES) Prof. Paul K. Chu
Auger Electron Spectroscopy (AES) Prof. Paul K. Chu Auger Electron Spectroscopy Introduction Principles Instrumentation Qualitative analysis Quantitative analysis Depth profiling Mapping Examples The Auger
More informationTCAD Modeling of Stress Impact on Performance and Reliability
TCAD Modeling of Stress Impact on Performance and Reliability Xiaopeng Xu TCAD R&D, Synopsys March 16, 2010 SEMATECH Workshop on Stress Management for 3D ICs using Through Silicon Vias 1 Outline Introduction
More informationLecture 2. Introduction to semiconductors Structures and characteristics in semiconductors
Lecture 2 Introduction to semiconductors Structures and characteristics in semiconductors Semiconductor p-n junction Metal Oxide Silicon structure Semiconductor contact Literature Glen F. Knoll, Radiation
More informationExtensive reading materials on reserve, including
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
More information6.152J / 3.155J Spring 05 Lecture 08-- IC Lab Testing. IC Lab Testing. Outline. Structures to be Characterized. Sheet Resistance, N-square Resistor
IC Lab Testing Review Process Outline Structures to be Characterized Resistors Sheet Resistance, Nsquare Resistor MOS Capacitors Flatband Voltage, Threshold Voltage, Oxide Thickness, Oxide Charges, Substrate
More informationSECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University
NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula
More informationStudent Number: CARLETON UNIVERSITY SELECTED FINAL EXAMINATION QUESTIONS
Name: CARLETON UNIVERSITY SELECTE FINAL EXAMINATION QUESTIONS URATION: 6 HOURS epartment Name & Course Number: ELEC 3908 Course Instructors: S. P. McGarry Authorized Memoranda: Non-programmable calculators
More informationDept. of Materials Science and Engineering. Electrical Properties Of Materials
Problem Set 12 Solutions See handout "Part 4: Heterojunctions MOS Devices" (slides 9-18) Using the Boise State Energy Band Diagram program, build the following structure: Gate material: 5nm p + -Poly Si
More informationMOS Capacitor MOSFET Devices. MOSFET s. INEL Solid State Electronics. Manuel Toledo Quiñones. ECE Dept. UPRM.
INEL 6055 - Solid State Electronics ECE Dept. UPRM 20th March 2006 Definitions MOS Capacitor Isolated Metal, SiO 2, Si Threshold Voltage qφ m metal d vacuum level SiO qχ 2 E g /2 qφ F E C E i E F E v qφ
More information8. Schottky contacts / JFETs
Technische Universität Graz Institute of Solid State Physics 8. Schottky contacts / JFETs Nov. 21, 2018 Technische Universität Graz Institute of Solid State Physics metal - semiconductor contacts Photoelectric
More informationPlasmonic Hot Hole Generation by Interband Transition in Gold-Polyaniline
Supplementary Information Plasmonic Hot Hole Generation by Interband Transition in Gold-Polyaniline Tapan Barman, Amreen A. Hussain, Bikash Sharma, Arup R. Pal* Plasma Nanotech Lab, Physical Sciences Division,
More informationLecture 18 Field-Effect Transistors 3
Lecture 18 Field-Effect Transistors 3 Schroder: Chapters, 4, 6 1/38 Announcements Homework 4/6: Is online now. Due Today. I will return it next Wednesday (30 th May). Homework 5/6: It will be online later
More informationLecture 2. Introduction to semiconductors Structures and characteristics in semiconductors. Fabrication of semiconductor sensor
Lecture 2 Introduction to semiconductors Structures and characteristics in semiconductors Semiconductor p-n junction Metal Oxide Silicon structure Semiconductor contact Fabrication of semiconductor sensor
More informationContamination Monitoring of Semiconductor Processes by VPD HR-ICPMS
Contamination Monitoring of Semiconductor Processes by VPD HR-ICPMS Jürgen Lerche, SEMICON 2002 AMD, the AMD Arrow Logo and combinations thereof are trademarks of Advanced Micro Devices, Inc. 5/16/2002
More informationMoS 2 Thin Film Transistors using PECVD Dielectrics and Optical Contrast Modeling for Thickness Measurement
MoS 2 Thin Film Transistors using PECVD Dielectrics and Optical Contrast Modeling for Thickness Measurement by Nicholas Vardy A thesis presented to the University of Waterloo in fulfillment of the thesis
More informationABSTRACT INTRODUCTION
CHEMICAL VAPOR DEPOSITION OF ZIRCONIUM TIN TITANATE: A DIELECTRIC MATERIAL FOR POTENTIAL MICROELECTRONIC APPLICATIONS Ebony L. Mays 1, 4, Dennis W. Hess 2 1, 3, 4, and William S. Rees, Jr. Departments
More informationIntrinsic Electronic Transport Properties of High. Information
Intrinsic Electronic Transport Properties of High Quality and MoS 2 : Supporting Information Britton W. H. Baugher, Hugh O. H. Churchill, Yafang Yang, and Pablo Jarillo-Herrero Department of Physics, Massachusetts
More information! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 9, 019 MOS Transistor Theory, MOS Model Lecture Outline CMOS Process Enhancements Semiconductor Physics Band gaps Field Effects
More informationChallenges and Opportunities. Prof. J. Raynien Kwo 年
Nanoelectronics Beyond Si: Challenges and Opportunities Prof. J. Raynien Kwo 年 立 Si CMOS Device Scaling Beyond 22 nm node High κ,, Metal gates, and High mobility channel 1947 First Transistor 1960 1960
More informationELECTRONIC DEVICES AND CIRCUITS SUMMARY
ELECTRONIC DEVICES AND CIRCUITS SUMMARY Classification of Materials: Insulator: An insulator is a material that offers a very low level (or negligible) of conductivity when voltage is applied. Eg: Paper,
More informationT: +44 (0) W:
Ultraviolet Deposition of Thin Films and Nanostructures Ian W. Boyd ETC Brunel University Kingston Lane Uxbridge Middx UB8 3PH UK T: +44 (0)1895 267419 W: etcbrunel.co.uk E: ian.boyd@brunel.ac.uk Outline
More informationC-V and G-V Measurements Showing Single Electron Trapping in Nanocrystalline Silicon Dot Embedded in MOS Memory Structure
Mat. Res. Soc. Symp. Proc. Vol. 686 2002 Materials Research Society C-V and G-V Measurements Showing Single Electron Trapping in Nanocrystalline Silicon Dot Embedded in MOS Memory Structure Shaoyun Huang,
More information