C-V and G-V Measurements Showing Single Electron Trapping in Nanocrystalline Silicon Dot Embedded in MOS Memory Structure

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1 Mat. Res. Soc. Symp. Proc. Vol Materials Research Society C-V and G-V Measurements Showing Single Electron Trapping in Nanocrystalline Silicon Dot Embedded in MOS Memory Structure Shaoyun Huang, Souri Banerjee, and Shunri Oda Research Center for Quantum Effect Electronics, Tokyo Institute of Technology, O-okayama, Meguro-ku, Tokyo , JAPAN ABSTRACT We prepared a SiO 2 /nanocrystalline Si (nc-si)/sio 2 sandwich structure. A clear positive shift in C-V and G-V curves due to electrons trapped in nc-si dots has been observed at room temperature. The peak in conductance around flat band condition indicates that a trap event had occurred where an electron is stored per nc-si dot. A logarithmic charge loss function is found and this discharging process is independent of the thermal activation mechanism. The longer memory retention time and logarithmic charge loss in the dots are explained by a built-in electric field through the tunnel oxide, which varies with time, resulting in a variable tunneling probability. The electric repulsion induced by the built-in electric field hinders the discharging of electrons remained in the dots. INTRODUCTION Metal-Oxide-Semiconductor field-effect-transistor (MOSFET) memory structures based on silicon-quantum-dots or nanocrystals have recently attracted great interest both for new physical phenomena and for potential applications in next generation memory devices [1,2], in which silicon nanocrystals, embedded in the oxide layer between the control gate and channel, act as floating memory nodes. Many works have been devoted to fabricate ideal memory structures and to obtain reproducible hysteresis in current-voltage (I-V) characteristics [3,4]. However, the retention mechanism corresponding to interface defects are still unclear. In this kind of devices, the defects associated with nanocrystalline silicon (nc-si) often results in the long-term memory retention time [5]. In our previous work, Hinds et. al. investigated the retention time distribution in MOSFET memory devices and found the interface states were not the dominant mechanism for electron storage in the investigated device structure [6]. However, the detail retention mechanism (dots charging and discharging processes) should be further understood, which will directly give large influence on fast write/erase and long-term charge retention time in the device. The capacitance-voltage (C-V) and conductance-voltage (G-V) measurements are useful and sensitive tools for investigating interface characters between Si and SiO 2. Kohno et. al. investigated the transient current of a Si quantum dot floating gate MOS structure with tunnel gate oxide and showed a charging and discharging process in C-V characteristics with short retention time [7]. In our work, we fabricate a SiO 2 /nc-si/sio 2 sandwich structure. These structures rather differ from those obtained using Si + implantation or Si-rich film followed by annealing, where a wide distribution in space and size of dots would result in a large lateral current leakage and degrade the device performance [8,9]. The charging and discharging characteristics of the embedded dots were investigated by C-V and G-V methods and discussed in terms of charge loss in the dots. A hysteresis in the electrical characteristics obtained by C-V and G-V measurements was attributed to an electron trapped per nc-si dot. A modification of the electric field controlled by the stored charge in the dots is thought to be the cause for the longterm retention time in this device. A8.8.1

2 EXPERIMENTAL DETAILS The schematics of the MOS diodes with silicon nanocrystals and its transmission-electronmicrograph (TEM) are shown in Fig. 1. Al electrode Upper Oxide Si nanocrystal Tunneling Oxide n-type Si SiO 2 /nc-si/sio 2 Sandwich structure nc-si dot Al electrode (a) 100 nm (b) Si Substrate Figure 1. A SiO 2 /nc-si/sio 2 sandwich structure was prepared. a) The schematic of device structure. b) TEM image of sandwich structure The device fabrication process begins with the <100> n-type silicon wafer (1-10 Ω cm) after H 2 SO 4 /H 2 O 2 (30:70) and diluted HF solution cleaning process. First, an ultra-thin tunnel oxide was grown by H 2 SO 4 /H 2 O 2 (30:70) oxidization, which gave rise to a 2 nm oxide measured by ellipsometry and confirmed by cross section TEM image. Next, a layer of uniform nc-si dots with size of 8 nm and density of 1-2x10 11 /cm 2 was deposited by remote plasma-enhanced CVD (PECVD) technique [10]. Then a 60 nm of upper oxide was grown by TEOS PECVD method and the sample was annealed in N 2 ambient at 1100 o C, 1 hour. Aluminum electrodes for the front (100 µm in diameter) and the back sides were evaporated after etching away of the SiO 2 on the wafer backside, which reduced upper oxide thickness to 50 nm. Finally, the sample was annealed again in H 2 /N 2 ambient at 450 o C for 5 minutes, which improved the contact between metal and semiconductor or silicon dioxide and reduce the defect density in the devices. For comparison, samples without nc-si dots were also fabricated following the above processes. Scanning-electron-micrograph (SEM) and TEM were utilized to observe microstructures of the samples. The electrical properties of this sandwich structure device were measured by HP4156B precision semiconductor parameter analyser and HP 4284 A precision LCR meter at different temperatures. RESULTS According to low-resolution image (Fig. 1b), a layer of uniform nc-si dot is found to be apart from silicon surface at a constant distance (tunnel barrier), which differs from the devices where sandwiched dots have a wide space distribution in the gate oxide [8,9]. The hill-like surface contour on the upper SiO 2 corresponds with the nc-si dot underneath. A high-resolution cross-sectional TEM image of nc-si dots embedded in a matrix of SiO 2 is shown in Fig. 2. It clearly indicates that 8 nm nc-si dots were sandwiched between 2 nm tunnel oxide and 50 nm upper gate oxide. Sheet dot density of 1.4x10 11 /cm 2 was calculated according to the SEM A8.8.2

3 observation (not shown here). Based on SEM and TEM, the capacitor surface portion covered by Si dots is then about 10 %. Upper Oxide 50 nm 10 nm nc-si Dot 8 nm Tunnel Oxide 2.5 nm Si Substrate Figure 2. High-resolution TEM image of the sandwich structure. <111> spherical nc-si dot is seen clearly. C-V and G-V curves shown in Fig. 3 were obtained by sweeping the voltage between inversion and accumulation regions at room temperature. A positive shift was observed both in C-V and G-V curves. Capacitance (pf) x x x x x x x x x x Gate Bias (V) Figure 3. C-V and G-V curves obtained by sweeping gate bias from 5 V to 5 V and back to 5 V. The conductance peak position is around flat band voltage. Notable is the presence of one conductance peak, whose position is close to the flat-band voltage, in each forward and backward conductance measurements. Both of the voltage shifts in C-V (in flat band) and G-V (in peak position) are about 0.37 V. In contrast, unlike Fig. 3, no obvious hysteresis was observed in C-V curve or with the peak in G-V curve after the bias sweeping from negative voltage to positive voltage and back again for the samples without nc-si dots deposition. Therefore these hysteresis and peak should be attributed to electron traps in the sandwiched nc-si or at the interface on the nanocrystal dots but not in the oxide matrix. Moreover no distortions of C-V curve due to deep defect traps or large surface defect density, for example flat step, were found in our experiments with the change of temperature. And this hysteresis also cannot result from Fowler-Nordheim tunneling currents through the gate oxide of MOS capacitors, where the flat band shift is attributed to trapping of positive charges within the Conductance (S) A8.8.3

4 bulk of the oxide [11]. Further measurements also prove that this clockwise hysteresis is independent of the scan direction and speed (5 ~ 500 mv/s). It is worthwhile to note that no holes were trapped at the inversion state. For a better understanding of the high frequency C-V results, the frequency dependent capacitance has been investigated at room temperature. In frequency dependent measurements, we found similar clockwise C-V hysteresis and no significant change in peak position in G-V characteristics from 1 MHz to 1 khz, which indicate that hysteresis and conductance peak has the same origin. It also suggests that the hysteresis and peak are not from interface traps, which are generally time dependent, giving rise to time or frequency dependent C-V or G-V characteristics. That the interface states have little affect is supported by the observations that there is a very small temperature dependence on conductance and an absence of activation energy (~3 mev). These results will be reported elsewhere in detail. After electrons are trapped, at a reading voltage (e.g. flat band voltage in our experiments), the stored electrons have a possibility to tunnel back to the Si substrate because of perturbation, which could cause a shift in capacitance gradually. In the time dependent capacitance measurement, the memory retention time exceeding 5 hours (about 10 % dots lost their charge) was observed in this memory device at room temperature. Fig. 4 shows a time dependence of capacitance measured at a initial flat band voltage, which presents a logarithmic law. It suggests that the tunneling possibility is varied with time, as a constant probability would give an exponential law [12] Capacitnace (pf) Time (s) Figure 4. Time dependence of capacitance after electrons were stored in nc-si dots. Gate bias is at the initial flat band voltage, -1.2 V. DISCUSSION In our device, the Coulomb blockade effect can be very significant for the dimension of nc- Si of 8 nm. The Coulomb charging energy (q 2 /2C self ), where C self is the nc-si self capacitance embedded in SiO 2, is about 46 mev, which is not only greater than the thermal energy (26 mev at room temperature), but also limits additional capture of electrons into the nc-si dot. For our device, the extrinsic Debye length at room temperature is about 74.8 nm. Thus, with even a random distribution of dots in position, the screening efficiency is sufficient to maintain memory state of the device in spite of charge loss from some of the dots. A8.8.4

5 Based on our experimental results, at sufficient negative bias voltage (erase voltage), no electron resides in the nc-si dots. When bias is swept to the high positive value, some electrons will direct tunnel through the ultra-thin oxide and will be stored in nc-si dots, which results in the shift of capacitance as well as conductance characteristics. According to G-V measurements, these trap events begin from flat band condition to accumulation condition. The peak of conductance indicates one electron trap event and the two conductance mesas at each side of conductance peak show a self-limiting trap process due to Coulomb blockade effect. According to the fixed oxide charges inducing the shift of flat band voltage, the trap and /or nanocrystal density (D trap ) is estimated by formula as following [13] VFBC t ox upper + 0.5t dot Dtrap = (1) q ttotal where V FB is flat band voltage shift, C ox is the total oxide capacitance and q is elementary charge, t upper is the upper gate oxide, t dot is the nc-si dot diameter, and t total is the total thickness of sandwich structure, respectively. The estimated trap density is about 2x10 11 /cm 2, minus sign means the trap site is an electron acceptor, which has the same magnitude as the sheet density of dots in diode. Because in the experiments, only one conductance peak was observed in G-V curve, one electron is trapped in one nanocrystal is a reasonable conclusion within errors. We also can estimate the magnitude of flat band shift with the formula in reference [1]. T qndot 1 ε ox VFB = ( tupper + tdot ) (2) ε ox 2 ε Si where n dot is the density of the nc-si, ε ox and ε Si are permittivity of oxide and silicon, respectively. From this formula, V T FB is calculated to be 0.38 V for one electron per nanocrytal, which is in good agreement with the experimental V FB. Shi et. al. suggested that electrons should not reside in the conduction band but in deep traps of dot to explain the observed long-term retention behaviors [5]. According to the model, the retention time should be thermally activated at deep trap energy level. However, in their experiments the charge-loss rate only decreased slightly as temperature was decreased from 300 to 80 K. Our frequency and temperature dependent results also indicate that neither interface defect nor deep defect is dominant for the charging or discharging processes in our samples. According to the results in Fig. 4, the logarithmic shape involves a variation of the tunneling probability with time. A variation of the tunneling probability should come from a varied tunnel barrier. In our device, with a positive voltage on the gate that led Si surface into the accumulation condition, electrons were injected efficiently by direct tunneling from the conduction band of silicon substrate to the conduction band of nc-si dot. It is well known that the tunneling transparency depends on the electric field in the tunnel oxide [14]. When the bias is held at the initial flat-band voltage after dots charged, the electric field across the tunneling oxide layer can be ignored since the gate bias was fully screened by the charge in sandwich layers. After these dots were charged, then at the initial flat band voltage, some of the stored electrons will tunnel back to the substrate since an ultra-thin tunnel barrier and perturbation. Once some of these electrons tunnel back to substrate, the Si surface band would be bent down a little, because of the charge loss in the dot layer. An electric field from nc-si dot layer to Si substrate would be formed ( V/cm around nc-si dot estimated on one electron release from this dot), which would hinder discharging of other stored electrons. This built-in electric field could be changed with the stored charge in nc-si dots. Thus the tunneling probability would also be A8.8.5

6 changed with charge loss and with time. Therefore, this built-in field, created and controlled by charge loss in nc-si dots, will improve the retention time significantly. CONCLUSION We prepared a SiO 2 /nc-si/sio 2 sandwich structure memory device. Sensitive electrical measurements of C-V and G-V were utilized to investigate charge and discharge in nc-si dots. A clear positive shift in C-V and G-V curves due to electrons trapped in nc-si dots has been found. Moreover, one peak around flat band condition indicates a trap event of one electron stored per nc-si. Experiments show that neither interface defect nor deep defect is dominant for dot s charging and discharging processes. Retention time exceeding 5 hours and a logarithmic charge loss function were shown. A repulsive built-in electric field from nc-si dots to Si substrate created and controlled by charge loss in nc-si dots is taken into account to explain logarithmic charge loss and long-term retention time. ACKOWLEDGEMENTS The authors would like to thank Dr. K. Arai and J. Oomachi for their help for nc-si dots deposition processes. Funding was supported by grant-in-aid for Scientific Research from the Ministry of Education and by Core Research for Evolutional Science and Technology (CREST) program of the Japan Science and Technology Corporation (JST). REFERENCES 1. S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. Crabbé, and K. Chan, Appl. Phys. Lett. 68, 1377 (1996). 2. A. Dutta, Y. Hayafune and, S. Oda, Jpn. J. Appl. Phys. 39, 855 (2000). 3. L. J. Guo, E. Leobandung, and S. Y. Chou, Science (1997). 4. A. Nakajima, T. Futatsugi, K. Kosemura, T. Fukano, and N. Yokoyama, Appl. Phys. Lett. 70, 1742 (1997). 5. Y. Shi, K. Saito, H. Ishikuro, and T. Hiramoto, J. Appl. Phys. 84, 2358 (1998). 6. B. J. Hinds, T. Yamanaka, and S. Oda, J. Appl. Phys. 90, 6402 (2001). 7. A. Kohno, H. Murakami, M. Ikeda, S. Miyazaki, and M. Hirose: Ext. Abstr Int. Conf. Solid State Devices & Materials, Hiroshima, 1998, p Y. Kim, K. H. Park, T. H. Chung, H. J. Bark, and J. Y. Yi, Appl. Phys. Lett. 78, 934 (2001). 9. E. Kapetanakis, P. Normand, and D. Tsoukalas, Appl. Phys. Lett. 77, 3450 (2000). 10. T. Ifuku, M. Otobe, A. Itoh and, S. Oda, Jpn. J. Appl. Phys. 36, 4031 (1997). 11. M. Kerber, J. Appl. Phys. 74, 2125 (1993). 12. C. Busseret, A. Souifi, T. Baron and, G. Guillot, Supperlattices and Microstructures, 28, 493 (2000). 13. S. M. Sze, Physics of Semiconductor Devices, (New York, Wiley, 1981) Chap S. Fleischer, P. T. Lai, and Y. C. Cheng, J. Appl. Phys. 72, 5711 (1992). A8.8.6