Decoding A Counter. svbitec.wordpress.com 1
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1 ecoding A ounter ecoding a counter involves determining which state in the sequence the counter is in. ifferentiate between active-high and active-low decoding. Active-HIGH decoding: output HIGH if the counter is in the state concerned. Active-LOW decoding: output LOW if the counter is in the state concerned. svbitec.wordpress.com 1
2 ecoding A ounter Example: MO-8 ripple counter (active-high decoding). lock A' B' ' HIGH only on count of AB = 000 A' B' HIGH only on count of AB = 001 A' B ' A B. HIGH only on count of AB = 010 HIGH only on count of AB = 111 svbitec.wordpress.com 2
3 ecoding A ounter Example: To detect that a MO-8 counter is in state 0 (000) or state 1 (001). A' B' ' A' B' A' B' lock HIGH only on count of AB = 000 or AB = 001 Example: To detect that a MO-8 counter is in the odd states (states 1, 3, 5 or 7), simply use. lock HIGH only on count of odd states svbitec.wordpress.com 3
4 ounters with Parallel Load ounters could be augmented with parallel load capability for the following purposes: To start at a different state To count a different sequence As more sophisticated register with increment/decrement functionality. svbitec.wordpress.com 4
5 ounters with Parallel Load ifferent ways of getting a MO-6 counter: A 4 A 3 A 2 A 1 A 4 A 3 A 2 A 1 Load I 4 I 3 I 2 I 1 ount = 1 lear = 1 P lear I 4 I 3 I 2 I 1 ount = 1 Load = 0 P Inputs = 0 (a) Binary states 0,1,2,3,4,5. Inputs have no effect (b) Binary states 0,1,2,3,4,5. A 4 A 3 A 2 A 1 A 4 A 3 A 2 A 1 arry-out Load I 4 I 3 I 2 I 1 ount = 1 lear = 1 P Load I 4 I 3 I 2 I 1 ount = 1 lear = 1 P (c) Binary states 10,11,12,13,14,15. (d) Binary states 3,4,5,6,7,8. svbitec.wordpress.com 5
6 ounters with Parallel Load 4-bit counter with parallel load. lear P Load ount Function 0 X X X lear to 0 1 X 0 0 No change 1 1 X Load inputs Next state svbitec.wordpress.com 6
7 Introduction: Registers An n-bit register has a group of n flip-flops and some logic gates and is capable of storing n bits of information. The flip-flops store the information while the gates control when and how new information is transferred into the register. Some functions of register: retrieve data from register store/load new data into register (serial or parallel) shift the data within register (left or right) svbitec.wordpress.com 7
8 Simple Registers No external gates. Example: A 4-bit register. A new 4-bit data is loaded every clock cycle. A 3 A 2 A 1 A 0 P I 3 I 2 I 1 I 0 svbitec.wordpress.com 8
9 Registers With Parallel Load Instead of loading the register at every clock pulse, we may want to control when to load. Loading a register: transfer new information into the register. Requires a load control input. Parallel loading: all bits are loaded simultaneously. svbitec.wordpress.com 9
10 Registers With Parallel Load Load Load'.A 0 + Load. I 0 A 0 I 0 A 1 I 1 A 2 I 2 A 3 I 3 LK LEAR svbitec.wordpress.com 10
11 Using Registers to implement Sequential ircuits A sequential circuit may consist of a register (memory) and a combinational circuit. Next-state value lock Register Inputs ombinational circuit Outputs The external inputs and present states of the register determine the next states of the register and the external outputs, through the combinational circuit. The combinational circuit may be implemented by any of the methods covered in MSI components and Programmable Logic evices. svbitec.wordpress.com 11
12 Using Registers to implement Sequential ircuits Example 1: A 1+ = S m(4,6) = A 1.x' A 2+ = S m(1,2,5,6) = A 2.x' + A 2 '.x = A 2 x y = S m(3,7) = A 2.x Present Next state Input State Output A 1 A 2 x + A 1 + A 2 y A 1.x' A 2 x x A 1 A 2 y svbitec.wordpress.com 12
13 Using Registers to implement Sequential ircuits Example 2: Repeat example 1, but use a ROM. Address Outputs x A 1 A 2 8 x 3 ROM y ROM truth table svbitec.wordpress.com 13
14 Shift Registers Another function of a register, besides storage, is to provide for data movements. Each stage (flip-flop) in a shift register represents one bit of storage, and the shifting capability of a register permits the movement of data from stage to stage within the register, or into or out of the register upon application of clock pulses. svbitec.wordpress.com 14
15 Shift Registers Basic data movement in shift registers (four bits are used for illustration). ata in ata out ata out ata in (a) Serial in/shift right/serial out (b) Serial in/shift left/serial out ata in ata in ata in ata out (c) Parallel in/serial out ata out (d) Serial in/parallel out ata out (e) Parallel in / parallel out (f) Rotate right (g) Rotate left svbitec.wordpress.com 15
16 Serial In/Serial Out Shift Registers Accepts data serially one bit at a time and also produces output serially. Serial data input Serial data output LK svbitec.wordpress.com 16
17 Serial In/Serial Out Shift Registers Application: Serial transfer of data from one register to another. SI Shift register A SO SI Shift register B SO lock Shift control P lock Shift control P Wordtime T 1 T 2 T 3 T 4 svbitec.wordpress.com 17
18 Serial In/Serial Out Shift Registers Serial-transfer example. Timing Pulse Shift register A Shift register B Serial output of B Initial value After T After T After T After T svbitec.wordpress.com 18
19 Serial In/Parallel Out Shift Registers Accepts data serially. Outputs of all stages are available simultaneously. ata input LK ata input LK SRG 4 Logic symbol svbitec.wordpress.com 19
20 Parallel In/Serial Out Shift Registers Bits are entered simultaneously, but output is serial. ata input SHIFT/LOA Serial data out LK SHIFT. 0 + SHIFT'. 1 svbitec.wordpress.com 20
21 Parallel In/Serial Out Shift Registers Bits are entered simultaneously, but output is serial. ata in SHIFT/LOA LK SRG 4 Serial data out Logic symbol svbitec.wordpress.com 21
22 Parallel In/Parallel Out Shift Registers Simultaneous input and output of all data bits. Parallel data inputs LK Parallel data outputs svbitec.wordpress.com 22
23 Bidirectional Shift Registers ata can be shifted either left or right, using a control line RIGHT/LEFT (or simply RIGHT) to indicate the direction. RIGHT/LEFT Serial data in RIGHT. 0 + RIGHT' LK 0 svbitec.wordpress.com 23
24 Bidirectional Shift Registers 4-bit bidirectional shift register with parallel load. Parallel outputs A 4 A 3 A 2 A 1 lear LK s 1 4x1 s MUX x1 MUX x1 MUX x1 MUX Serial input for shift-right I 4 I 3 I 2 I 1 Serial input for shift-left Parallel inputs svbitec.wordpress.com 24
25 Bidirectional Shift Registers 4-bit bidirectional shift register with parallel load. Mode ontrol s 1 s 0 Register Operation 0 0 No change 0 1 Shift right 1 0 Shift left 1 1 Parallel load svbitec.wordpress.com 25
26 An Application Serial Addition Most operations in digital computers are done in parallel. Serial operations are slower but require less equipment. A serial adder is shown below. A A + B. Shift-right P SI Shift-register A SO x y z FA S External input SI Shift-register B SO lear svbitec.wordpress.com 26
27 An Application Serial Addition A = 0100; B = A + B = 1011 is stored in A after 4 clock pulses. Initial: A: B: : 0 Step 1: S = 1, = 0 Step 2: S = 1, = 0 Step 3: S = 0, = 1 Step 4: S = 1, = 0 A: B: x A: B: x x 0 1 A: B: x x x 0 A: B: x x x x : 0 : 0 : 1 : 0 svbitec.wordpress.com 27
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