New Metrics for the Reliability of Approximate and Probabilistic Adders

Transcription

1 IEEE TRANSACTIONS ON COMPUTERS, TC New Metrics for the Reliability of Approximate and Probabilistic Adders Jinghang Liang, Student Member, Jie Han, Member, Fabrizio Lombardi, Fellow IEEE Abstract Addition is a fundamental function in arithmetic operation; several adder designs have been proposed for implementations in inexact computing. These adders show different operational profiles; some of them are approximate in nature while others rely on probabilistic features of nanoscale circuits. However, there has been a lack of appropriate metrics to evaluate the efficacy of various inexact designs. In this paper, new metrics are proposed for evaluating the reliability as well as the power efficiency of approximate and probabilistic adders. Reliability is analyzed using the so-called sequential probability transition matrices (SPTMs). Error distance (ED) is initially defined as the arithmetic distance between an erroneous output and the correct output for a given input. The mean error distance (MED) and normalized error distance (NED) are then proposed as unified figures that consider the averaging effect of multiple inputs and the normalization of multiple-bit adders. It is shown that the MED is an effective metric for measuring the implementation accuracy of a multiple-bit adder and that the NED is a nearly invariant metric independent of the size of an adder. The MED is, therefore, useful in assessing the effectiveness of an approximate or probabilistic adder implementation, while the NED is useful in characterizing the reliability of a specific design. Since inexact adders are often used for saving power, the product of power and NED is further utilized for evaluating the tradeoffs between power consumption and precision. Although illustrated using adders, the proposed metrics are potentially useful in assessing other arithmetic circuit designs for applications of inexact computing. Index Terms Adders, Inexact computing, Reliability, Error masking, Approximate logic, Imprecise arithmetic, Mean error distance, Normalized error distance, Power, Energy efficiency. J. Liang and J. Han are with the Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada T6G 2V4. ( jinghang@ualberta.ca, jhan8@ualberta.ca) F. Lombardi is with the Department of Electrical and Computer Engineering, Northeastern University, Boston, USA. ( lombardi@ece.neu.edu) Manuscript received Dec. 11, xxxx-xxxx/0x/$xx x IEEE 1 INTRODUCTION ethodologies for inexact (or soft) computing rely on Mthe feature that many applications can tolerate some loss of precision and therefore, the solution can tolerate some degree of uncertainty [1-3]. Deterministic, explicit, and precise models and algorithms are not always suitable to solve these types of problems. However, inexact computing applications are mostly implemented using digital binary logic circuits, thus operating with a high degree of predictability and precision. A framework based on a precise and specific implementation can still be used with a methodology that intrinsically has a lower degree of precision and an increasing uncertainty in operation. While this may be viewed as a potential conflict, such an approach tailors the significant advantage of inexact computing (and its inherent tolerance to some imprecision and uncertainty) to a technology platform implemented by conventional digital logic and systems. The paradigm of inexact computation relies on relaxing fully precise and completely deterministic building blocks (such as a full adder) when for example, implementing bio-inspired systems. This allows nature inspired computation to redirect the existing design process of digital circuits and systems by taking advantage of a decrease in complexity and cost with possibly a potential increase in performance and power efficiency. In imprecise computation, however, traditional measures for performance, power and reliability are often conflicting, so new figures of merit for assessing the tradeoffs involved in such design process are needed to better understand the operation of approximate/probabilistic circuits. One of the fundamental arithmetic operations in many applications of inexact computing is addition [4, 5]. Soft additions are generally based on the operation of deterministic approximate logic or probabilistic imprecise arithmetic (categorized in [6] as design-time and run-time techniques). Several recently proposed adder architectures are representatives of these types. The bio-inspired lower-part OR adder (LOA) [7] is based on approximate logic, whose truth table is slightly different from the original truth table of a full adder. The approximate mirror adders (AMAs) proposed in [8] save power by reducing the number of transistors in a mirror adder design. The use of these architectures results in approximations to the addition, making it deterministically different from the precise operational outcome. Another design is known as the probabilistic full adder (PFA) [9, 10]; its implementation is based on probabilistic CMOS, a technology platform for modeling the behavior of nanometric designs as well as reducing power consumption. In light of these advances, design metrics are urgently needed to evaluate the effectiveness of the architectures; as shown in latter sections, the traditional metric of reliability (defined as the probability of system survival) is not appropriate for use in evaluating approximate designs. Moreover, it is useful to have a design metric with no dependency on the number of operands in an addition. The objective of this paper is to propose new metrics for

2 2 IEEE TRANSACTIONS ON COMPUTERS, TC assessing adder designs with respect to reliability and power efficiency for inexact computing. A new figure of merit referred to as error distance (ED) is initially proposed to characterize the reliability of an output of an adder. ED is then used to obtain two new metrics: the mean error distance (MED) and the normalized error distance (NED). The MED and NED can be obtained using sequential probability transition matrices (SPTMs) and are able to evaluate the reliability of both probabilistic and deterministic adders. It is shown that the MED is an effective metric in evaluating the implementation of a multiple-bit adder. The NED is a stable metric that is almost independent of the size of an implementation; this feature brings a new perspective for the evaluation and comparison of different adder designs. The power and NED product is further used to evaluate the power and precision tradeoff. An adder implementation with reduced precision, referred to as the lower-bit ignored adder (LIA), is investigated as a baseline design for assessing the LOA, AMAs and PFAs. A detailed analysis and simulation results are presented to assess the reliable performance of these adders using the proposed new metrics. Some preliminary results of this work have been previously presented in [11]; [11] introduced the concepts of ED and MED and presented a comparative study of reliability and static power for the LOA, PFAs and LIA. This paper is a significant extension of [11] and includes the following novel contributions: The recently proposed approximate mirror adders (AMAs) as transistor-level designs are considered and included in the analysis of the proposed metrics. The notion of sequential probability transition matrices (SPTMs), as well as their formulation, is presented in detail as a framework for evaluating the reliability of sequential circuits. A normalized error distance (NED) is proposed; as a nearly invariant metric, the NED is almost independent of the size of an adder implementation, so it is an important metric for characterizing the reliability of an approximate or probabilistic design. The product of power and NED is proposed to quantitatively evaluate the tradeoff of power and precision. Moreover, the power saving and NED ratio is used in the analysis of the efficiency of a design when trading off precision for power. The rest of the paper is organized as follows. Section 2 contains a review and Section 3 presents sequential probability transition matrices (SPTMs). Section 4 presents the notion of error distance (ED) and the evaluations of mean error distance (MED) and normalized error distance (NED). Section 5 discusses the power and precision tradeoff. Section 6 concludes the paper. 2 REVIEW In most digital systems, sequential circuits are utilized, so this paper primarily deals with sequential adders. A sequential adder, as the one shown in Fig. 1, consists of a k-bit full adder concatenated with a k-bit register. In this section, different implementations of a full adder are reviewed; particular emphasis is devoted to features relevant to soft and inexact computing. Fig. 1. A k-bit sequential adder. 2.1 Conventional Full Adder (CFA) Fig. 2 shows a one-bit (precise) conventional full adder (CFA); the CFA is commonly connected in a ripple-carry implementation, i.e., by cascading the circuit of Fig. 2 in a linear array. A B Cin S Cout Fig. 2. A one-bit conventional full adder (CFA). 2.2 Lower-Part-OR Adder (LOA) Fig. 3. Hardware structure of the lower-part-or adder (LOA) [7]. Differently from conventional designs that strictly operate according to the exact function (as defined by its truth table), an approximate logic implementation alters some entries in the truth table. This feature allows balancing precision with other performance metrics. The recently proposed LOA is based on such a design [7]. A LOA divides a k-bit addition into two smaller parts, i.e., two modules of m-bits and n bits. As shown in Fig. 3, the m- bit module of a LOA uses a smaller but precise adder (referred to as the sub-adder) to compute the exact values of the m most significant bits of the result (also referred to as the upper part). Additional OR gates are used to approximately compute the n least significant bits (also referred to as the lower part) of the sum by applying a bitwise OR operation on the respective input bits. An additional AND gate is used to generate the carry-in for the precise

3 LIANG ET AL.: NEW METRICS FOR THE RELIABILITY OF APPROXIMATE AND PROBABILISTIC ADDERS 3 sub-adder when the most significant bits of both the lower-part inputs are 1. As this implementation ignores the trivial carries in the lower part of the LOA adder, it may result in a loss of precision. Albeit using different structures, the approximate adder designs in [12] and [13] belong to the same category. 2.3 Approximate Mirror Adder (AMA) A Mirror Adder (MA) is not based on the complementary structure of CMOS logic. It is based on a special arrangement of the transistors and is yet another common design for implementing conventional adders. When approximate logic is applied to the MA cells, approaches such as IMPACT [8] have been reported to tradeoff precision for power and area. Three implementations of an approximate mirror adder (AMA) are proposed in [8] by removing different numbers of transistors. The truth table of these three approximate implementations is shown in Table 1. Similarly, AMAs can be used in the least significant n-bit (or the lower part) of an approximate sequential adder. TABLE 1. TRUTH TABLE OF CONVENTIONAL MIRROR ADDER AND ITS APPROXIMATE IMPLEMENTATIONS [8]; ENCLOSED ENTRIES INDICATE INCORRECT OUTPUTS. Inputs Accurate AMA1 AMA2 AMA3 Cout Sum Cout Sum Cout Sum Cout Sum Probabilistic Full Adder (PFA) Probabilistic CMOS (PCMOS) is a technique for achieving savings in power consumption, while balancing performance at nanometric ranges. In a k-bit PFA, the most significant m-bit adders are implemented using perfectly reliable (and thus deterministic) gates, while the least significant n bits are implemented in PCMOS. Although new adder architectures have been proposed to optimize the use of PCMOS technology [14], probabilistic implementations of a conventional full adder are considered in this work. The structure of this type of adder is shown in Fig SEQUENTIAL PROBABILITY TRANSITION MATRICES 3.1 Definitions Prior to presenting the analysis, several definitions are first introduced. In a probabilistic design, the signal probability is defined as the probability of a signal being logical 1. An error may occur to the function of a gate and the probability of this occurrence is given by a gate error rate (or probability). Unless otherwise noted, the von Neumann type of error (i.e., flipping the correct signal) is considered in this paper. In a combinational circuit, the output probability for a specific input vector i is defined as the joint probability that all of the outputs are 1 when the input vector is i. Any output that deviates from the correct value due to the effect of errors, is considered as a faulty output. The output reliability for input i is defined as the joint probability that all outputs are correct for i. This definition of reliability considers the correlation among signals and is therefore used in this paper. Circuit reliability is defined as the average output reliability over all applicable input vectors. In an approximate design, the operation is deterministic and a faulty output is due to a functional approximation. This deterministic as well as the aforementioned probabilistic behavior can analytically be assessed for circuit reliability using the so-called sequential probability transition matrices (SPTMs), as presented next. 3.2 Probabilistic Transfer Matrices (PTMs) The PTM approach represents a computational framework for the evaluation of circuit reliability in the presence of both deterministic and probabilistic errors [15]. A PTM is a matrix, in which the (i, j) th entry represents the conditional probability of the output vector of value j, determined by the circuit structure for the input vector i. Since a fault-free circuit has correct outputs with probability 1, it has an ideal transfer matrix (ITM), in which an entry is either 0 or 1. A two-input NAND gate s ITM and PTM are shown in Fig. 5. (a) (b) (c) Fig. 5. An ITM and PTM for a two-input NAND gate: (a) a twoinput NAND gate, (b) ITM of the NAND gate, (c) PTM of the NAND gate (the gate has a probability of 1-p to produce an error). Fig. 4. Hardware structure of the probabilistic full adder (PFA). A circuit PTM can be obtained by combining the gate PTMs using simple rules of matrix operations and the connectivity of the gates. Matrix multiplications are used for gates connected in series, while tensor products are used for gates connected in parallel. Special PTMs and ITMs are constructed for fanouts, interconnects and

4 4 IEEE TRANSACTIONS ON COMPUTERS, TC swapping of wires by taking into account their topologies. Since signal representation and propagation are incorporated into the formulation of PTMs, a circuit PTM contains accurate and comprehensive information about the probabilistic behavior of a circuit. A PTM can also be extended to account for more complex circuit structures. In [16], PTMs are used to investigate the effects of soft errors in sequential circuits. In this paper, sequential PTMs (SPTMs) are defined and a detailed formulation is presented by considering the topology and structure of sequential circuits for reliability evaluation. 3.3 Formulation of Sequential PTMs (SPTMs) M Primary Inputs N Present States { Combinational } Logic { } Flip-Flops Fig. 6. Mealy model of a sequential circuit. K Primary Outputs N Next States Consider a general Mealy model of a sequential circuit (Fig. 6). In this circuit, there are M+N inputs: M of them are Primary Inputs and the remaining N inputs are Present States (i.e., the feedback signals from the flip-flops). There are also K+N outputs: K of them are Primary Outputs, while the remaining N outputs are Next States, which will be stored in the flip-flops and then fed back into the inputs during the next clock cycle. For this circuit, SPTMs define several matrices mapping from the M+N inputs to the N next states (denoted by Φ ns ) and to the K primary outputs (denoted by Φ po ), also from the N next states to the N present states. In the SPTM Φ ns, the entries denote the transition probabilities from the 2 M+N input combinations to the 2 N next states. Φ ns is therefore a 2 M+N 2 N matrix, given by Φ ns p(0 0) p(1 0) p(j 0) p(2 N 1 0) p(0 1) p(1 1) p(j 1) p(2 N 1 1) = p(0 i) p(1 i) p(j i) p(2 N 1 i) p(0 2 M+N 1) p(1 2 M+N 1) p(j 2 M+N 1) p(2 N 1 2 M+N 1) (1) where p(j i) represents the conditional transition probability that the next state has the j th value, given that the inputs have the i th value. Similarly, the entries in Φ po are given by the transition probabilities from the 2 M+N input combinations to the 2 K primary output combinations. Furthermore, the circuit SPTM Φ c is defined for the mappings between the M+N inputs and the K+N outputs. In the likely circuit scenario, the primary outputs and the next states are correlated due to the fanouts of signals to both the primary inputs and the next states (an example is evident in the half adder circuit of Fig. 7). So, Φ c, like any other SPTM, can be obtained in a similar way as the combinational PTMs, i.e. by combining the gate PTMs following the matrix operation rules and the connectivity of the gates in a circuit. If the flip-flops are also subject to errors, the SPTM Φ ff must be defined. For a single flip-flop with an error rate of ε, its SPTM Φ 1 ff is given by Φ 1 ff = 1 ε ε. (2) ε 1 ε For N independent flip-flops, the SPTM Φ ff is obtained as Φ ff = Φ N 1 ff, (3) i.e., Φ ff is the Nth tensor product of Φ 1 ff. Its entries are the transition probabilities from the 2 N input combinations and the 2 N output combinations of the flip-flops. At time t, the primary-input vector is given by P pi (t) = (P pi (0, t), P pi (1, t),, P pi (2 M 1), t, (4) where P pi (i, t) is the probability that the primary inputs have the i th value at time t. The present-state vector is given by P ps (t) = (P ps (0, t), P ps (1, t),, P ps (2 M 1), t, (5) where P ps (i, t) is the probability that the present states have the i th value at time t. Therefore inputs can be represented by a vector of length 2 M+N given by P in (t) = P pi (t) P ps (t), (6) where indicates the tensor product. For the N next states, their joint distribution is described by a vector P ns (t) of length 2 N, and P ns (t) = P in (t) Φ ns. (7) The present-state vector at time t+1, P ps (t + 1), can be calculated as follows: P ps (t + 1) = P ns (t) Φ ff. (8) Similarly, the primary-output vector P po (t) is given by P po (t) = P in (t) Φ po. (9) 3.4 Reliability evaluation using SPTMs In a sequential circuit, the cumulative effect of errors is modeled by matrix operations (as according to the Markov process); specifically, error propagation is described by matrix multiplications, while the combination of signals is described by tensor products. By considering the SPTMs defined previously for the sequential circuit of Fig. 6, the input vector at time t+1, P in (t + 1), can be computed by P in (t + 1) = P pi (t + 1) P ps (t + 1) = P pi (t + 1) P in (t) Φ ns Φ ff. (10) It can be shown that P in (t + 1) = P in (t) P pi (t + 1) (Φ ns Φ ff ), (11) as per the Theorem in the Appendix. Let Φ in (t) = P pi (t + 1) (Φ ns Φ ff ), (12) (11) can be written as P in (t + 1) = P in (t) Φ in (t). (13) Φ in (t) is a time-dependent SPTM, whose entries are the transition probabilities from the 2 M+N input combina-

5 LIANG ET AL.: NEW METRICS FOR THE RELIABILITY OF APPROXIMATE AND PROBABILISTIC ADDERS 5 tions at time t to the 2 M+N input combinations at time t+1. Therefore, (13) describes the (error) characteristics of the sequential circuit (under its current primary inputs) and captures the temporal correlation between the inputs at different time steps. At time t+1, the primary output vector can now be computed as P po (t + 1) = P in (t + 1) Φ po = P in (t) Φ in (t) Φ po = P in (t 1) Φ in (t 1) Φ in (t) Φ po = = P in (t k) Φ in (t k) Φ in (t k + 1) Φ in (t 1) Φ po = = P in (0) Φ in (0) Φ in (1) Φ in (t 1) Φ po t = P in (0) ( k=0 Φ in (k)) Φ po. (14) Furthermore, assume that in the error-free case, the ideal output vector is given by I po (t + 1); so if the primary inputs at every time step and the initial state are known, the output reliability of a sequential circuit at time t+1 can be computed by: R po (t + 1) = P po (t + 1) I po (t + 1), (15) i.e., by the dot product of the two vectors. Example: Consider the sequential half adder circuit shown in Fig. 7. Given the gate PTMs, the circuit PTM can be found by first dividing the combinational part of the circuit into several levels and then evaluating the PTMs at each level. Alternatively, Φ ns and Φ po can be obtained for the next state and output logic. P in (0) = P pi (0) P ps (0) = (0.0495, , , ). (19) At t=1, the present-state vector is given by P ps (1) = P ns (0) Φ ff = P in (0) Φ ns Φ ff = (0.0851, ). (20) If the primary input vector at t=1 is given by P pi (1) = (0.98, 0.02), then the input vector P in (1) is given by P in (1) = P pi (1) P ps (1) = (0.0834, , , ). (21) The primary output vector is then obtained as P po (1) = P in (1) Φ po = ( ). (22) (22) gives the output distribution after one clock cycle for the probabilistic sequential adder. The above process can also be computed directly from (14) for t=0. Since the ideal error-free output vector is I po (1) = (1, 0), it can be obtained that R po (1) = P po (1) I po (1) = , (23) i.e., the output reliability at this time is Table 2 shows the simulation results of some sequential circuits obtained using the SPTM approach. Albeit with an exponential complexity, the SPTM approach produces accurate evaluation results. Alternatively, the reliability can be evaluated using probabilistic gate models [17] or stochastic computational models [18]. As can be seen in Table 2, the reliability values are very different at different clock cycles (denoted by T ) for the probabilistic and approximate designs. For example, for the LOA and AMAs, the reliability is mostly 0, which indicates that these designs are totally unreliable. However, they can be useful in many applications, where a partial loss of precision can be tolerated. Therefore, these new paradigms need to be better assessed as efficient design alternatives. Toward this end, new metrics are proposed subsequently to characterize the extent of loss of precision and its gain in reducing power consumption. 4 MEAN AND NORMALIZED ERROR DISTANCES Fig. 7. SPTM evaluation of a sequential half adder with one primary input, one flip-flop and one primary output. Assume a gate error rate of 0.01, we obtain Φ po = , 0.01 (16) and Φ ns = (17) Also assume that the flip-flop has an error rate of 0.02, i.e., ε = 0.02, then Φ ff = Φ 1 ff =. (18) Given the primary input at each time step, the reliability of the primary output can be calculated as follows. Let the initial state of the flip-flop be P ps (0) = (0.99, 0.01). If the primary-input vector is given by P pi (0) = (0.05, 0.95), then at t=0, the input vector can be calculated as 4.1 Error Distance In this section, a new metric is proposed for evaluating the reliability of an adder and SPTMs are used in the computation of this metric. Consider as an example the case in which the exact output Sum of an adder is and other values can result as inexact outputs. For example, both and represent inexact values. However, these two output values have different implications when compared to the correct value: means the output is different by 1 (or at a distance of 1) from the correct value, while is different by 16 (or at a distance of 16) from the correct value. So, an output can take erroneous values that are substantially different from the correct one. This is determined by the error effects on the addition; for example, a lower bit error has less impact on the output of an adder.

6 6 IEEE TRANSACTIONS ON COMPUTERS, TC TABLE 2. THE RELIABILITY OF SOME SEQUENTIAL CIRCUITS OBTAINED USING SPTMS. THE INPUT VECTOR IS RANDOMLY GENERATED AT EACH CLOCK CYCLE, DENOTED BY T. Circuits Characteristics Reliability (ε=0.005) Gates Inputs Outputs DFFs T=1 T=2 T=3 T=4 T=5 2-bit counter Simplified semaphore s bit probabilistic sequential adder bit Lower-part OR sequential adder bit AMA1 based sequential adder 22 (transistors) bit AMA2 based sequential adder 22 (transistors) bit AMA3 based sequential adder N/A Under these circumstances, the metric of circuit reliability has limited usefulness in assessing an adder, because it considers only the presence of an error, but not the error s implication on the performed addition. A new metric referred to as error distance (ED) is therefore proposed to better characterize the reliability of an adder. In general, the ED between two binary numbers, a (erroneous) and b (correct, i.e., golden), is defined as the arithmetic distance between these two numbers, i.e., ED(a, b) = a b = i a[i] 2 i j b[j] 2 j, (24) where i and j are the indices for the bits in a and b, respectively. In the previous example, the two erroneous values and have an ED of 1 and 16 to the golden , respectively. For a non-deterministic implementation, the output is probabilistic and usually follows a distribution for a given input a i. In this case, the ED of the output (denoted by d i ) is defined as the weighted average of EDs of all possible outputs to the nominal output. Assume that for a given input, the output has a nominal value b, but it can take any value given in a set of vectors b j (1 j r); the ED of the output is then given by: d i = j ED(b j, b) p j, (25) where p j is the output probability of b j (1 j r). 4.2 Mean Error Distance (MED) When the primary inputs to a circuit are nondeterministic and thus each input occurs at certain probability, the mean error distance (MED) of a circuit (denoted by d m ) is defined as the mean value of the EDs of all possible outputs for each input. Assume that the input is given by a set of vectors a i (1 i s) and that each vector occurs with a probability q i (1 i s). Then, the MED of the circuit is given by: d m = i d i q i, (26) where d i is the ED of the outputs for input a i (1 i s), which can be computed by (25). For simplicity, uniformly-distributed random inputs are considered hereafter, i.e., each input occurs with the same probability. Consider as an example a 3-bit adder. In Figs. 3 and 4, let k = 3, m = 1 and n = 2. A 3-bit CFA is used to calculate the correct output value. A gate error rate of is used for PFA; this value is selected such that the MED is close to that of the LOA (as shown in subsequent sections). Table 3 shows the results of three experiments, each of which consists of four consecutive clock cycles. As expected, the CFA has a MED of 0 throughout the four clock cycles in all experiments. However, the MED for the PFA is significantly greater than that of its LOA counterpart in most cases. Also shown is that the MEDs of the LOA and AMAs can be reduced to 0 at an intermediate time step. For example, the MED of the LOA has a value of 0 at both Clk1 and Clk4 in Experiment 3; this is due to the effect of error masking, as discussed next. TABLE 3. MEAN ERROR DISTANCE FOR FOUR CLOCK CYCLES WITH RANDOM INPUTS. Experiment Architecture Clk1 Clk2 Clk3 Clk4 CFA PFA No. 1 LOA AMA AMA AMA CFA PFA No. 2 LOA AMA AMA AMA CFA PFA No. 3 LOA AMA AMA AMA For uniformly distributed inputs, the 16 input values occur with the same probability of 1/16 for this 3-bit adder. Based on the SPTM model, the transition matrix Φ ns for the lower two bits is given in Fig. 8 for each implementation (as the higher bits are accurate and are therefore the same). Given these transition matrices, the ED of an output can be computed for an input against the corresponding output of the CFA (taken as the golden value). Given Φ LOA in Fig. 8(b), for example, the MED of the LOA is: d m,loa = 1 ( ) = (27) The MED of the PFA is calculated using Φ PFA in Fig. 8(f) as: d m,pfa = 1 d 16 i i = (28)

7 LIANG ET AL.: NEW METRICS FOR THE RELIABILITY OF APPROXIMATE AND PROBABILISTIC ADDERS 7 (a) (d) (b) (e) (c) (f)

8 8 IEEE TRANSACTIONS ON COMPUTERS, TC Fig. 8. The SPTM Φ ns for the two lower bits of the 3-bit adder: (a) CFA (b) LOA (c) AMA1 (d) AMA2 (e) AMA3 and (f) PFA. Each row corresponds to an input consisting of two bits from the primary inputs and two bits from the feedbacks; each column corresponds to a 3-bit output of the 2-bit addition. An entry in a matrix indicates a transition (probability) from an input to an output. Similarly, the MEDs of the AMAs are obtained as follows: d m,ama1 = 1 16 ( ) = 1.125, (29) d m,ama2 = 1 16 ( ) = 1, (30) d m,ama3 = 1 16 ( ) = 1. (31) This shows that the AMA1 has the largest MED, while the MED of the PFA (0.6167) is only slightly different from that of the LOA for an error rate of However, the cumulated error distances are quite different in the sequential adders, as shown in Table 2. This is mainly due to a result of partial error masking [19]. For the LOA and AMA2, several so-called restoring inputs are found, as indicated by the neighboring 1 s in the columns of Φ LOA and Φ AMA2. By these inputs, errors are logically masked, which leads to the same next state from different present states. This can also be explained as follows. For certain primary inputs, the approximate logic masks the cumulative errors in the LOA and AMA2. However, this is not the case for the PFA (or CFA), because it is always affected by errors; therefore, errors accumulate rather than being masked. 4.3 Mean Error Distance (MED) Evaluation In this section, the MEDs of the various designs are evaluated against a baseline design of a reduced precision adder, i.e., the lower-bit ignored adder (LIA). In this implementation, rather than using n-bit unreliable adders for computation, the lower significant bits are ignored. Consider the general case of a 32-bit adder (k=32). Fig. 9(a) shows the reliability of each adder design, while the MEDs are plotted in Fig. 9(b) by varying the number of lower bits, n. A comparison of the adder implementations shows that the interpretation of these metrics (i.e., reliability and MED) leads to a different assessment result; for example under the MED metric, the performance of LOA is similar to a PFA with a gate error rate of However, under the reliability metric the reliability of LOA is significantly lower than the reliability of PFA for the same gate error rate. As shown in Fig. 9(b), an n-bit ignored LIA performs slightly better in terms of the MED than an n-bit PFA at a gate error rate of 0.2 for the 32-bit adder. However, a PFA with an error rate significantly lower than 0.2 is expected to have a smaller MED. The AMAs have a similar performance as a PFA with an error rate of approximately Moreover, as shown in Fig. 9(b), the expected MEDs of both the LOA and the PFA increase exponentially with the number of lower bits. For the LOA, error masking occurs when the carry bit is ignored - there is no carry for the lower bits. Therefore, errors in a lower bit are operationally isolated. In this way, error masking occurs in the combinational circuit. Therefore, errors in the lower bits cannot be propagated to the higher bits, thus preventing their cumulative effect. The simulation results of Fig. 9 show the effectiveness of the proposed evaluation technique. It reveals that, although there is no cumulative error for the LOA, an error due to the approximate logic makes its MED not as optimistic as expected, especially for an increased number of lower bits. This is due to the fact that an error can occur in the most significant lower bit. The PFA shows a different scenario. Errors in the lower bits are likely to be propagated to the higher bits. So, its MED is rather large even for a small error rate, due to the cumulative errors from the lower bits (even though the error that results from the most significant bit is not that large). (b) Fig. 9. (a) Reliability vs. the number of lower bits in a 32-bit adder, and (b) MED vs. the number of lower bits in the 32-bit adder. 4.4 Normalized Error Distance (NED) and its Evaluation It is shown that in Fig. 9(b), the MED increases expo- (a)

9 LIANG ET AL.: NEW METRICS FOR THE RELIABILITY OF APPROXIMATE AND PROBABILISTIC ADDERS 9 nentially with the number of lower bits in an adder. Therefore, MED is an unfair metric when a comparison is made between two adders with different lower bits, as the maximum value of error that can be effectively reached, has also changed. To overcome this limitation, a normalized MED, referred to as a normalized error distance (NED), is defined as follows: d n = d m D, (32) where d m is the MED and D is the maximum value of error that an unreliable adder can have. This maximum value is usually 2 n for n lower bits, so we obtain d n = d m 2 n. (33) Fig. 10. Normalized Error Distance (NED) vs. the number of lower bits. Fig. 10 shows the NEDs of the various adder implementations. The NEDs of the LIA are constant at 0.5 and thus serving as a baseline. For other implementations, as revealed in the figure, the NED shows little change and only fluctuates in a small interval when different lower bits are compared. This is consistent with the results in Fig. 9(b), i.e., the MED increases exponentially with the number of lower bits. Therefore, NED is a stable metric that is almost independent of the size of an implementation and is useful in assessing the reliability of a specific design. This feature also brings a new perspective for the evaluation and comparison of different adder designs for inexact computing. However, it should be noted that the MED is very useful in evaluating adder implementations of different size. For example, a different number of lower bits can be implemented in approximate or probabilistic adders, as discussed previously. So, the MED is best suited for evaluating the effectiveness of an implementation of multiplebit adders. 5 POWER AND PRECISION TRADE-OFF As discussed previously, inexact computing is confronted with many similarities and often contradictory features that can also be found in bio-inspired systems, i.e., systems made of a large number of unreliable modules. These systems utilize extensive networks to circumvent the unreliable nature of the computational modules while still retaining low power/energy consumption. The adder configurations presented previously draw significant resemblance to this type of system. The LOA and AMAs resort to approximate logic to target reliable modules and PFA resorts to characterizing probabilistic behavior of nanoscale modules. However, one of the issues that must be addressed for inexact computing is that probabilistic implementations may likely tradeoff too much accuracy for little saving in area and power. In this section, this tradeoff is evaluated using the product of power and NED of a design. Consider first the power consumption of the adders. As suggested in [3], the energy (E) consumed by a probabilistic inverter increases exponentially with the probability of its correct functioning, p, if the noise magnitude remains constant. For simplicity, here we assume that the energy consumption of any binary gate increases exponentially with p. It is further assumed that the power consumption of any adder is normalized to that of a 1-bit CFA (given by a unit power), i.e., E 1 CFA = 1. (34) Hence, the power consumption of a 1-bit PFA is then: E 1 PFA = E 1 CFA ep = e 1 ep 1. (35) For a k-bit CFA, its power is then: E CFA = k E 1 CFA = k. (36) For a k-bit PFA with m higher bits and n lower bits, its power consumption is given by: E PFA = m E 1 CFA + n E 1 PFA = m + n e p 1. (37) Since adders perform a similar function (i.e., an addition), we assume that the switching activities of the gates in an adder are similar. Therefore, the power consumption is considered to be proportional to the number of logic gates for an approximate implementation. In a single-bit LOA, there is only one OR gate instead of five gates as in a conventional adder; so as a first-order estimation, the power consumption of the lower bits in a LOA is 1/5 of that in a CFA, i.e., E LOA = m E 1 CFA + n E OR = m n. (38) For the three AMAs, a reduction in the number of transistors allows for a lower operating voltage, which subsequently reduces power consumption. An application of the Inverse Discrete Cosine Transform (IDCT) is considered for evaluating the power consumption in [8]. Compared to an operating voltage of 1.13 V for the accurate IDCT operation (equivalent to an operation using the CFA), an AMA-based IDCT operation requires a voltage of 1.04 V, 1.1 V and 1.01 V, respectively for the three approximate implementations [8]. Therefore, the power can be estimated as E AMA 1 = m E 1 CFA + n E 1 AMA 1 = m + n (39) E AMA 2 = m E 1 CFA + n E 1 AMA 2 = m + n (40) E AMA 3 = m E 1 CFA + n E 1 AMA 3 = m + n (41) For the LIA, its power consumption is simply: E LIA = m. (42) The power consumption and saving of each lower bit compared to the CFA are reported in Table 4 for the various implementations. Given a fixed power budget, it has

10 10 IEEE TRANSACTIONS ON COMPUTERS, TC been shown that the MED of the PFA drastically increases with the number of lower unreliable bits, while the LIA has a significantly lower MED and the LOA performs the best with the smallest MED [11]. For a fixed MED, similarly, the power consumption of a 32-bit sequential adder can be considered. TABLE 4. POWER AND SAVING PER LOWER BIT OF THE ADDER IMPLEMENTATIONS (COMPARED TO AND NORMALIZED TO THE POWER CONSUMPTION OF A 1-BIT CFA). Implementation Power per bit Power saving per bit p=0.05 : p=0.028: PFA p=0.02: p=0.01: p=0.005: LOA LIA 0 1 AMA AMA AMA Table 5 shows the power consumption of the various implementations at MED=16. There is no substantial difference in the power consumption; however, the LOA has the best performance with the LIA as a close second. The PFAs consume more power than the LIA. For more unreliable bits, a lower error rate is required, so a higher power consumption results. So far, the comparison is constrained by either a fixed power budget or MED. Next, a different metric is used to evaluate the tradeoff between power consumption and precision (as represented by NED). and precision. As shown in Fig. 11, the AMA2 has a similar power precision tradeoff as the PFA with a gate error rate of 0.05, while the AMA3 has a better power efficiency. Also shown is that the PFA with a gate error rate of has a comparable power-ned product to that of the LOA, so a PFA with a lower gate error rate is preferred. This tradeoff can further be explained by the ratio of the normalized power saving and NED, i.e., the power saving per lower bit (compared to the CFA) divided by the NED. This power saving-ned ratio provides a quantitative measure to assess the implications of the efficiency as related to the power saving per unit of the resulting error distance. Since it is normalized to one lower bit, as shown in Fig. 12, the power saving-ned ratio is also nearly independent of the number of lower bits. Moreover from Fig. 12, the LOA has the highest ratio; so when trading off precision for power saving, the LOA has a better efficiency than other designs considered in this paper. Note that in the analysis of the power-ned product and power saving-ned ratio, the CFA and LOA are not included, because the CFA has an NED of 0 and the LOA has a power of 0 (per lower bit). This shows a limitation of these measures, i.e., their inability to capture the effect of an individual metric of power or precision. TABLE 5. POWER CONSUMPTION OF VARIOUS IMPLEMENTA- TIONS OF A 32-BIT ADDER WITH A LARGEST MED OF 16 (IN UNITS OF POWER CONSUMPTION OF A 1-BIT CFA). Implementation Features Power consumption m=27, n=5 : p= PFA m=26, n= 6 : p= m=25, n= 7 : p= LOA m=26, n=6 27 LIA m=28, n=4 28 AMA1 m=26, n= AMA2 m=26, n= AMA3 m=26, n= This metric is given by the product of the normalized power per lower bit and NED, i.e., the power-ned product. As shown in Fig. 11, the power-ned product of a design has a rather constant value, which is nearly independent of the number of lower bits. For an implementation such as the PFA with a gate error rate of 0.005, its power consumption is considered high, while its NED is low. For a larger gate error rate, the power consumption decreases, while the NED increases. However, this synergetic effect of power and NED is captured by the power- NED product; the smaller the product, the better the design, in terms of a tradeoff between power consumption Fig. 11. The power-ned product vs. the number of lower bits for different adder implementations and gate error rates. Fig. 12. The power saving-ned ratio vs. the number of lower bits for different adder implementations and gate error rates.

11 LIANG ET AL.: NEW METRICS FOR THE RELIABILITY OF APPROXIMATE AND PROBABILISTIC ADDERS 11 The relationship between power and precision, however, is further revealed in Fig. 13, in which the analysis of CFA and LIA is included. Power and precision are represented by the power consumption per bit and the NED of a design. While the LIA and CFA are the two extreme corner designs (with a power of 0 and an NED of 0, respectively), the other designs generally save power by allowing for some loss of precision. The LOA shows a better tradeoff between power saving and precision loss. Clearly, a design with a better power saving efficiency in terms of precision loss is desired (as indicated by the direction of the arrow in Fig. 13). As the product of normalized power and NED is used to investigate the precision/power relationship, this imposes an equal weight on the impact of power consumption and precision. In practice, a different measure that emphasizes the importance of a particular metric (such as the power or precision) can be used for a better assessment of a design according to the specific requirement of an application. Fig. 13. Relationship between power and precision, given by the power consumption per bit and the NED of a design. Each dashed curve indicates a value of the product of power per bit and the NED. The arrow points to the direction for a better design with a more efficient power and precision tradeoff. 6 CONCLUSION This paper has proposed several new metrics for evaluating approximate and probabilistic adders with respect to their reliability and power efficiency, as unified figures of merit for design assessment in inexact computing applications. The Error distance (ED) is defined as the arithmetic distance between an erroneous output and the correct one. The Mean error distance (MED) and normalized error distance (NED) have been proposed by considering the averaging effect of multiple inputs and the normalization of multiple-bit adders. While the MED is effective in evaluating the adder implementation of multiple bits, the NED is nearly invariant with the size of an implementation and is therefore useful in the reliability assessment of a specific design. To evaluate the tradeoff between power consumption and precision, the product of power and NED has been considered and the power efficiency against the precision loss is computed for gaining insights into the effectiveness of a design. The socalled sequential probability transition matrices (SPTMs) have been formulated for use in the computation of the proposed metrics. Using the proposed metrics, several adder implementations, namely the LOA, AMAs and PFA, are compared against a baseline implementation, the LIA. Simulation results have indicated that, compared to probabilistic adders such as the PFA, approximate adders such as the LOA and AMAs are advantageous in terms of power saving, but with a relatively low precision (comparable to that of the PFA with a high gate error rate). Probabilistic adders such as the PFA, on the other hand, are able to provide a high precision, especially for a low gate error rate, but at the cost of a relatively high power consumption. This tradeoff in precision and power are quantitatively evaluated using the proposed metric of power- NED product. The evaluation results are further supported by the analysis of the power saving and NED ratio that indicates the efficiency of a design in trading off precision for power. Although not discussed and beyond the scope of this paper, the proposed metrics may also be useful in assessing other arithmetic circuits [20] for inexact computing and/or fault-tolerant designs [21] in nanocomputing applications. REFERENCES [1] Y. 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Fortes, Toward hardwareredundant, fault-tolerant logic for nanoelectronics, IEEE Design and Test of Computers, vol. 22, no. 4, pp , July August Jinghang Liang was born in Jilin, China, in He received the B.Eng. degree in Institute of Microelectronics from Tsinghua University, China, in Since 2010, he has been pursuing the M.Sc degree in Electrical and Computer Engineering, University of Alberta, Edmonton, Canada. His research interests include nanoelectronic circuit and system design, fault-tolerant system design and genetic network modeling. Besides, he is interested in RF circuit designs especially high-speed PLLs. Jie Han (S 02 M 05) received the B.Sc. degree in electronic engineering from Tsinghua University, Beijing, China, in 1999 and the Ph.D. degree from Delft University of Technology, The Netherlands, in He is currently an assistant professor in the Department of Electrical and Computer Engineering at the University of Alberta, Edmonton, AB, Canada. He was a NASA INAC (Institute for Nanoelectronics and Computing) Postdoctoral Fellow in the Department of Electrical and Computer Engineering at the University of Florida from 2004 to From 2007 to 2009, he worked as a Research Scientist at the Advanced Medical Diagnostics S.A./B.V. in Belgium. His research interests include reliability and fault tolerance, nanoelectronic circuits and systems, novel computational models for nanoscale and biological applications. Dr. Han was nominated for the 2006 Christiaan Huygens Prize of Science by the Royal Dutch Academy of Science (Koninklijke Nederlandse Akademie van Wetenschappen (KNAW) Christiaan Huygens Wetenschapsprijs). His work was recognized by the 125th anniversary issue of Science, for developing theory of fault-tolerant nanocircuits. He has published a book, two book chapters and about 25 refereed articles in journals and conferences. He served as a Technical Program Chair in IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2012) and as a Technical Committee Member in DFT 2011, the International Workshop on Unique Chips and Systems, 2010 (UCAS- 6) and 2012 (UCAS-7), and the First International Workshop on Secure and Resilient Architecture and Systems (WSRAS 2012). Fabrizio Lombardi (M 81 SM 02-F 09) graduated in 1977 from the University of Essex (UK) with a B.Sc. (Hons.) in Electronic Engineering. In 1977 he joined the Microwave Research Unit at University College London, where he received the Master in Microwaves and Modern Optics (1978), the Diploma in Microwave Engineering (1978) and the Ph.D. from the University of London (1982). He is currently the holder of the International Test Conference (ITC) Endowed Chair Professorship at Northeastern University, Boston. At the same Institution during the period he served as Chair of the Department of Electrical and Computer Engineering. Prior to Northeastern University, he was a faculty member at Texas Tech University, the University of Colorado-Boulder and Texas A&M University. During Dr. Lombardi was the Editor-In-Chief of the IEEE Transactions on Computers. He is also an Associate Editor of the IEEE Transactions on Nanotechnology and IEEE Transactions on CAD of ICAS. Dr. Lombardi serves as the Chair of the Committee on "Nanotechnology Devices and Systems" of the Test Technology Technical Council of the IEEE ( ). In the past, Dr. Lombardi was an Associate Editor ( ) and Associate Editor-in-Chief ( ) of the IEEE Transactions on Computers and twice a Distinguished Visitor of the IEEE-CS ( and ). Dr. Lombardi is a Golden Core Member of the IEEE Computer Society and Fellow of the IEEE for "contributions to testing and fault tolerance of digital systems". He is the recipient of the 2011 Meritorious Service Award by the IEEE Computer Society. Starting January 1, 2012 he is serving as an elected Member of the Board of Governors of the IEEE Computer Society. Dr. Lombardi has received many professional awards: the Visiting Fellowship at the British Columbia Advanced System Institute, University of Victoria, Canada (1988), twice the Texas Experimental Engineering Station Research Fellowship ( , ) the Halliburton Professorship(1995), the Outstanding Engineering Research Award at Northeastern University (2004) and an International Research Award from the Ministry of Science and Education of Japan ( ). Dr. Lombardi was the recipient of the 1985/86 Research Initiation Award from the IEEE/Engineering Foundation and a Silver Quill Award from Motorola-Austin (1996). At the IEEE DFT07 Symposium, one of his papers won the best paper award. Dr. Lombardi has been involved in organizing many international symposia, conferences and workshops sponsored by professional organizations as well as guest editor of Special Issues in archival journals and magazines such as IEEE Transactions on Computers, IEEE Transactions on Instrumentation and Measurement, IEEE Transactions on VLSI, the IEEE Micro Magazine and the IEEE Design & Test Magazine. He is the Founding General Chair of the IEEE Symposium on Network Computing and Applications and the IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems. His research interests are bio-inspired and nano manufacturing/computing, VLSI design, testing, and fault/defect tolerance of digital systems. He has extensively published in these areas and coauthored/edited seven books.