AON V Common-Drain Dual N-Channel MOSFET
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1 2V CommonDrain Dual NChannel MOSFET General Description Low R DS(ON) With ESD Protection to improve battery performance and safety Common drain configuration for design simplicity RoHS and HalogenFree Compliant Product Summary V DS I D (at V GS =4.V) R DS(ON) (at V GS =4.V) R DS(ON) (at V GS =3.7V) R DS(ON) (at V GS =3.V) R DS(ON) (at V GS =2.V) 2V 2A <.mω < 7mΩ < 7.8mΩ < 8.mΩ Typical ESD protection HBM Class 2 Application Battery protection switch Mobile device battery charging and discharging DFN 2XA Top View Bottom View D D2 S2 S2 G2 D/D2 G G2 S S G S S2 Orderable Part Number Package Type Form Minimum Order Quantity AON8 DFN2XA Tape & Reel Absolute Maximum Ratings T A =2 C unless otherwise noted Parameter Symbol Maximum DrainSource Voltage 2 GateSource Voltage Continuous Drain Current Pulsed Drain Current C T A =2 C T A =7 C V DS V GS I D I DM T A =2 C.7 P Power Dissipation A DSM W T A =7 C Junction and Storage Temperature Range T J, T STG to C ±2 2 Units V V A Thermal Characteristics Parameter Symbol Typ Max Maximum JunctiontoAmbient A t s 3 4 R θja Maximum JunctiontoAmbient A D SteadyState 7 Maximum JunctiontoCase SteadyState 4.. R θjc Units C/W C/W C/W Rev.: November 2 Page of
2 Electrical Characteristics (T J =2 C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units STATIC PARAMETERS BV DSS DrainSource Breakdown Voltage I D =2µA, V GS =V 2 V V DS =2V, V GS =V I DSS Zero Gate Voltage Drain Current µa T J = C I GSS GateBody leakage current V DS =V, V GS =±V µa V GS(th) Gate Threshold Voltage V DS =V GS, I D =2µA..9.3 V R DS(ON) Static DrainSource OnResistance V GS =4.V, I D =2A V GS =3.7V, I D =A V GS =3.V, I D =8A V GS =2.V, I D =8A. T J =2 C mω. 7.8 mω.2 8. mω g FS Forward Transconductance V DS =V, I D =2A S V SD Diode Forward Voltage I S =A,V GS =V.3 V I S Maximum BodyDiode Continuous Current 3 A DYNAMIC PARAMETERS C iss Input Capacitance 27 pf C oss Output Capacitance V GS =V, V DS =V, f=mhz 33 pf C rss Reverse Transfer Capacitance 27 pf R g Gate resistance V GS =V, V DS =V, f=mhz 3. Ω SWITCHING PARAMETERS Q g Total Gate Charge 22 3 nc Q gs Gate Source Charge V GS =4.V, V DS =V, I D =2A 3 nc Q gd Gate Drain Charge nc t D(on) TurnOn DelayTime 2 ns t r TurnOn Rise Time V GS =4.V, V DS =V, R L =.8Ω, 24 ns t D(off) TurnOff DelayTime R GEN =3Ω ns t f TurnOff Fall Time 27 ns t rr Body Diode Reverse Recovery Time I F =2A, di/dt=a/µs 23 ns Q rr Body Diode Reverse Recovery Charge I F =2A, di/dt=a/µs 4 nc A. The value of R θja is measured with the device mounted on in 2 FR4 board with 2oz. Copper, in a still air environment with T A =2 C. The Power dissipation P DSM is based on R θja and the maximum allowed junction temperature of C. The value in any given application depends on the user's specific board design. B. The power dissipation P D is based on T J(MAX) = C, using junctiontocase thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used. C. Repetitive rating, pulse width limited by junction temperature T J(MAX) = C. Ratings are based on low frequency and duty cycles to keep initial T J =2 C. D. The R θja is the sum of the thermal impedance from junction to case R θjc and case to ambient. E. The static characteristics in Figures to are obtained using <3µs pulses, duty cycle.% max. F. These curves are based on the junctiontocase thermal impedance which is measured with the device mounted to a large heatsink, assuming a maximum junction temperature of T J(MAX) = C. The SOA curve provides a single pulse rating. G. The maximum current rating is package limited. H. These tests are performed with the device mounted on in 2 FR4 board with 2oz. Copper, in a still air environment with T A =2 C. mω APPLICATIONS OR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN,FUNCTIONS AND RELIABILITY WITHOUT NOTICE. Rev.: November 2 Page 2 of
3 TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS 8 4.V 2.V 3.V 3.7V 2V 8 V DS =V I D (A) 4 I D (A) C V GS =.V V DS (Volts) Fig : OnRegion Characteristics (Note E) 2 C V GS (Volts) Figure 2: Transfer Characteristics (Note E) 8. R DS(ON) (mω) 7 4 V GS =4.V V GS =2.V V GS =3.V V GS =3.7V Normalized OnResistance.4.2 V GS =2.V I D =8A V GS =3.V I D =8A V GS =4.V I D =2A 7 V GS =3.7V I D =A I D (A) Figure 3: OnResistance vs. Drain Current and Gate Voltage (Note E) Temperature ( C) Figure 4: OnResistance vs. Junction 8Temperature (Note E) R DS(ON) (mω) C 2 C I D =2A I S (A).E2.E 4.E.E.E2.E3 2 C 2 C 2.E V GS (Volts) Figure : OnResistance vs. GateSource Voltage (Note E).E V SD (Volts) Figure : BodyDiode Characteristics (Note E) Rev.: November 2 Page 3 of
4 TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS 8 V DS =V I D =2A V GS (Volts) 4 2 Capacitance (pf) 2 2 C oss C iss Q g (nc) Figure 7: GateCharge Characteristics C rss 2 V DS (Volts) Figure 8: Capacitance Characteristics I D (Amps)..... R DS(ON) T J(Max) = C T C =2 C DC µs µs µs ms ms Power (W) T J(Max) = C T C =2 C V DS (Volts) V GS > or equal to 2.V Figure 9: Maximum Forward Biased Safe Operating Area (Note F).... Figure : Single Pulse Power Rating 8JunctiontoCa (Note F) Z θjc Normalized Transient Thermal Resistance. D=T on /T T J,PK =T C P DM.Z θjc.r θjc R θjc =. C/W Single Pulse. E In descending order D=.,.3,.,.,.2,., single pulse P D T on T Figure : Normalized Maximum Transient Thermal Impedance (Note F) Rev.: November 2 Page 4 of
5 TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS 3 Power Dissipation (W) 2 2 Current rating I D (A) T CASE ( C) Figure 2: Power Derating (Note F) T CASE ( C) Figure 3: Current Derating (Note F) T A =2 C Power (W) E.. Figure 4: Single Pulse Power Rating JunctiontoAmbient (Note H) Z θja Normalized Transient Thermal Resistance.. D=T on /T T J,PK =T A P DM.Z θja.r θja R θja =7 C/W Single Pulse. E In descending order D=.,.3,.,.,.2,., single pulse P D T on T Figure : Normalized Maximum Transient Thermal Impedance (Note H) Rev.: November 2 Page of
6 Gate Charge Test Circuit & Waveform Qg VDC DUT VDC Vds V Qgs Qgd Ig Charge V ds R L Resistive Switching Test Circuit & W aveforms V ds R g V gs D U T VD C Vdd 9% % V gs V gs td(on ) t r t d (o ff) t f t on t off Diode Recovery Test Circuit & Waveforms Vds DUT Q rr = Idt Vds Ig Isd L VDC Vdd Isd Vds I F di/dt I RM t rr Vdd Rev.: November 2 Page of
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