FEATURES FUNCTIONAL BLOCK DIAGRAM

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1 TECHNICAL DATA DC-TO-DC CONVETE CONTOL CICUIT IL0A The IL0A is a monolithic control circuit containing the primary functions required for DC-to-DC converters. These devices consist of an internal temperature compensated reference, comparator, controlled duty cycle oscillator with an active current limit circuit, driver and high current output switch. This series was specifically designed to be incorporated in tep-down and tep-up and Voltage-Inverting applications with a minimum number of external components. FEATUE FUNCTIONAL BLOCK DIAGAM Operation from.0 V to 0 V Input Low tandby Current Current Limiting Output witch Current to. A Output Voltage Adjustable Frequency Operation to 00 khz Precision % eference MAXIMUM ATING ating ymbol Value Unit Power upply Voltage V CC 0 Vdc Input Voltage ange V I -0. to 0 Vdc witch Collector Voltage V C(switch) 0 Vdc witch Emitter Voltage (Vpin = 0 V) V E(switch) 0 Vdc witch Collector to Emitter Voltage V CE(switch) 0 Vdc Driver Collector Voltage I C(driver) 0 Vdc Driver Collector Current (Note ) I C(driver) 00 ma witch Current I W. A Power Dissipation and Thermal Characteristics Ceramic Package, U uffix T A = C Thermal esistance Plastic Package, P uffix T A = C Thermal esistance OIC Package, D uffix TA = C Thermal esistance Operating Junction Temperature TJ 0 C Operating Ambient Temperature ange T A 0 to 0 C torage Temperature ange Tstg -to0 C P D qja P D qja P D qja W C/W W C/W mw C/W ev. 0

2 IL0A ODEING INFOMATION Device Temperature ange Package 0AD O- 0 to 0 C 0AN Plastic DIP Pin connection ELECTICAL CHAACTEICITIC (V CC =.0 V, T A = 0 to 0 o C unless otherwise specified.) Characteristics ymbol Min Typ Max Unit OCILLATO Frequency (V Pin = 0 V, C T =.0 nf, T A = C) fosc khz Charge Current (V CC =.0 V to 0 V, T A = C) Ichg ma Discharge Current (V CC =.0 V to 0 V, T A = C) Idischg ma Discharge to Charge Current atio (Pin to Vcc, T A= C) Idischg/Ichg... Current Limit ense Voltage (Ichg = Idischg, T A = C) Vipk(sense) mv OUTPUT WITCH (Note ) aturation Voltage, Darlington Connection (I W =.0 A, Pins, V CE (sat).0. V connected) aturation Voltage (I W =.0 A, Pin = W to V CC. V CE (sat) V Forced b = 0) DC Current Gain (I W =.0 A, V = CE.0 V, T A = C) h FE 0 0 Collector Off-tate Current (V CE = 0V) I C (off) ma COMPAATO Threshold Voltage (T A = C) Vth... V (T A = T LOW to T HIGH)..9 Threshold Voltage (T A = C) ** Vth... V Threshold Voltage Line egulation (V CC = 0 V to 0 V) egline..0 mv Input Bias Current (Vin=0V) I IB na TOTAL DEVICE upply Current (V CC = 0 V to 0 V, C T = 0 nf, V pin = V CC. V Pin > Vth, Pin = Gnd, emaining pins open) I CC..0 ma NOTE:. Maximum package power dissipation limits must be observed.. Low duty cycle pulse techniques are used during test to maintain Junction temperature as close to ambient temperature as possible. If the output switch is driven into hard saturation (non Darlington configuration) at low switch currents (< 00 ma) and high driver currents (>0 ma), it may take up to.0 ms to come out of saturation This condition will shorten the off' time at frequencies > 0 khz, and is magnified at high temperatures This condition does not occur with a Darlington configuration, since the output switch cannot saturate If a non Darlington configuration is used, the following output drive condition is recommended Forced b of output switch = I C, output/(ic, driver -.0 ma*) > 0 *The 00 W. resistor in the emitter of the driver device requires about.0 ma before the output switch conducts **Possible version for shipment ev. 0

3 IL0A TYPICAL APPLICATION CICUIT tep-up Converter L 0mH 0W DC WC WE D BYV0-0 G 0.W Vcc TC V C 00 mf Cll 0A/E GND C.nF.kW kw C 0mF Test Condition (V OUT = V) Test Conditions Value (Typ) Unit Line egulation V IN = to V, I O = ma 0 mv Load egulation V IN = V, I O = to ma 0 mv Output ipple V IN = V, I O = ma 00 mv Efficiency V IN = V, I O = ma 9 % ev. 0

4 IL0A tep-down Converter DC WC 0.W WE BYV0-0 D Vcc TC Cll GND L 0mH C C 00 mf 0A/E 0pF.kW.kW C 0mF Test Condition (V OUT = V) Test Conditions Value (Typ) Unit Line egulation V IN = to V, I O = 00 ma mv Load egulation V IN = V, I O = 0 to 00 ma 0 mv Output ipple V IN = V, I O = 00 ma 00 mv Efficiency V IN = V, I O = 00 ma 0 % IC V IN = V, LOAD = 0. W. A ev. 0

5 IL0A Voltage Inverting Converter DC WC 0.W WE L 90mH Vcc TC. to V C 00mF Cll 0A/E GND C.nF D BYV0-0.kW 9W -V / 00mA C 000mF Test Condition (V OUT = - V) Test Conditions Value (Typ) Unit Line egulation V IN =. to V, I O = 00 ma mv Load egulation V IN = V, I O = 0 to 00 ma 0 mv Output ipple V IN = V, I O = 00 ma 0 mv Efficiency V IN = V, I O = 00 ma % IC V IN = V, LOAD = 0. W 0.9 A ev. 0

6 IL0A Calculation Parameter tep-up (Discontinuous mode) tep-down (Continuous mode) Voltage Inverting (Discontinuous mode) t on /t off V out V F -V in(min) V out V F êv out ê V F V in(min) - V sat V in(min) - V sat - V out V in - V sat (t on t off )max /f min /f min /f min C T.x0 - t on.x0 - t on.x0 - t on I PK(switch) I out(max) [(t on /t off )] I out(max) I out(max) [(t on /t off )] C 0./I PK(switch) 0./I PK(switch) 0./I PK(switch) C O I out t on I PK(switch) (t on t off ) I out t on º º V ripple(p-p) V ripple(p-p) V ripple(p-p) L(min) V in(min) - V sat V in(min) -V sat -V out V in(min) - V sat t I on(max) t on(max) PK(switch) IPK(switch) IPK(switch) t on(max) NOTE: V sat = aturation voltage of the output switch V F = Forward voltage drop of the output rectifier THE FOLLOWING POWE UPPLY CHAACTEITIC MUT BE CHOEN: V in = Nominal input voltage V out = Desired output voltage, êv out ê =.( / ) I out = Desired output current fmin = Minimum desired output switching frequency at the selected values of Vin and lo V ripple = Desired peak to peak output ripple voltage. In practice, the calculated capacitor value will and to be increased due to its equivalent series resistance and board layout. The ripple voltage should be kept to a low value since it will directly affect the line and load regulation. tep-up With External NPN witch -.V eference egulator ev. 0

7 IL0A tep-down With External NPN witch. V eforence egulator tep-down With External PNP witch. V eference egulator ev. 0

8 IL0A Voltage Inverting With External NPN witch. V eference egulator Voltage Inverting With External PNP aturated witch V IN. V eforence egulator ev. 0

9 IL0A Dual Output Voltage V GND -V. V eforence egulator Higher Output Power, Higher Input Voltage Isolated from input - -. V eforence egulator ev. 0

10 IL0A N UFFIX PLATIC DIP (M 00BA) A NOTE: F G N D 0. (0.00) M T B -T- C -T-. Dimensions A, B do not include mold flash or protrusions. Maximum mold flash or protrusions 0. mm (0.00) per side. K EATING PLANE M L H J Dimension, mm ymbol MIN MAX A. 0. B.. C. D F.. G H.. J 0 0 K.9. L.. M N 0. D UFFIX OIC (M - 0AA) H D A G B 0. (0.00) M T C M K P C EATING PLANE J ymbol MIN MAX A. B. C.. D F 0.. G H Dimension, mm J 0 NOTE: K Dimensions A and B do not include mold flash or protrusion. M Maximum mold flash or protrusion 0. mm (0.00) per side P.. for A; for B 0. mm (0.00) per side x F M.. ev. 0