Research on an Improved Power Factor Correction Method Based on Single-Cycle Control Wenwen Zhang1, a, Zilong Liu2, b Jidong Xia3, c

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1 nd Internatinal Cnference n Electrnic, Netwrk and Cuter Engineering (ICENCE 06) Reearch n an Irved wer Factr Crrectin Methd Baed n ingle-cycle Cntrl Wenwen Zhang, a, Zilng Liu, b Jidng Xia3, c niverity f hanghai fr cience and Technlgy, chl f tical-electrical and Cuting Engineering, hanghai, China, a eail, beail, ceail, Keywrd: wer Factr Crrectin, ne Cycle Cntrl, Circuit Tlgy, tability Abtract. Analyi the cnventinal tlgy f Bt wer factr crrectr and inut uivalent circuit and int ut that cnventinal tlgy f Bt wer factr crrectr exit with irveent f cnverter wer and the witching fruency. The efficiency f yte i greatly reduced. The aer re a dified wer factr crrectr,analyze the dified Bt circuit tlgy,baic rincile, analyze the irved ne-cycle cntrl uatin f the circuit, give the electin f araeter f the ain cnent with theretical bai analyze the deign f cntrl yte f the I regulatr in thery and calibrate the cntrl yte a tyical Ⅱ tye yte, irve the anti-jaing ability and tability f the yte, and ake a rttye t rve the validity f theretical reult. Intrductin With the develent f wer electrnic technlgy, re and re wer int the grid rectifier ued in the benefit f the wer indutry, but al t the large nuber f harnic injected int the wer grid, AFC (Active wer Factr Crrectin) active wer factr crrectin al It ha bece a ht reearch chlar, traditinal Bt wer factr crrectin circuit becaue the circuit by M tranitr witching fruency f liit [-5], baed n the CC (ne Cycle Cntrl) wer factr can reduce the ultilier and inut vltage detectin circuit, any chlar ingle and three-hae cnverin are ade baed n ne week f FC circuit, baed n the rincile f quai-teady tate cntrl, CC FC cnverter can be cnidered a deeed t DC-DC cnverin architecture teady-tate eratin f the witch in a ingle week, if the inut fr end cntrl hae vltage and hae current rati i a cntant, it can be regarded a a wer factr f. At reent, t reearch fcue n the wer fruency f (50Hz) cae, a hwn in Figure i a cheatic diagra f a cnventinal ingle-cycle cntrlled Bt cnverter, naely: after bridge rectifier cnnected Bt circuit, a wer crrectin circuit can be reved later in the bridge rectifier the large filter caacitr C, that the utut vltage f the rectifier behind half ine wave, Bt will change jut by changing the duty cycle f the inuidal utut vltage i higher than the axiu cntant DC vltage, which i t nitr the cre eence f the half-wave rectified half-wave vltage, the current tracking vltage, Bt cnverter will rie and fall alng the half-ine curve different vltage int a DC vltage rincile i, in a erid T witch i turned n fr e tie TN, energy trage inductr L, when the witch i turned ff, the inductr L are revered larity. 06. The authr - ublihed by Atlanti re 959

2 Fig cheatic f cnventinal bt cnverter When the dt L end f the inductr vltage rie higher than the inut vltage V in, witch, the inductance energy t rvide energy L t the lad thrugh VD, ff, during trage f T N thi cnverter utut - inut vltage relatinhi a fllw: VIN V () T N T The ain tak f the wer factr crrectin circuit i the ue f Bt cnverter will be cnverted int table alng half ine wave vltage rie and fall f nwhere than the axiu alitude f the inut inuidal vltage lightly higher DC vltage utut, wer factr crrectin circuit f the ecnd circuit the ain tak i t detect the inut current f the wer grid, and inut it int the grid vltage inuidal hae [7-8]. The ain rincile i t cntrl the chi grid aling f current and inuidal current reference i cared, the difference between thee tw ine wave will rduce an errr vltage, the errr vltage t adjut the turn-n vltage, that the grid current ale and the reference ine current have the ae alitude and hae, in Figure, the ine itive thrughut the erid, there will alway be tw fur bridge rectifier witching device will be turned n, regardle f the tage rtin ine itive r negative axle axle there will be a freewheeling dide r a M tranitr i turned n at all tie, that any three f the witching device i turned n, the increae with the increae f the witching device and witching fruency, witching le will increae, the verall yte l will increae, that the verall efficiency will be reduced. T lve thi rble thi aer fr CC FC circuit tructure analyi, t rvide an irved CC FC circuit, it i ible t irve the tability and rbutne f the yte. General CC FC Cnverter Inut Equivalent Circuit and Analyi Thi aer analyze the ingle-hae CC FC circuit, Figure hw the ain ingle-hae CC FC ain circuit tlgy, within a erid f the utut vltage can be cnidered cntant aunt, the entire cntrller utut teady-tate value, wherein i the inut aling reitr grid, the tranfer functin H i the vltage cntrl. V ( ) iin(t) z AC in(t) in(wt) + (t) - + C - R R R / Dff(t) HV() Kv ref + Fig CC FC cnverter chart Thrughut the everal cnecutive witching cycle AC / DC cnverter can be cnidered a teady-tate eratin f DC / DC cnverter circuit, the inut vltage in(t) and the reference vltage ref circuit, which can be arxiated by the uatin. D () in( t ) ff ref 960

3 Wherein D ff i the witch ff when the duty cycle, but al by the inut D current aling ff reitr i in(t) and the rduct f the entire cntrller R teady-tate utut rati baed n the calculated araeter, the araeter are calculated a fllw: D i ( t) R in ff () We need t get the uivalent circuit f FIG. 3, the circuit by the reence f the fllwing uatin, in( t) iin( t) R (3) Ang the, the uivalent reitance i a fllw. R ( R ) / (4) iin(t) in(t) R Irved FC Circuit Diagra Fig 3 CC FC inut uivalent circuit Accrding t the literature [5], irved FC circuit, a hwn, the circuit analyi thery, Fig 4 Irved FC circuit tlgy Circuit can be brken ver the entire erid f fur tate circuit cheatic [9-], the fur kind f uivalent circuit diagra, the itive half cycle f the inuidal AC circuit, the uivalent circuit diagra f tw 5 Fr the Fig. 5 (a) circuit, the itive half cycle inuidal vltage alternating current fr charging the inductr L, cling witch M tranitr, VD cntrlled cnductin, thi tate 4 caacitr C t rvide energy lad; when cled M tranitr, which i uivalent t circuit hwn in Figure (b) inverting the larity f inductr L, cntrlled anti-arallel araitic dide cnducting, fr wering lad while caacitr C i charged. 96

4 Fig 5 The half circle inuidal vltage inuidal vltage negative half-cycle tie, wrk tie uivalent circuit diagra f the circuit hwn in Figure 6, which wrk a fllw, FIG. 6 (c) cheatic, i cled at thi tie M tranitr i turned n, the flw thrugh the witch anti-arallel dide, and the caacitr lad C, when the witch i turned ff when the inductance L f the larity i inverted, VD cnductin cntrlled t rvide energy lad while the utut caacitr C t rvide energy, cntrlled anti-arallel dide i turned n. Fig 6 inuidal vltage negative half-cycle Baed n the abve analyi, the cnventinal ingle-cycle cntrl f wer factr crrectin, there are three witching device i turned n, the irved wer factr crrectin ha tw witching device turned n during any erid in any erid ince the M and cn grund, n external ilatin circuit, driving circuit i ile, due t lwer wer cnutin, it i uitable fr ediu and high-wer alicatin. The Main Cntrl cheatic f Irved wer Factr Crrectin Circuit 96

5 ne cycle cntrl cntrl cre idea i t ake the average f the cntrl bject and witch variable in each erid f the reference aunt i rrtinal t [3]. ince the witch tube drive circuit i ile and a fruency fixed aunt, the circuit deign WM drive utut electing circuit ha tw ite WM circuit, cnly ued are: D fli-fl. Next, the circuit diagra araeter detailed derivatin and calculatin, a viewed fr the AC inut, auing wer factr crrectin i, the Bt cnverter i urely reitive, can be uivalent t R, and get cntrl f the bjective functin need. u R (5) i Wherein: u i the inut AC vltage. i i the current value f the AC inut. ince the itive and negative half cycle which are uivalent t the ae Bt cnverter circuit, the relatinhi between the inut and utut tabilizing circuit utut vltage can be uivalent t, u (6) Dn Wherein: i the terinal vltage acr the lad. D n i Duty M tube at wrk. Cnlidatin (5) and (6) in accrdance with the rincile f ual affrd, Ri ( Dn ) (7) T btain the reitance f the ale with the aling vltage, the uatin (7) i ultilied t bth ide f the aling reitr R, t give R R i R ( D ) R et R (8) Re ne cycle cntrl i btained cntrl uatin ( D ) Ri (9) T (8) n bth ide iultaneuly integrating in a witching cycle, T r DnVdt (0) Tr 0 (9) uatin can be ued t build the circuit, with reitance diviin ethd t cllect the lad 963 n

6 terinal vltage, and et a gd reference vltage, a difference thrugh I regulatr utut e ref a fr the r t btain a difference, will be and ubtractin a integratr alifier cnfigured a a caratr, the utut value reached when the difference between when the caratr utut inverted, the integratr i reet while the reet ignal [4]. Deign f ingle-cycle Cntrl I Regulatr ingle-week erfrance FC cntrl circuit that cntrl the ultiate gal i t ake the utut f R the vltage tability, accrding t, the araeter can be deterined by Re, accrding t the wer f the inut wer i ual t the utut wer t give, ut in lad + I cin () R Wherein: lad i the wer cnutin f the lad I cin : Current flwing thrugh the caacitr R R Accrding t, get R. Accrding t () t get R lad + I cin () R Affect the actual deign rce f all ignal erturbatin + u + u + u Wherein I C I C + icin, ince the caacitance I i negligible, t get the nuber f tranfer C line fr i cin t u. u (4) icin C In rder t btain ecnd-rder yte, adding inertia, rvided the tranfer functin f the regulatr + Q( ) (5) ( + ) It i lcated a blck diagra f the cntrl yte are a fllw (3) erid α i fr the cale factr f the vltage detectr, accrding t the tial deign tye Ⅱ yte, the bandwidth rvided in the h 5, the en-l tranfer functin fr the entire yte, α ( + ) K( + ) q( ) R C ( + ) ( + ) 964

The Verificatin f Exeriental Data h + T get w α C c K R The abve analyi f the data, t deign a FC rttye 50A irved ne-cycle cntrl, the DC utut vltage 50V, with DC electrnic lad under cntant

3 The exeriental tet uing IV87 rgraable DC Electrnic Lad Teter, rgraed int the cntant gear 3A, the entire yte debugging circuit hwn in Figure 9, w c Fig.

7 The Verificatin f Exeriental Data h + T get w α C c K R The abve analyi f the data, t deign a FC rttye 50A irved ne-cycle cntrl, the DC utut vltage 50V, with DC electrnic lad under cntant tate current 3A, cntrlled M tranitr witching fruency i 0KHz; inductr L H, DC ide C 00uF ; adjuting the utut araeter 5, 8, 3 3.6, K The exeriental tet uing IV87 rgraable DC Electrnic Lad Teter, rgraed int the cntant gear 3A, the entire yte debugging circuit hwn in Figure 9, w c Fig.9 The rductin tet yte rttye ncrrected circuit current wavefr ditrtin i very eriu, yu can ue the THD (ttal harnic ditrtin) t eaure the ize f the araeter value, THD H n Gn ( ) G Calculated befre uncrrected a 78.4%, ingle-cycle cntrl FC circuit that crrect the wer factr dr t t, 50A rttye eauring the inut vltage and current wavefr in Figure 0, the current wavefr eriu ditrtin, wer factr lw Fig 0 Irved wer factr crrectin i nt added t the yte inut wavefr After the additin f irved wer factr crrectin yte, the yte fllw the wavefr hwn in Figure, Fig Irved wer factr crrectin yte wavefr The inut current wavefr tracking vltage, inut wer factr f ide eaure, in rder 965

8 t verify that the utut circuit efficiency rble, thi circuit eaure the efficiency f ultile et f data curve and wer factr crrectin f the cnventinal ingle-cycle cntrl utut efficiency curve were cared, t ee fr the abve data viualizatin t irve the efficiency f the yte, the efficiency f the circuit diagra hwn in Figure Fig Irved cntrat ingle-cycle cntrl and the efficiency f a cnventinal ingle-cycle cntrl Cncluin In thi aer, baed n ne week f irved cntrl f wer factr crrectin circuit, firt intrduced the yte circuit diagra f a cnventinal ingle-cycle cntrl, and ne-week wer factr crrectin circuit rincile f derivatin, intrduced cnventinal wer factr crrectin circuit the ain deign te, tw ain tak, the firt tak i the utut than the inut ine half-wave eak vltage large table DC utut vltage, the ecnd tak i t track the inut current ene inut vltage [5]. Becaue it alway ha three witch circuit i turned n within the entire cycle, leading t it efficiency i nt high enugh, in rder t lve thi aer reent an irved wer factr crrectin circuit analyi and derivatin f ingle-cycle cntrl uatin f yte deign cheatic, etablihed a ne-cycle cntrl uatin, and the t irtant deign I cntrller ha been deigned with the idea f derivatin f it deign, the final deign with a 50W ingle week baed n irved cntrl f wer factr crrectin the eauring circuit vltage and current wavefr with and withut wer factr crrectin circuit wavefr were cared, efficiency i irved by % -5%, the aer deign i ually alicable t a ingle week FCAT device cntrl. Reference [] Ma,Xie J,Xu A G,et al. Tranactin f china Electrnical ciety, Vl. (00) N5, -7 [] Wang, Ruan X,Ya K,et al. IEEE Tranactin n wer Electrnic, Vl. (0) N 7, [3] Wang B,Ruan X,Ya K,et al.ieee Tranactin n wer Electrnic, Vl. 3 (00) N 5, [4] Ni J,Zhang F,Yu Y,et al. Energy and Electrical Driver, Vl. 9 (0) N 7,.-6 [5] Chen W,Zhuang K,Ruan X.A. IEEE Tranactin n wer Electrnic, Vl. 9 (009) N 4, [6] Fang T,Ruan X,Te C K. IEEE Tranactin n wer Electrnic, Vl. 6 (00) N 5,. 966

9 [7] Zha B,Yu Q,un W X. IEEE Tranactin n wer Electrnc, Vl. (0) N 7,.-7 [8] Zhang Y W,Jin K,. rceeding f the CEE, Vl. 6 (0) N 3, [9] Hava A M,Cetin N. Tranactin n wer Electrnic, Vl. 5 (0) N 6, [0] Wu Y X,hafi M A,Knight A M,et al. IEEE Tranactin n wer, Vl. 9 (0) N 7,.-6 [] Chen W,Zhuang K,Ruan X.A. IEEE Tranactin n wer Electrnic Electrnic, Vl. (0) N 6,. 8-9 [] Bierhff M H,Fuch F W. IEEE Tranactin n Indutrial Electrnic, Vl. 5 (008) N 55, [3] Le J I.Lez,Franquel L G,et al. IEEE Tranactin n Indutrial Electrnic, Vl. 6 (00) N 57, [4] Chen W,Zhuang K,Ruan X. IEEE Tranactin n wer Electrnic,, Vl. 4 (009) N 9, [5] Bai H,Mi C. IEEE Tranactin n wer Electrnic, Vl. 6 (008) N 3,

Exclusive Technology Feature. Eliminate The Guesswork When Selecting Primary Switch V DD Capacitors. ISSUE: May 2011

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