Double-Boost DC to DC Converter

Transcription

1 Dule-Bt D t D nverter JFJ van enurg ), J ae ) and D Niclae ) ) aal Univerity f Technlgy, Faculty f Engineering & Technlgy, P. Bag X0, anderijlark, 900, Suth Africa ) Univerity f Jhanneurg, Pwer & ntrl Engineering Technlgy, PO Bx 70, Drfntein 08, Jhanneurg, Suth Africa hannevr@vut.ac.za; mcae@uj.ac.za; danaurel@ye.c.za Atract-In thi aer anew t tlgy i red. The circuit i imilar with tw arallel t dc-t-dc cnverter, ut the tw inductr are charged in arallel and releae energy in erie, thu enhancing the vltage t rati. After a hrt analyi f the circuit, a cmarative tudy with ther claic t cnverter (ingle t and tw-cacade) i reented. The imulatin reult hw a net imrvement f the t rati fr the new red tlgy. I. INTODUTION An increaed t factr uit the many emerging alicatin in the autmtive indutry, telecmmunicatin indutry, IT indutry a well a wer generatin via fuel cell, htvltaic array and wind turine [-8]. The aic t tlgy de nt rvide a high t factr. Thi ha led t many red tlgie uch a the taed-inductr t, cacaded t and interleaved t cnverter [5-8]. Thi aer intrduce anther variatin which rvide a higher t factr and al rvide fr the iility t gear u r dwn thu extending the cntrl range. Althugh cntrl methd uch a fuzzy lgic [], liding mde cntrl [4] and ther [0,, and 4] are availale, a imle IP cntrller i ued t verify the red dule -t tlgy. II. POPOSED ODE Fig. hw the red tlgy. The inductr & have the ame value, the dide D -D 3 are the ame tye and the ame aumtin wa fr the tranitr (Q & Q ). Each inductr ha it wn witch and thu i imilar with the aralleling f tw ingle/claic cnverter. D D 3 D Q Fig. Pred del A. Equivalent Diagram in O State et u firtly cnider ideal cmnent. When the tranitr Q & Q are in ON tate, the red tlgy Q tranfer energy frm the dc urce ( ) int the inductr & a can e een in Fig., where i i the current thrugh inductr/tranitr, i i the current thrugh inductr/tranitr, i i the utut current thrugh lad and i the mthing caacitr. Fig. Equivalent diagram fr Q Q ON B. Equivalent Diagram in OFF State During the OFF tate, the tw inductr are cnnected in erie, a hwn in the equivalent diagram (Fig. 3).. Bt Factr D Fig.3 Equivalent diagram fr Q Q OFF The witching frequency i high enugh the differential equatin gverning the circuit culd e linearized. Fr the charging interval (Q Q ON), the vltage acr each inductr i and the current i (t) and i (t) culd e written a: () ( ) ( ) ( ) i t i t t I 0 Q i Q i D where I (0) i the initial current thrugh inductr at t 0. When the tranitr are turned OFF at t δt, the vltage acr inductr i and the current i (t) i: D 3 i I i I

2 i( t) ( t δt) I ( δt) () Evaluating eq. () at t δt and () at t T, the ytem ecme: I ( δt) i( t δt) i( t δt) δt I ( 0) (3) I ( 0) i( t T) ( T δt) I ( δt) (4) The cnverter i deign t erate in cntinuu mde and I (0) I (δt). Frm the ytem f () and (3) the t factr fr the red circuit can e deducted: (5) δ A can e nticed, the t factr f the red tlgy i dule a regarded t the imle t cnverter. III. BOOST FATO OPAISON In rder t enhance the advantage f the red t tlgy, a t factr cmarin with a ingle and twcacaded cnverter i neceary. Thi huld e dne tang in cnideratin the real value f cmnent. A. Simle t cnverter A reented in [9], the t factr ( ) deend n inductr reitance (r ) a: / ( δ) r ( δ) When tang in cnideratin vltage dr acr the dide ( d ) and tranitr reitance in aturatin (r dn ), the t factr ecme: δ r wn / ( δ) ( δ) B. Dule cacaded t cnverter When tw identical imle cnverter are cnnected in cacade (Fig. 4), the t factr ( c ) i affected y the caacitr () in the firt unit and witching frequency. The eq. (8) hw the t factr fr the cacade. D D d Q Q (6) (7) δt r δ r wn d c / / ( δ) ( δ) ( δ). Pred dule-t cnverter Fr thi tlgy, all the real arameter huld e taken in cnideratin at nce. A can e nticed, the current thrugh inductr are lightly uneven, ut fr a gd arximatin they till can e cnidered equal. Then the t factr culd e written a: r δ r / ( δ) ( δ) wn d It can e een that the inductance reitr and vltage acr tranitr reitr in ON tate are cnidered with unity factr ecaue the charging i arallel and indeendent ne f each ther, while the dide vltage dr ha a cefficient tw ecaue they th are in erie when the energy i tranferred t the utut. I. ONTO SYSTE Fr thi tudy, a imle PI cntrller ha een ued, a hwn in Fig. 5. Fig.5 Dule-t cnverter, cntrl ytem In the teady tate, the wer alance etween inut and utut can e written a: d I ( ) I dt (0) Baed n thi dynamic equatin, majrity f authr have red a claic PI regulatr. But the cled-l tranfer functin f thi tye f regulatr ha tw zer: ref D D D 3 ( k )( τ3) τ Q Q PW 3 3 k IP eg. am Generatr (8) (9) () Fr thi tudy an integral/rrtinal (Fig. 6) lutin ha een chen a vltage regulatr, where k i, k are the integral and rrtinal cefficient reectively and τ i the time cntant f a nie-rejectin lw-a filter. ref Fig.4 Dule cacade t cnverter

3 ref k i - k - t factr f 0. cmared t.9 etimated accrding t (9). D u 3 3 D D-cathde τ 00 50u D5 S S3 45 I 0u 50 4 Fig. 6 IP egulatr The cle-l tranfer functin f the ytem i: τ ref 3 τ k () The equatin () hw that the IP lutin cancel a lw zer frm the tranfer functin imrving the dynamic f the regulatr. If the le f the ytem ( 0, and ) are laced n the Butterwrth circle with the radiu ω uch a: - ω, 3π 4 ω e j 3π j and ω 4, then the cefficient k and k i are: k (3) ( ) τ3 ( ) 3 τ3 (4) If the lad reitr i cnidered ( ), then the cefficient ecme []: ( T τ ) T τ 3 ( ) 3 (5) Fig.7 Dule-t cnverter- imulatin mdel Fig.8 Dule-t cnverter- maximum utut vltage In figure 9 & 0, the imle t imulatin mdel and maximum utut vltage are hwn. The maximum utut vltage achieved wa 5.7 fr a duty cycle f 80 ercentage. The t factr i 4.4 cmared with and etimated f u D S. 0u 50 4 k ( T τ ) ( ) Tτ (6) Fig.8 Simle-t cnverter- imulatin mdel where T SIUATION ESUTS T validate the ave tudy, the Simetrix 5.3 ftware latfrm ha een ued t imulate the red tlgy (Fig. 7) ut al the imle and the tw cacade t cnverter. Fr all the ave circuit, the value f the element have een very cnervative chen a:, 00 µh, r 0. Ω, 0 µf, d 0.8, 50 Ω, r dn 50 mω and the witching frequency f f 50 khz. Figure 7 & 8 hw the imulatin mdel fr the red t cnverter and the utut vltage. The mdel ha een tune t give the maximum utut vltage f. fr a duty cycle f 85 ercentage. Thi give a Fig.9 Simle-t cnverter- maximum utut vltage The tw-cacade t cnverter imulatin mdel i hwn in figure 0 and the maximum utut vltage in figure. The maximum utut vltage f 8. i achieved fr 80 ercentage duty cycle which rereent a t factr f 6.84 cmared t 7.9. What can al e

4 erved a very intale tarting erid, ame cncluin a in [4]. 00u D 00u D S 0u S 0u 50 4 IN U Fig.0 Tw-cacaded t cnverter- imulatin mdel Fig.4 Outut vltage f all tudied cnverter 8. Anther aect tudied wa t verify the aumtin that the charging current thrugh the tw inductr culd e cnidered equal. Fig, 5 hw the tw current and the current thrugh dide 3 n nrmal cale, while Fig. 6 hw the zm f the mment when thee entire three current jint tgether. Fig. Tw-cacade t cnverter- maximum utut vltage Figure & 3 hw the cmarative utut vltage etween the imle and tw-cacade t and etween the imle and the red dule-t reectively, while figure 4 hw all three utut vltage fr a etter cmarin. Fig. 5 Inductr and dide 3 current I Fig. 3 I Fig. Dule-t and imle-t cmarin I D3 Fig. 6 Inductr and dide 3 current-zm Frm Fig. 6 reult a 0.68 ercentage difference etween the tw inductr current, which make very much accetale the initial aumtin. I. EXPEIENTA ESUTS Fig.3 Dule-t and tw-cacade cmarin An exerimental mdel ha een uilt. Fig. 7 hw the exerimental et. Fr ractical cnvenience, the uly vltage ( ) wa 4. The ther arameter f the exeriment were: the inductr 00 µh, the lad 680 Ω, the mthing caacitr 47 µf, IF63 a witching

5 tranitr, 0 TQ50 a dide and 50 khz a witching frequency. Fig. ltage acr II. ONUSIONS Fig. 7 Exerimental et-u Fr a duty cycle f 90 ercentage, the utut vltage wa 55.3 fr the given 4 inut vltage (). Fig. 8 hw the utut vltage and the gate ignal fr a duty cycle f 90%. Figure 9, 0 hw the vltage acr tranitr Q and Q and figure hw the vltage acr the inductr. The reent aer ha reented a new t tlgy which enure a ignificant imrvement n t factr. The new dule-t cnverter ha een mdeled and the imulatin reult are reented in cmarin with claical knwn t cnverter. The exerimental reult hw an imrved t factr. EFEENES [] Fig. 8 Outut vltage. Fig. 9 ltage acr Q J.A. rale-saldaňa, et al, deling f a acade Bt nverter with Single Switch, The 3nd Annual nference f the IEEE Indutrial Electrnic Sciety, 006 [] W. ee, et al, Interleaved ZT Bt nverter with Winding Inductr and Built-In w-pa Outut Filter Suitale fr Ditriuted Fuel ell Generatin Sytem, 38th IEEE Pwer Electrnic Secialit nference, 007 [3] H.. Iu, Exerimantal Study f Intailitie in Tw arallennected Bt nverter under urrent de ntrl, th Eurean nference n Pwer Electrnic and Alicatin. 005 [4]. eerachary, General ule fr Signal Flw Grah deling and Analyi f D-D nverter, IEEE Tran. On Aerace and Electrnic Sytem, l. 40, N.,. 59-7, Jan. 004 [5] N. azquez,. Etrada,. Hernandez and E. driguez, «The Taed-Inductr Bt nverter, IEEE Internatinal nference n Indutrial Electrnic (ISIE), 007 [6] Y. Bercvich, B. Axelrd, S. Tauci and A. Iinvici, A Family f Fur-Quadrant D-D nverter, 38th IEEE Pwer Electrnic Secialit nference, 007 [7] G. Thiele and E. Bayer, ltage Duler/Triler urrent-de harge Pum Tlgy with Simle Gear Bx, 38th IEEE Pwer Electrnic Secialit nference, 007 [8] B.S. in, N.J Park and D.S. Hyun, A Nvel urrent Sharing Technique fr Interleaved Bt nverter, 38th IEEE Pwer Electrnic Secialit nference, 007 [9] I. Batareh, Pwer Electrnic ircuit, Jhn Wiley & Sn, Inc. 004, [0] Q. Zhu, Y. Huang, F. Zeng and Q-S. hen, Dynamic analyi f D-D nverter Baed n It Nnlinear haracteritic, The 3nd Annual nference f the IEEE Indutrial Electrnic Sciety, 006 [] H. Kmurcugil, A PI-Tye Self Tuning Fuzzy ntrller fr DcDc Bt nverter, The 30th Annual nference f the IEEE Indutrial Electrnic Sciety, Nvemer -6, 004 [] D Niclae, Single-Phae Unity Pwer Factr ectifier with Imrved Dynamic ene fr Nn-linear ad, Internatinal eview f Electrical Engineering, l. N. 4, , JulyAugut 007 Fig. 0 ltage acr Q k,(((