DATASHEET. Features. Applications ISL28130, ISL28230, ISL Single, Dual, and Quad Micropower, Low Drift, RRIO Operational Amplifiers

Transcription

1 DATASHEET ISL8, ISL8, ISL8 Single, Dual, and Quad Micropower, Low Drift, RRIO Operational Amplifiers FN7 Rev 7. The ISL8, ISL8 and ISL8 are single, dual and quad micropower, low offset drift operational amplifiers that are optimized for single and dual supply operation from.8v to.v and ±.9V to ±.7V. Their low supply current of µa and railtorail input/output enable the ISL8, ISL8, and ISL8 to be an excellent generalpurpose op amp for a range of applications. The ISL8, ISL8 and ISL8 are ideal for handheld devices that operate off AA or single Liion batteries. The ISL8 is available in industry standard pinouts for Ld SOT, Ld S7 and 8 Ld SOI packages. The ISL8 is available in industry standard pinouts for 8 Ld MSOP, 8 Ld SOI and 8 Ld DFN packages. The ISL8 is available in Ld TSSOP and Ld SOI packages. ommercial devices operate over the temperature range of to 7. Full temperature range devices operate over the temperature range of to. Features Low input offset voltage µv, Max. Low offset drift nv/, Max. Input bias current pa, Max. Quiescent current (per amplifier) µa, Typ. Single supply range v to +.V Dual supply range ±.9v to ±.7V Low noise (.Hz to Hz) µV PP, Typ. Railtorail inputs and output Applications Bidirectional current sense Temperature measurement Medical equipment Electronic weigh scales Precision/strain gauge sensor Precision regulation Low Ohmic current sense High gain analog front ends ISENSE+ V + +.8V TO +.V..99k.99k + V+ V 99k 99k V REF V SENSE OUT INPUT BIAS URRENT (pa) V S = ±.9V V S = ±.V ISENSE BIDIRETIONAL URRENT SENSE AMPLIFIER GND 7 TEMPERATURE ( ) FIGURE. TYPIAL APPLIATION DIAGRAM FIGURE. I B vs TEMPERATURE FN7 Rev 7. Page of 9

2 Ordering Information PART NUMBER (Notes, ) PART MARKING TEMP RANGE ( ) TEMPERATURE GRADE PAKAGE (PbFree) PKG. DWG. # ISL8HZT7 (Note ) BDPA (Note ) to +7 ommercial Ld SOT P.A ISL8HZT7A (Note ) BDPA (Note ) to +7 ommercial Ld SOT P.A ISL8FHZT7 (Note ) BEFA (Note ) to + Full Ld SOT P.A ISL8FHZT7A (Note ) BEFA (Note ) to + Full Ld SOT P.A ISL8EZT7 (Note ) BLA (Note ) to +7 ommercial Ld S7 P.9 ISL8EZT7A (Note ) BLA (Note ) to +7 ommercial Ld S7 P.9 ISL8FEZT7 (Note ) BNA (Note ) to + Full Ld S7 P.9 ISL8FEZT7A (Note ) BNA (Note ) to + Full Ld S7 P.9 ISL8UZ (Note ) 8Z to +7 ommercial 8 Ld MSOP M8.8A ISL8FUZ (Note ) 8F to + Full 8 Ld MSOP M8.8A ISL8BZ (Note ) 8 BZ to +7 ommercial 8 Ld SOI M8.E ISL8FBZ (Note ) 8 FBZ to + Full 8 Ld SOI M8.E ISL8RZ (Note ) Z to +7 ommercial 8 Ld mmxmm DFN L8.xJ ISL8FRZ (Note ) F to + Full 8 Ld mmxmm DFN L8.xJ ISL8BZ (Note ) 8 BZ to +7 ommercial Ld SOI MDP7 ISL8FBZ (Note ) 8 FBZ to + Full Ld SOI MDP7 ISL8VZ (Note ) 8 VZ to +7 ommercial Ld TSSOP MDP ISL8FVZ (Note ) 8 FVZ to + Full Ld TSSOP MDP NOTES:. Add T* suffix for tape and reel. Please refer to TB7 for details on reel specifications.. Please refer to TB7 for details on reel specifications.. These Intersil Pbfree plastic packaged products employ special Pbfree material sets, molding compounds/die attach materials, and % matte tin plate plus anneal (e termination finish, which is RoHS compliant and compatible with both SnPb and Pbfree soldering operations). Intersil Pbfree products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pbfree requirements of IP/JEDE J STD.. For Moisture Sensitivity Level (MSL), please see device information page for ISL8, ISL8, ISL8. For more information on MSL please see Tech Brief TB.. The part marking is located on the bottom of the part. FN7 Rev 7. Page of 9

3 ISL8, ISL8, ISL8 Pin onfigurations ISL8 ( LD SOT) ISL8 (8 LD SOI) OUT V+ N 8 N V + IN 7 V+ IN+ IN IN+ + OUT V N ISL8 ( LD S7) ISL8 (8 LD MSOP, SOI) IN+ V + V+ OUT_A IN_A V+ OUT_B IN OUT IN+_A + IN_B V IN+_B ISL8 (8 LD DFN) ISL8 ( LD TSSOP, SOI) OUT_A 8 V+ OUT_A OUT_D IN_A IN+_A PAD 7 OUT_B IN_B IN_A IN+_A + + IN_D IN+_D V IN+_B V+ V IN+_B IN+_ IN_B IN_ OUT_B 7 8 OUT_ FN7 Rev 7. Page of 9

4 Pin Descriptions ISL8 ( Ld SOT) ISL8 (8 Ld SOI) ISL8 ( LD S7) ISL8 (8 Ld MSOP, SOI, DFN) ISL8 ( Ld TSSOP, SOI) PIN NAME FUNTION EQUIVALENT IRUIT IN+ IN+_A IN+_B IN+_ IN+_D Noninverting input IN V+ + IN+ V Negative supply IN Inverting input (See ircuit ) 9 IN_A IN_B IN_ IN_D OUT OUT_A OUT_B OUT_ OUT_D Output V ircuit V+ OUT ircuit 7 8 V+ Positive supply,, 8 N Not onnected This pin is not electrically connected internally. PAD Paddle Thermal Pad. onnect to most negative supply. DFN packages only. V FN7 Rev 7. Page of 9

5 Absolute Maximum Ratings Max Supply Voltage V+ to V V Max Voltage VIN to GND (V.V) to (V+ +.V)V Max Input Differential Voltage V Max Input urrent ma Max Voltage VOUT to GND (s) (V.V) to (V+ +.V)V ESD Tolerance (ISL8) Human Body Model (Tested at JESDAF) V Machine Model (Tested at JESDAB) V harged Device Model (Tested at JESDD) V ESD Tolerance (ISL8, ISL8) Human Body Model (Tested at JESDAF) V Machine Model (Tested at JESDAB) V harged Device Model (Tested at JESDD) V LatchUp (Passed Per JESD78B) Thermal Information Thermal Resistance (Typical) JA ( /W) J ( /W) Ld SOT (Notes, 8) Ld S7 (Notes, 8) Ld SOI (ISL8) (Notes, 8) Ld MSOP (Notes, 8) Ld SOI (ISL8) (Notes, 8) Ld DFN (Notes 7, 9) Ld TSSOP (Notes, 8) Ld SOI (Notes, 8) Maximum Storage Temperature Range to + PbFree Reflow Profile see link below Operating onditions Temperature Range Full Grade Devices to + ommercial Grade Devices to +7 AUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES:. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB79 for details. 7. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features. See Tech Brief TB For J, the case temp location is taken at the package top center. 9. For J, the case temp location is the center of the exposed metal pad on the package underside. Electrical Specifications V + = V, V = V, V M =.V, T A = +, R L = kω, unless otherwise specified. Boldface limits apply over the entire operating temperature range. PARAMETER DESRIPTION ONDITIONS MIN (Note ) TYP MAX (Note ) UNIT D SPEIFIATIONS V OS Input Offset Voltage Vs =.8V to.v ± µv Vs =.8 to.v; T = to +7 Vs =.8V to.v; T = to µv µv TV OS Input Offset Voltage Temperature oefficient nv/ I OS Input Offset urrent pa TI OS Input Offset urrent Temperature oefficient. pa/ I B Input Bias urrent T = to +7 pa T = to pa ommon Mode Input Voltage Range Guaranteed by MRR.. V MRR ommon Mode Rejection Ratio V M =.V to.v db db PSRR Power Supply Rejection Ratio Vs =.V to.v 8 db db V OH Output Voltage Swing, High.9.98 V V OL Output Voltage Swing, Low 8 mv FN7 Rev 7. Page of 9

6 Electrical Specifications V + = V, V = V, V M =.V, T A = +, R L = kω, unless otherwise specified. Boldface limits apply over the entire operating temperature range. (ontinued) PARAMETER DESRIPTION ONDITIONS MIN (Note ) TYP MAX (Note ) UNIT A OL Open Loop Gain R L = MΩ db V + Supply Voltage Guaranteed by V OS.8. V I S Supply urrent, Per Amplifier R L = OPEN µa µa I S+ Output Source Short ircuit urrent R L = Short V ma I S Output Sink Short ircuit urrent R L = Short V+ ma A SPEIFIATIONS GBWP Gain Bandwidth Product A V =, R F = kω R G =kω, R L = kω to V M khz e N V PP PeaktoPeak Input Noise Voltage f =.Hz to Hz. µv PP e N Input Noise Voltage Density f = khz nv/ (Hz) i N Input Noise urrent Density f = khz 7 fa/ (Hz) f = Hz 8 fa/ (Hz) in Differential Input apacitance f = MHz. pf TRANSIENT RESPONSE ommon Mode Input apacitance. pf SR Positive Slew Rate V OUT = V to V, R L = kω. V/µs Negative Slew Rate. V/µs t r, t f, Small Signal Rise Time, t r % to 9% A V = +, V OUT =.V PP R F = Ω,. µs Fall Time, t f % to 9% R L = kω, L =.pf. µs t r, t f Large Signal Rise Time, t r % to 9% A V = +, V OUT = V PP R F =Ω, µs Fall Time, t f % to 9% R L = kω, L =.pf µs t s Settling Time to.%, V PP Step A V = +, R F = Ω, R L =kω, L =.pf µs t recover Output Overload Recovery Time, Recovery to 9% of Output Saturation A V = +, R F = kω, R L =Open L =.7pF. µs NOTE:. ompliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. FN7 Rev 7. Page of 9

7 n Typical Performance urves V+ = V, V = V, V M =.V, R L = Open, T = +, unless otherwise specified. INPUT BIAS URRENT (pa) V S = ±.V V S = ±.9V INPUT BIAS URRENT (pa) V S = ±.9V V S = ±.V 7 TEMPERATURE ( ) FIGURE. I B + vs TEMPERATURE 7 TEMPERATURE ( ) FIGURE. I B vs TEMPERATURE SUPPLY URRENT (µa) PER AMPLIFIER SUPPLY URRENT (µa) PER AMPLIFIER 7 TEMPERATURE ( ) 7 TEMPERATURE ( ) FIGURE. SUPPLY URRENT vs TEMPERATURE, Vs = ±.9V FIGURE. SUPPLY URRENT vs TEMPERATURE, Vs = ±.V SUPPLY URRENT (µa) V IN = V R L = OPEN SUPPLY VOLTAGE (V) OPEN LOOP GAIN (db)/phase ( ) R L = M L = pf SIMULATION.m m m m GAIN FREQUENY (Hz) PHASE k k k M M FIGURE 7. SUPPLY URRENT vs SUPPLY VOLTAGE FIGURE 8. FREQUENY RESPONSE vs OPEN LOOP GAIN, R L =MΩ FN7 Rev 7. Page 7 of 9

8 Typical Performance urves V+ = V, V = V, V M =.V, R L = Open, T = +, unless otherwise specified. NORMALIZED GAIN (db) R L = k R L = k R L = 9.9k R L = k R L = OPEN V S = ±.9V 7 L =.7pF A V = + 8 V OUT = mv PP 9 k k k M M FREQUENY (Hz) FIGURE 9. GAIN vs FREQUENY vs R L, V S = ±.9V NORMALIZED GAIN (db) 7 8 R L = k V S = ±.V L =.7pF A V = + V OUT = mv PP R L = k R L = 9.9k R L = k R L = OPEN 9 k k k M M FREQUENY (Hz) FIGURE. GAIN vs FREQUENY vs R L, V S = ±.V GAIN (db) R F = R G = k R F = R G = k V S = ±.V R F = R G = k R L = k L =.7pF A V = + V OUT = mv PP k k k M M FREQUENY (Hz) FIGURE. GAIN vs FREQUENY vs FEEDBAK RESISTOR VALUES R F /R G NORMALIZED GAIN (db) V OUT = V V OUT = mv V OUT = mv 7 V S = ±.V R L = OPEN V OUT = mv 8 L =.7pF A V = V OUT = mv 9 k k k M M FREQUENY (Hz) FIGURE. GAIN vs FREQUENY vs V OUT GAIN (db) 7 A V = R G =, R F = k A V = R G = k, R F = k V+ = V L =.7pF A V = R L = k V OUT = mv PP R G = k, R F = k A V = R G = OPEN, R F = k k k M M FREQUENY (Hz) NORMALIZED GAIN (db) V S = ±.9V V S = ±.V V S = ±.7V R L = k 7 L =.7pF 8 A V = + V OUT = mv PP 9 k k k M M FREQUENY (Hz) FIGURE. FREQUENY RESPONSE vs LOSED LOOP GAIN FIGURE. GAIN vs FREQUENY vs SUPPLY VOLTAGE FN7 Rev 7. Page 8 of 9

9 Typical Performance urves V+ = V, V = V, V M =.V, R L = Open, T = +, unless otherwise specified. NORMALIZED GAIN (db) 8. L = 8pF. L = 7pF. L = pf... L = pf. R L = pf L = k. L =.7pF V S = ±.V. A R L = k L =.7pF V = 8 V A V = +. OUT = V PP V OUT = mv PP k k k M M FREQUENY (Hz) TIME (µs) FIGURE. GAIN vs FREQUENY vs L FIGURE. LARGE SIGNAL STEP RESPONSE (V) SIGNAL (V) SIGNAL (V)... R L = k L =.7pF A V = V OUT = V PP SIGNAL (V).8... R L = k L =.7pF A V = V OUT = mv PP TIME (µs) FIGURE 7. LARGE SIGNAL STEP RESPONSE (V) TIME (µs) FIGURE 8. SMALL SIGNAL STEP RESPONSE (mv)..99 V S = V R L = kω V S = V R L = kω V OH (V) V OL (mv) TEMPERATURE ( ) 7 TEMPERATURE ( ) FIGURE 9. V OH vs TEMPERATURE FIGURE. V OL vs TEMPERATURE FN7 Rev 7. Page 9 of 9

10 Typical Performance urves V+ = V, V = V, V M =.V, R L = Open, T = +, unless otherwise specified. ROSSTALK (db) 8 V s = ±.9V R L = OPEN L =.7pF A V = V OUT = V PP ROSSTALK (db) 8 V s = ±.V R L = OPEN L =.7pF A V = V OUT = V PP k k k M FREQUENY (Hz) FIGURE. ROSSTALK vs FREQUENY, V S = ±.9V k k k M FREQUENY (Hz) FIGURE. ROSSTALK vs FREQUENY, V S = ±.V FN7 Rev 7. Page of 9

11 Applications Information Functional Description The ISL8, ISL8 and ISL8 are low offset and low drift operational amplifiers with a very high open loop gain (db) and railtorail input/output. They are designed to operate on a single supply range of.8v to.v or a dual supply range of ±.9V to ±.7V while consuming only µa of supply current per channel. The ISL8, ISL8 and ISL8 have a khz gainbandwidth. The high open loop gain, low offset voltage, high bandwidth and low /f noise make the ISL8, ISL8 and ISL8 ideal for precision applications. Railtorail Input and Output (RRIO) The RRIO MOS amplifier uses parallel input PMOS and NMOS that enable the inputs to swing mv beyond either supply rail. The inverting and noninverting inputs do not have backtoback input clamp diodes and are capable of maintaining high input impedance at high differential input voltages. This is effective in eliminating output distortion caused by high slew rate input signals. The output stage uses common source connected PMOS and NMOS devices to achieve railtorail output drive capability with ma current limit and the capability to swing to within mv of either rail while driving a kω load. IN+ and IN Protection All input terminals have internal ESD protection diodes to both positive and negative supply rails, limiting the input voltage to within one diode beyond the supply rails. For applications in which either input is expected to exceed the rails by.v, an external series resistor must be used to ensure the input currents never exceed ma (see Figure ). V IN R IN + R L V OUT Layout Guidelines for High Impedance Inputs To achieve maximum performance from the high input impedance and low offset voltage of the ISL8, ISL8 and ISL8 amplifiers, care should be taken in the circuit board layout. The P board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board reduces surface moisture and provides a humidity barrier, reducing parasitic resistance on the board. High Gain, Precision Doupled Amplifier The circuit in Figure implements a singlestage Dcoupled amplifier with an input D sensitivity of under nv that is only possible using a low VOS amplifier with high open loop gain. High gain D amplifiers operating from low voltage supplies are not practical using typical low offset precision op amps. For example, consider a typical precision amplifier in a gain of kv/v. A low offset op amp with ±µv V OS and.µv/ offset drift yields a D error of >V, with an additional mv/ of temperaturedependent error. This amount of error makes it difficult to resolve D input voltage changes in the mv range. The ±µv max V OS and nv/ temperature drift of the ISL8, ISL8, and ISL8 produce a temperaturestable maximum D output error of only ±mv, with a maximum output temperature drift of.mv/. The additional benefit of a very low /f noise corner frequency and some feedback filtering allows D voltages and voltage fluctuations well below µv to be easily detected with a simple, singlestage amplifier. V IN MΩ Ω + F.8µF MΩ +.V Ω.V R L V OUT A L = kv/v FIGURE. INPUT URRENT LIMITING FIGURE. HIGH GAIN, PREISION DOUPLED AMPLIFIER opyright Intersil Americas LL. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see FN7 Rev 7. Page of 9

12 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION HANGE FN7.7 Ordering information table on page : Added part number ISL8FRZ Absolute Maximum Ratings table on page : changed Max Voltage VOUT to GND (s) : from ±.V to: (V.V) to (V+ +.V)V.. November, FN7. Removed oming Soon from ISL8FBZ in Ordering Information on page. November 8, FN7. Removed oming Soon from ISL8FHZT7, ISL8FEZT7, ISL8BZ, ISL8FBZ, ISL8FUZ, ISL8FRZ, ISL8FVZ, ISL8FRZ, ISL8BZ and ISL8FBZ in Ordering Information on page. February, FN7. Removed oming Soon from ISL8FBZ in Ordering Information on page. June, FN7. hanged minimum operating supply voltage from +.V to +.8V throughout datasheet. Modified Electrical Specifications table, beginning on page, for all specs related at +.V to +.8V, and all other text references accordingly. On page, paragraph, last sentence: changed from All devices operate over the temperature range of to +. to ommercial temp range devices operate over the temperature range of to 7. Full temp range devices operate over the temperature range of to. On page, Ordering Information: added oming Soon to all devices with to temp range and to ISL8BZ at to +7 temp range. March, FN7. Ordering Information Table: Removed all 'oming Soon' under part numbers (except for ISL8FBZ and ISL8FRZ), added part markings for all grade parts. Added new data column called 'TEMPERATURE GRADE' to distinguish between 'ommercial' and 'Full' temp grades. Electrical Specifications Table: added new text to common conditions: Boldface limits apply over the entire operating temperature range. This note allows bold face limits to apply both to commercial and full grade temp devices. Added over temperature to 7 spec for Vos in addition to to Vos spec. Original Vos spec of.8µv for to is a typo based on a TVos of nv/. to limit corrected as µv over temp. December 7, FN7. orrected Thermals for DFN package in Tja from to, Tjc from 9 to December, Removed Part Markings from Full temp grade parts and changed to TBD until availability is validated. December, Updated front page text to add DFN packaging and extended temp range to + Removed previous Ib vs Temp plot and added new to + Ib vs Temp plot on front page. Updated ordering information table by adding a full temp range option to all parts and temp range column. Also added in DFN part to ordering table. All full temp parts are stamped oming Soon. Added DFN package to Pin onfigurations table. Added to + temp range under Operating onditions page. Added the testing standards performance information to the ESD ratings in Abs Max Table Added new Input Bias urrent Ib spec of 7pA MIN/MAX in Electrical Spec table for to + temp range Revised Note for Electrical Spec table as: ompliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. Updated all curves in the datasheet with to +7 temp range to to + temp range. Added DFN package L8.xJ outline drawing to the end of datasheet. October 9, On page changed Supply urrent, Per Amplifier from a typical of 8µA to µa to comply with front page. August 7, FN7. Initial Release About Intersil Intersil orporation is a leader in the design and manufacture of highperformance analog, mixedsignal and power management semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal computing and highend consumer markets. For more information about Intersil, visit our website at For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at You may report errors or suggestions for improving this datasheet by visiting Reliability reports are also available from our website at FN7 Rev 7. Page of 9

13 Small Outline Transistor Plastic Packages (S7) E A A SEATING PLANE e D e L. (.8) M L WITH PLATING X q X q c b VIEW A BASE METAL L L. (.) L L b b R a R VIEW SEATING PLANE c GAUGE PLANE L E P.9 LEAD SMALL OUTLINE TRANSISTOR PLASTI PAKAGE INHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A...8. A.... A b.... b.... c c D E E.... e. Ref. Ref e. Ref. Ref L..8.. L.7 Ref.. Ref. L. BS. BS o 8 o o 8 o N R.. R.... Rev. 7/7 NOTES:. Dimensioning and tolerances per ASME Y.M99.. Package conforms to EIAJ S7 and JEDE MOAA.. Dimensions D and E are exclusive of mold flash, protrusions, or gate burrs.. Footlength L measured at reference to gauge plane.. N is the number of terminal positions.. These Dimensions apply to the flat section of the lead between.8mm and.mm from the lead tip. 7. ontrolling dimension: MILLIMETER. onverted inch dimensions are for reference only..mm.7mm.mm.mm TYPIAL REOMMENDED LAND PATTERN FN7 Rev 7. Page of 9

14 Package Outline Drawing P.A LEAD SMALL OUTLINE TRANSISTOR PLASTI PAKAGE Rev, / A.9 D.8. PIN INDEX AREA. D x.9.8. x. (.) B. ±.. M AB D SEE DETAIL X END VIEW TYP ( PLS).9. x AB H. MAX. ±.. SEATING PLANE (.) GAUGE PLANE SIDE VIEW...±. DETAIL "X" (.) (.) NOTES: (.).. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to ASME Y.M99. (.9) (.9) TYPIAL REOMMENDED LAND PATTERN.... Dimension is exclusive of mold flash, protrusions or gate burrs. Foot length is measured at reference to guage plane. This dimension is measured at Datum H. Package conforms to JEDE MO78AA. FN7 Rev 7. Page of 9

15 Package Outline Drawing M8.8A 8 LEAD MINI SMALL OUTLINE PLASTI PAKAGE (MSOP) Rev, 9/9.±. A 8. A B.±..9±. DETAIL "X". Max PIN# ID B. BS SIDE VIEW.8 ±..9 BS H.8±.9 GAUGE PLANE. SEATING PLANE. +.7/.8.8 A B. ±... ±. ± SIDE VIEW DETAIL "X".8.. NOTES:. Dimensions are in millimeters.. Dimensioning and tolerancing conform to JEDE MO87AA and AMSE Y.m99... Plastic or metal protrusions of.mm max per side are not included.. TYPIAL REOMMENDED LAND PATTERN... Plastic interlead protrusions of.mm max per side are not included. Dimensions D and E are measured at Datum Plane H.. This replaces existing drawing # MDP MSOP 8L. FN7 Rev 7. Page of 9

16 Thin Shrink Small Outline Package Family (TSSOP) E. M A B E B SEATING PLANE. N LEADS e N D b (N/)+ SIDE VIEW SEE DETAIL X (N/) A PIN # I.D.. B A X N/ LEAD TIPS.. M A B H MDP THIN SHRINK SMALL OUTLINE PAKAGE FAMILY MILLIMETERS SYMBOL LD LD LD LD 8 LD TOLERANE A..... Max A..... ±. A ±. b /. c /. D ±. E..... Basic E..... ±. e..... Basic L..... ±. L..... Reference Rev. F /7 NOTES:. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed.mm per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.mm per side.. Dimensions D and E are measured at datum Plane H.. Dimensioning and tolerancing per ASME Y.M99. c END VIEW L A A A DETAIL X L 8 GAUGE PLANE. FN7 Rev 7. Page of 9

17 Small Outline Package Family (SO) A D h X N (N/)+ E E PIN # I.D. MARK c A SEE DETAIL X B. M A B (N/) L e H A SEATING PLANE GAUGE PLANE... M A B b A DETAIL X L ± MDP7 SMALL OUTLINE PAKAGE FAMILY (SO) INHES SO SO (. ) SO SO SO8 SYMBOL SO8 SO (. ) (SOL) (SOL) (SOL) (SOL8) TOLERANE NOTES A MAX A ±. A ±. b ±. c ±. D ±., E ±.8 E ±., e Basic L ±.9 L Basic h Reference N 8 8 Reference Rev. M /7 NOTES:. Plastic or metal protrusions of. maximum per side are not included.. Plastic interlead protrusions of. maximum per side are not included.. Dimensions D and E are measured at Datum Plane H.. Dimensioning and tolerancing per ASME Y.M99 FN7 Rev 7. Page 7 of 9

18 Package Outline Drawing M8.E 8 LEAD NARROW BODY SMALL OUTLINE PLASTI PAKAGE Rev, 8/9.9 ±. A DETAIL "A". ±. B. ±..9 ±. PIN NO. ID MARK.7. ±.7 (.) x ±. MAB SIDE VIEW B.7 MAX. ±..7 ±.7 SIDE VIEW A. GAUGE PLANE SEATING PLANE.. ±. (.7) (.) DETAIL "A" (.) NOTES:. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. (.)..... Dimensioning and tolerancing conform to AMSE Y.m99. Unless otherwise specified, tolerance : Decimal ±. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed.mm per side. The pin # identifier may be either a mold or mark feature. Reference to JEDE MS. TYPIAL REOMMENDED LAND PATTERN FN7 Rev 7. Page 8 of 9

19 Package Outline Drawing L8.xJ 8 LEAD DUAL FLAT NOLEAD PLASTI PAKAGE Rev 9/9 X.9. A X. (X). B /. PIN INDEX AREA 8X. ±..8 +./. PIN # INDEX AREA 8X.. M A B BOTTOM VIEW (.8 ) SEE DETAIL "X" (.9) Max...8 ( 8X.) SIDE VIEW (.) (.8 ) PIN. REF (x.) ( 8 X.). MIN.. MAX. TYPIAL REOMMENDED LAND PATTERN DETAIL "X" NOTES: Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y.m99. Unless otherwise specified, tolerance : Decimal ±. Dimension applies to the metallized terminal and is measured between.mm and.mm from the terminal tip. Tiebar shown (if present) is a nonfunctional feature. The configuration of the pin # identifier is optional, but must be located within the zone indicated. The pin # identifier may be either a mold or mark feature. FN7 Rev 7. Page 9 of 9