Common Number Systems

Transcription

1 Number Systems

2 Common Number Systems System Base Symbols Used by humans? Used in computers? Decimal 10 0, 1, 9 Yes No Binary 2 0, 1 No Yes Octal 8 0, 1, 7 No No Hexadecimal 16 0, 1, 9, A, B, F No No

3 Conversion Among Bases The possibilities: Decimal Octal Binary Hexadeci mal Quick Example = = 31 8 = Base

4 Technique Binary to Decimal Multiply each bit by 2 n, where n is the weight of the bit The weight is the position of the bit, starting from 0 on the right Add the results

5 Example Bit => 1 x 2 0 = 1 1 x 2 1 = 2 0 x 2 2 = 0 1 x 2 3 = 8 0 x 2 4 = 0 1 x 2 5 =

6 Octal to Decimal Technique Multiply each bit by 8 n, where n is the weight of the bit The weight is the position of the bit, starting from 0 on the right Add the results

7 Example => 4 x 8 0 = 4 2 x 8 1 = 16 7 x 8 2 =

8 Hexadecimal to Decimal Technique Multiply each bit by 16 n, where n is the weight of the bit The weight is the position of the bit, starting from 0 on the right Add the results

9 Example ABC 16 => C x 16 0 = 12 x 1 = 12 B x 16 1 = 11 x 16 = 176 A x 16 2 = 10 x 256 =

10 Decimal to Binary Technique Divide by two, keep track of the remainder First remainder is bit 0 (LSB, least-significant bit) Second remainder is bit 1 Etc.

11 Example =? =

12 Octal to Binary Decimal Octal Binary Hexadecimal

13 Octal to Binary Technique Convert each octal digit to a 3-bit equivalent binary representation

14 Example =? =

15 Hexadecimal to Binary Decimal Octal Binary Hexadecimal

16 Hexadecimal to Binary Technique Convert each hexadecimal digit to a 4-bit equivalent binary representation

17 Example 10AF 16 =? A F AF 16 =

18 Decimal to Octal Decimal Octal Binary Hexadecimal

19 Decimal to Octal Technique Divide by 8 Keep track of the remainder

20 Example =? =

21 Decimal to Hexadecimal Decimal Octal Binary Hexadecimal

22 Decimal to Hexadecimal Technique Divide by 16 Keep track of the remainder

23 Example =? = D = 4D2 16

24 Binary to Octal Decimal Octal Binary Hexadecimal

25 Binary to Octal Technique Group bits in threes, starting on right Convert to octal digits

26 Example =? =

27 Binary to Hexadecimal Decimal Octal Binary Hexadecimal

28 Binary to Hexadecimal Technique Group bits in fours, starting on right Convert to hexadecimal digits

29 Example =? B B = 2BB 16

30 Octal to Hexadecimal Decimal Octal Binary Hexadecimal

31 Octal to Hexadecimal Technique Use binary as an intermediary

32 Example =? E = 23E 16

33 Hexadecimal to Octal Decimal Octal Binary Hexadecimal

34 Hexadecimal to Octal Technique Use binary as an intermediary

35 Example 1F0C 16 =? 8 1 F 0 C F0C 16 =

36 Common Powers (1 of 2) Base 10 Power Preface Symbol pico p 10-9 nano n 10-6 micro 10-3 milli m 10 3 kilo k 10 6 mega M 10 9 giga G tera T Value

37 Common Powers (2 of 2) Base 2 Power Preface Symbol 2 10 kilo k 2 20 mega M 2 30 Giga G Value What is the value of k, M, and G? In computing, particularly w.r.t. memory, the base-2 interpretation generally applies

38 Binary Addition (1 of 2) Two 1-bit values A B A + B two

39 Binary Addition (2 of 2) Two n-bit values Add individual bits Propagate carries E.g.,

40 Multiplication (1 of 3) Decimal (just for fun) 35 x pp. 39

41 Multiplication (3 of 3) Binary, two n-bit values As with decimal values E.g., 1110 x

42 Fractions Decimal to decimal (just for fun) 3.14 => 4 x 10-2 = x 10-1 = x 10 0 = pp

43 Fractions Binary to decimal => 1 x 2-4 = x 2-3 = x 2-2 = x 2-1 = x 2 0 = x 2 1 = pp

44 Fractions Decimal to binary x x x x x x etc. p. 50

45 Boolean Algebra

46 Introduction 1854: Logical algebra was published by George Boole known today as Boolean Algebra It s a convenient way and systematic way of expressing and analyzing the operation of logic circuits. 1938: Claude Shannon was the first to apply Boole s work to the analysis and design of logic circuits.

47 Boolean Operations & Expressions Variable a symbol used to represent a logical quantity. Complement the inverse of a variable and is indicated by a bar over the variable. Literal a variable or the complement of a variable.

48 Laws & Rules of Boolean Algebra The basic laws of Boolean algebra: The commutative laws The associative laws The distributive laws

49 Commutative Laws The commutative law of addition for two variables is written as: A+B = B+A A B A+B B A B+A The commutative law of multiplication for two variables is written as: AB = BA A B AB B A B+A

50 Associative Laws The associative law of addition for 3 variables is written as: A+(B+C) = (A+B)+C A B C B+C A+(B+C) The associative law of multiplication for 3 variables is written as: A(BC) = (AB)C A B C A+B (A+B)+C A B C BC A(BC) A B C AB (AB)C

51 Distributive Laws The distributive law is written for 3 variables as follows: A(B+C) = AB + AC B C A B+C X A B A C AB AC X X=A(B+C) X=AB+AC

52 Rules of Boolean Algebra A A A A A A A A A A A BC A C A B A B A AB A A AB A A A A A A A A ) )( 12.(

53 DeMorgan s Theorems DeMorgan s theorems provide mathematical verification of: the equivalency of the NAND and negative-or gates the equivalency of the NOR and negative-and gates.

54 DeMorgan s Theorems The complement of two or more ANDed variables is equivalent to the OR of the complements of the individual variables. NAND X Y Negative-OR X Y The complement of two or more ORed variables is equivalent to the AND of the complements of the individual variables. NOR X Y Negative-AND X Y

55 DeMorgan s Theorems (Exercises) Apply DeMorgan s theorems to the expressions: X Y Z X Y Z X Y Z W X Y Z

56 DeMorgan s Theorems (Exercises) Apply DeMorgan s theorems to the expressions: ( A B C) D ABC DEF AB CD EF A BC D( E F )

57 Boolean Analysis of Logic Circuits Boolean algebra provides a concise way to express the operation of a logic circuit formed by a combination of logic gates so that the output can be determined for various combinations of input values.

58 Boolean Expression for a Logic Circuit To derive the Boolean expression for a given logic circuit, begin at the left-most inputs and work toward the final output, writing the expression for each gate. C D B CD B+CD A A(B+CD)

59 Constructing a Truth Table for a Logic Circuit Once the Boolean expression for a given logic circuit has been determined, a truth table that shows the output for all possible values of the input variables can be developed. Let s take the previous circuit as the example: A(B+CD) There are four variables, hence 16 (2 4 ) combinations of values are possible.

60 Constructing a Truth Table for a Logic Circuit Evaluating the expression To evaluate the expression A(B+CD), first find the values of the variables that make the expression equal to 1 (using the rules for Boolean add & mult). In this case, the expression equals 1 only if A=1 and B+CD=1 because A(B+CD) = 1 1 = 1

61 Constructing a Truth Table for a Logic Circuit Evaluating the expression (cont ) Now, determine when B+CD term equals 1. The term B+CD=1 if either B=1 or CD=1 or if both B and CD equal 1 because B+CD = 1+0 = 1 B+CD = 0+1 = 1 B+CD = 1+1 = 1 The term CD=1 only if C=1 and D=1

62 Constructing a Truth Table for a Logic Circuit Evaluating the expression (cont ) Summary: A(B+CD)=1 When A=1 and B=1 regardless of the values of C and D When A=1 and C=1 and D=1 regardless of the value of B The expression A(B+CD)=0 for all other value combinations of the variables.

63 Constructing a Truth Table for a Logic Circuit Putting the results in truth table format A(B+CD)=1 When A=1 and B=1 regardless of the values of C and D When A=1 and C=1 and D=1 regardless of the value of B INPUTS OUTPUT A B C D A(B+CD)

64 Karnaugh Maps Boolean algebra helps us simplify expressions and circuits Karnaugh Map: A graphical technique for simplifying a Boolean expression into either form: minimal sum of products (MSP) minimal product of sums (MPS) Goal of the simplification. There are a minimal number of product/sum terms Each term has a minimal number of literals Circuit-wise, this leads to a minimal two-level implementation

65 Re-arranging the Truth Table A two-variable function has four possible minterms. We can rearrange these minterms into a Karnaugh map x y minterm 0 0 x y 0 1 x y 1 0 xy 1 1 xy Now we can easily see which minterms contain common literals Minterms on the left and right sides contain y and y respectively Minterms in the top and bottom rows contain x and x respectively Y X Y x y x y 1 xy xy X x y x y 1 xy xy Y Y X x y x y X xy xy

66 Karnaugh Map Simplifications Imagine a two-variable sum of minterms: x y + x y Both of these minterms appear in the top row of a Karnaugh map, which means that they both contain the literal x x y + x y = x (y + y) [ Distributive ] = x 1 [ y + y = 1 ] = x [ x 1 = x ] x y Y x y X xy xy What happens if you simplify this expression using Boolean algebra?

67 More Two-Variable Examples Another example expression is x y + xy Both minterms appear in the right side, where y is uncomplemented Y Thus, we can reduce x y + xy to just y How about x y + x y + xy? We have x y + x y in the top row, corresponding to x There s also x y + xy in the right side, corresponding to y This whole expression can be reduced to x + y x y Y x y X xy xy x y x y X xy xy

68 A Three-Variable Karnaugh Map For a three-variable expression with inputs x, y, z, the arrangement of minterms is more tricky: YZ x y z x y z x yz x yz X 1 xy z xy z xyz xyz X YZ m 0 m 1 m 3 m 2 1 m 4 m 5 m 7 m 6 x y z x y z x yz x yz X xy z xy z xyz xyz Z Y Another way to label the K-map (use whichever you like): Y m 0 m 1 m 3 m 2 X m 4 m 5 m 7 m 6 Z

69 Why the funny ordering? With this ordering, any group of 2, 4 or 8 adjacent squares on the map contains common literals that can be factored out Y x y z x y z x yz x yz X xy z xy z xyz xyz Z x y z + x yz = x z(y + y) = x z 1 = x z Adjacency includes wrapping around the left and right sides: Y x y z x y z x yz x yz X xy z xy z xyz xyz Z x y z + xy z + x yz + xyz = z (x y + xy + x y + xy) = z (y (x + x) + y(x + x)) = z (y +y) = z We ll use this property of adjacent squares to do our simplifications.

70 K-maps From Truth Tables We can fill in the K-map directly from a truth table The output in row i of the table goes into square m i of the K-map Remember that the rightmost columns of the K-map are switched x y z f (x,y,z) X Z Y Y m 0 m 1 m 3 m 2 X m 4 m 5 m 7 m 6 Z

71 Reading the MSP from the K-map You can find the minimal SoP expression Each rectangle corresponds to one product term The product is determined by finding the common literals in that Y rectangle X x y z x y z x yz x yz X xy z xy z xyz xyz y z Z Z Y xy F(x,y,z)= y z + xy 71

72 Grouping the Minterms Together The most difficult step is grouping together all the 1s in the K-map Make rectangles around groups of one, two, four or eight 1s All of the 1s in the map should be included in at least one rectangle Do not include any of the 0s Each group corresponds to one product term Y X Z 72

73 For the Simplest Result Make as few rectangles as possible, to minimize the number of products in the final expression. Make each rectangle as large as possible, to minimize the number of literals in each term. Rectangles can be overlapped, if that makes them larger. 73

74 K-map Simplification of SoP Expressions Let s consider simplifying f(x,y,z) = xy + y z + xz You should convert the expression into a sum of minterms form, The easiest way to do this is to make a truth table for the function, and then read off the minterms You can either write out the literals or use the minterm shorthand Here is the truth table and sum of minterms for our example: x y z f(x,y,z) f(x,y,z) = x y z + xy z + xyz + xyz = m 1 + m 5 + m 6 + m 7

75 Unsimplifying Expressions You can also convert the expression to a sum of minterms with Boolean algebra Apply the distributive law in reverse to add in missing variables. Very few people actually do this, but it s occasionally useful. xy + y z + xz = (xy 1) + (y z 1) + (xz 1) = (xy (z + z)) + (y z (x + x)) + (xz (y + y)) = (xyz + xyz) + (x y z + xy z) + (xy z + xyz) = xyz + xyz + x y z + xy z = m 1 + m 5 + m 6 + m 7 In both cases, we re actually unsimplifying our example expression The resulting expression is larger than the original one! But having all the individual minterms makes it easy to combine them together with the K-map

76 Making the Example K-map In our example, we can write f(x,y,z) in two equivalent ways f(x,y,z) = x y z + xy z + xyz + xyz x y z x y z x yz x yz X xy z xy z xyz xyz Z Y f(x,y,z) = m 1 + m 5 + m 6 + m 7 Y m 0 m 1 m 3 m 2 X m 4 m 5 m 7 m 6 Z In either case, the resulting K-map is shown below Y X Z 76

77 Practice K-map 1 Simplify the sum of minterms m 1 + m 3 + m 5 + m 6 Y X Z Y m 0 m 1 m 3 m 2 X m 4 m 5 m 7 m 6 Z 77

78 Solutions for Practice K-map 1 Here is the filled in K-map, with all groups shown The magenta and green groups overlap, which makes each of them as large as possible Minterm m 6 is in a group all by its lonesome Y X Z The final MSP here is x z + y z + xyz 78

79 K-maps can be tricky! There may not necessarily be a unique MSP. The K-map below yields two valid and equivalent MSPs, because there are two possible ways to include minterm m 7 Y X Z Y X Z y z + yz + xy Y X Z y z + yz + xz Remember that overlapping groups is possible, as shown above 79

80 Four-variable K-maps f(w,x,y,z) We can do four-variable expressions too! The minterms in the third and fourth columns, and in the third and fourth rows, are switched around. Again, this ensures that adjacent squares have common literals Grouping minterms is similar to the three-variable case, but: You can have rectangular groups of 1, 2, 4, 8 or 16 minterms You can wrap around all four sides 80

81 Four-variable K-maps Y w x y z w x y z w x yz w x yz w xy z w xy z w xyz w xyz W wxy z wxy z wxyz wxyz wx y z wx y z wx yz wx yz Z X Y m 0 m 1 m 3 m 2 m 4 m 5 m 7 m 6 m 12 m 13 m 15 m 14 X W m8 m 9 m 11 m 10 Z 81

82 Example: Simplify m 0 +m 2 +m 5 +m 8 +m 10 +m 13 The expression is already a sum of minterms, so here s the K- map: Y X W Y m 0 m 1 m 3 m 2 m 4 m 5 m 7 m 6 m 12 m 13 m 15 m 14 X W m8 m 9 m 11 m 10 Z Y X W Z Z Y w x y z w x y z w x yz w x yz w xy z w xy z w xyz w xyz W wxy z wxy z wxyz wxyz wx y z wx y z wx yz wx yz Z X We can make the following groups, resulting in the MSP x z + xy z 82

83 Five-variable K-maps f(v,w,x,y,z) V= 0 V= 1 Y m 0 m 1 m 3 m 2 m 4 m 5 m 7 m 6 m 12 m 13 m 15 m 14 X W m8 m 9 m 11 m 10 Z Y m 16 m 17 m 19 m 8 m 20 m 21 m 23 m 22 m 28 m 29 m 31 m 30 X W m24 m 25 m 27 m 26 Z 83

84 Simplify f(v,w,x,y,z)=σm(0,1,4,5,6,11,12,14,16,20,22,28,30,31) V= 0 V= 1 f = XZ Σm(4,6,12,14,20,22,28,30) + V W Y Σm(0,1,4,5) + W Y Z Σm(0,4,16,20) + VWXY Σm(30,31) + V WX YZ m11 84

85 PoS Optimization Maxterms are grouped to find minimal PoS yz expression x 0 1 x +y+z x+y+z x+y +z x+y +z x +y+z x +y+z x +y +z x +y +z 85

86 PoS Optimization F(W,X,Y,Z)= M(0,1,2,4,5) yz x 0 1 x +y+z x+y+z x+y +z x+y +z x +y+z x +y+z x +y +z x +y +z yz F(W,X,Y,Z)= Y. (X + Z) x

87 PoS Optimization from SoP F(W,X,Y,Z)= Σm(0,1,2,5,8,9,10) = M(3,4,6,7,11,12,13,14,15) F(W,X,Y,Z)= (W + X )(Y + Z )(X + Z) Or, F(W,X,Y,Z)= X Y + X Z + W Y Z Which one is the minimal one? 87

88 SoP Optimization from PoS F(W,X,Y,Z)= M(0,2,3,4,5,6) = Σm(1,7,8,9,10,11,12,13,14,15) 1 1 F(W,X,Y,Z)= W + XYZ + X Y Z

89 I don t care! You don t always need all 2 n input combinations in an n-variable function If you can guarantee that certain input combinations never occur If some outputs aren t used in the rest of the circuit We mark don t-care outputs in truth tables and K-maps with Xs. x y z f(x,y,z) X X Within a K-map, each X can be considered as either 0 or 1. You should pick the interpretation that allows for the most simplification. 89

90 Practice K-map Find a MSP for f(w,x,y,z) = m(0,2,4,5,8,14,15), d(w,x,y,z) = m(7,10,13) Y This notation means 1 that 0 0 input 1 combinations 1 1 x 0 wxyz = 0111, 1010 and 1101X 0 x 1 1 W x (corresponding to minterms m 7, m 10 and m 13 ) are Z unused. 90

91 Solutions for Practice K-map Find a MSP for: f(w,x,y,z) = m(0,2,4,5,8,14,15), d(w,x,y,z) = m(7,10,13) Y x x 1 1 X W 1 x Z f(w,x,y,z)= x z + w xy + wxy 91

92 K-map Summary K-maps are an alternative to algebra for simplifying expressions The result is a MSP/MPS, which leads to a minimal two-level circuit It s easy to handle don t-care conditions K-maps are really only good for manual simplification of small expressions... Things to keep in mind: Remember the correct order of minterms/maxterms on the K-map When grouping, you can wrap around all sides of the K-map, and your groups can overlap Make as few rectangles as possible, but make each of them as large as possible. This leads to fewer, but simpler, product terms There may be more than one valid solution 92

93 Tabulation Method STEP 1 1. Partition Prime Implicants (or minterms) According to Number of 1 s 2. Check Adjacent Classes for Cube Merging Building a New List 3. If Entry in New List Covers Entry in Current List Disregard Current List Entry 4. If Current List = New List HALT Else Current List New List New List NULL Go To Step 1

94 STEP 1 - EXAMPLE f on = {m 0, m 1, m 2, m 3, m 5, m 8, m 10, m 11, m 13, m 15 } = (0, 1, 2, 3, 5, 8, 10, 11, 13, 15) Minterm Cube

95 STEP 1 - EXAMPLE f on = {m 0, m 1, m 2, m 3, m 5, m 8, m 10, m 11, m 13, m 15 } = (0, 1, 2, 3, 5, 8, 10, 11, 13, 15) Minterm Cube Minterm Cube 0, , , , , , , , , , , , ,

96 STEP 1 - EXAMPLE f on = {m 0, m 1, m 2, m 3, m 5, m 8, m 10, m 11, m 13, m 15 } = (0, 1, 2, 3, 5, 8, 10, 11, 13, 15) Minterm Cube Minterm Cube 0, , , , , , , , , , , , , Minterm Cube 0,1,2, ,8,2, ,3,10,

97 STEP 1 - EXAMPLE f on = {m 0, m 1, m 2, m 3, m 5, m 8, m 10, m 11, m 13, m 15 } = (0, 1, 2, 3, 5, 8, 10, 11, 13, 15) Minterm Cube Minterm Cube 0, , , , , PI=D 2, , , , , PI=E 10, , PI=F 13, PI=G Minterm Cube 0,1,2, PI=A 0,8,2, PI=C 2,3,10, PI=B f on = {A,B,C,D,E,F,G} = {00--, -01-, -0-0, 0-01, -101, 1-11, 11-1}

98 STEP 2 Construct Cover Table PIs Along Vertical Axis (in order of # of literals) Minterms Along Horizontal Axis A x x x x B x x x x C x x x x D x x E x x F x x G x x NOTE: Table 4.2 in book is incomplete

99 STEP 2 Finding the Minimum Cover Extract All Essential Prime Implicants, EPI EPIs are the PI for which a Single x Appears in a Column A x x x x B x x x x C x x x x D x x E x x F x x G x x C is an EPI so: f on ={C,...} Row C and Columns 0, 2, 8, and 10 can be Eliminated Giving Reduced Cover Table Examine Reduced Table for New EPIs

100 STEP 2 Reduced Table Distinguished Column A x x x x B x x x x C x x x x D x x E x x F x x G x x Essential row A x x B x x D x x E x x F x x G x x The Row of an EPI is an Essential row The Column of the Single x in the Essential Row is a Distinguished Column

101 Row and Column Dominance If Row P has x s Everywhere Row Q Does Then Q Dominates P if P has fewer x s If Column i has x s Everywhere j Does Then j Dominates i if i has fewer x s If Row P is equal to Row Q and Row Q does not cost more than Row P, eliminate Row P, or if Row P is dominated by Row Q and Row Q Does not cost more than Row P, eliminate Row P If Column i is equal to Column j, eliminate Column i or if Column i dominates Column j, eliminate Column i

102 STEP 3 The Reduced Cover Table Initially, Columns 0, 2, 8 and 10 Removed No EPIs are Present No Row Dominance Exists A x x B x x D x x E x x F x x G x x No Column Dominance Exists This is Cyclic Cover Table Must Solve Exactly OR Use a Heuristic

103 NAND Function Implementation NAND gates can implement a simplified SumofProducts form. Constructing two level NAND-NAND gate circuits The first level is two 2-input NAND gates using ANDInvert. The second level is one 2- input NAND gate using Invert-OR. Using the NAND relationship, we

104 Logic Family Characteristics Complementary metal oxide semiconductor (CMOS) most widely used family for large-scale devices combines high speed with low power consumption usually operates from a single supply of 5 15 V excellent noise immunity of about 30% of supply voltage can be connected to a large number of gates (about 50) many forms some with t PD down to 1 ns power consumption depends on speed (perhaps 1 mw)

105 NAND Implementation (Cont.) In the implementation, note that the bubbles are on opposite ends of the same line. Thus, they can be combined and deleted: This form of the implementation is the Sum-of-Products form.

106 NOR Gates The basic positive logic NOR gate (Not-OR) is denoted by the following symbol: This is called the OR-Invert, since it is logically an OR function followed by an invert. By DeMorgan's Law we have the following Invert-AND symbol for a NOR gate:

107 General Implementations (Cont.) Given a two level implementation desired, use the previous transfromations to get it into one of the below forms. Then follow the steps to transform the function to the desired form:

108 Multi-level NAND Implementations Add inverters in two-level implementation into the cost picture Attempt to combine inverters to reduce the term count Attempt to reduce literal + tem count by factoring expression into POSOP or SOPOS

109 Transistor-transistor logic (TTL) based on bipolar transistors one of the most widely used families for small- and medium-scale devices rarely used for VLSI typically operated from 5V supply typical noise immunity about V many forms, some optimised for speed, power, etc. high speed versions comparable to CMOS (~ 1.5 ns) low-power versions down to about 1 mw/gate

110 Emitter-coupled logic (ECL) based on bipolar transistors, but removes problems of storage time by preventing the transistors from saturating very fast operation - propagation delays of 1ns or less high power consumption, perhaps 60 mw/gate low noise immunity of about V used in some high speed specialist applications, but now largely replaced by high speed CMOS

111 A Comparison of Logic Families Parameter CMOS TTL ECL Basic gate NAND/NOR NAND OR/NOR Fan-out > Power per gate (mw) 1 MHz Noise immunity Excellent Very good Good t PD (ns)

112 Complementary Metal Oxide Semiconductor A CMOS inverter

113 CMOS gates

114 CMOS logic levels and noise immunity

115 Transistor-Transistor Logic Discrete TTL inverter and NAND gate circuits

116 A basic integrated circuit TTL NAND gate

117 A standard TTL NAND gate

118 A TTL NAND gate with open collector output

119 Combinational Logic Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of input variables, logic gates, and output variables. 119

120 Analysis procedure To obtain the output Boolean functions from a logic diagram, proceed as follows: 1. Label all gate outputs that are a function of input variables with arbitrary symbols. Determine the Boolean functions for each gate output. 2. Label the gates that are a function of input variables and previously labeled gates with other arbitrary symbols. Find the Boolean functions for these gates. 3. Repeat the process outlined in step 2 until the outputs of the circuit are obtained. 4. By repeated substitution of previously defined functions, obtain the output Boolean functions in terms of input variables. 120

121 Example F 2 = AB + AC + BC; T 1 = A + B + C; T 2 = ABC; T 3 = F 2 T 1 ; F 1 = T 3 + T 2 F 1 = T 3 + T 2 = F 2 T 1 + ABC = A BC + A B C + AB C + ABC 121

122 Derive truth table from logic diagram We can derive the truth table in Table 4-1 by using the circuit of Fig

123 Design procedure 1. Table4-2 is a Code-Conversion example, first, we can list the relation of the BCD and Excess-3 codes in the truth table. 123

124 Karnaugh map 2. For each symbol of the Excess-3 code, we use 1 s to draw the map for simplifying Boolean function. 124

125 Circuit implementation z = D ; y = CD + C D = CD + (C + D) x = B C + B D + BC D = B (C + D) + B(C + D) w = A + BC + BD = A + B(C + D) 125

126 Binary Adder-Subtractor A combinational circuit that performs the addition of two bits is called a half adder. The truth table for the half adder is listed below: S: Sum C: Carry S = x y + xy C = xy 126

127 Implementation of Half-Adder 127

128 Full-Adder One that performs the addition of three bits(two significant bits and a previous carry) is a full adder. 128

129 Simplified Expressions C S = x y z + x yz + xy z + xyz C = xy + xz + yz 129

130 Full adder implemented in SOP 130

131 Another implementation Full-adder can also implemented with two half adders and one OR gate (Carry Look-Ahead adder). S = z (x y) = z (xy + x y) + z(xy + x y) = xy z + x yz + xyz + x y z C = z(xy + x y) + xy = xy z + x yz + xy 131

132 Half Subtractor Truth table Logic Circuit

133 Full Subtractor

134 Full Subtractor

135 This is also called Ripple Carry Adder,because of the construction with full adders are connected in cascade. Binary adder 135

136 Carry Propagation Fig.4-9 causes a unstable factor on carry bit, and produces a longest propagation delay. The signal from C i to the output carry C i+1, propagates through an AND and OR gates, so, for an n-bit RCA, there are 2n gate levels for the carry to propagate from input to output. 136

137 Carry Propagation Because the propagation delay will affect the output signals on different time, so the signals are given enough time to get the precise and stable outputs. The most widely used technique employs the principle of carry look-ahead to improve the speed of the algorithm. 137

138 Boolean functions P i = A i B i steady state value G i = A i B i steady state value Output sum and carry S i = P i C i C i+1 = G i + P i C i G i : carry generate C 0 = input carry P i : carry propagate C 1 = G 0 + P 0 C 0 C 2 = G 1 + P 1 C 1 = G 1 + P 1 G 0 + P 1 P 0 C 0 C 3 = G 2 + P 2 C 2 = G 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0 C 0 C 3 does not have to wait for C 2 and C 1 to propagate. 138

139 Logic diagram of carry look-ahead generator C 3 is propagated at the same time as C 2 and C

140 4-bit adder with carry lookahead Delay time of n-bit CLAA = XOR + (AND + OR) + XOR 140

141 Binary subtractor M = 1 subtractor ; M = 0 adder 141

142 4-5 Decimal adder BCD adder can t exceed 9 on each input digit. K is the carry. 142

143 Rules of BCD adder When the binary sum is greater than 1001, we obtain a non-valid BCD representation. The addition of binary 6(0110) to the binary sum converts it to the correct BCD representation and also produces an output carry as required. To distinguish them from binary 1000 and 1001, which also have a 1 in position Z 8, we specify further that either Z 4 or Z 2 must have a 1. C = K + Z 8 Z 4 + Z 8 Z 2 143

144 Implementation of BCD adder A decimal parallel adder that adds n decimal digits needs n BCD adder stages. The output carry from one stage must be connected to the input carry of the next higher-order stage. If =

145 4-6. Binary multiplier Usually there are more bits in the partial products and it is necessary to use full adders to produce the sum of the partial products. And 145

146 4-bit by 3-bit binary multiplier For J multiplier bits and K multiplicand bits we need (J X K) AND gates and (J 1) K- bit adders to produce a product of J+K bits. K=4 and J=3, we need 12 AND gates and two 4-bit adders. 146

147 Magnitude comparator The equality relation of each pair of bits can be expressed logically with an exclusive-nor function as: A = A 3 A 2 A 1 A 0 ; B = B 3 B 2 B 1 B 0 x i =A i B i +A i B i for i = 0, 1, 2, 3 (A = B) = x 3 x 2 x 1 x 0 147

148 Magnitude comparator We inspect the relative magnitudes of pairs of MSB. If equal, we compare the next lower significant pair of digits until a pair of unequal digits is reached. If the corresponding digit of A is 1 and that of B is 0, we conclude that A>B. (A>B)= A 3 B 3 +x 3 A 2 B 2 +x 3 x 2 A 1 B 1 +x 3 x 2 x 1 A 0 B 0 (A<B)= A 3 B 3 +x 3 A 2 B 2 +x 3 x 2 A 1 B 1 +x 3 x 2 x 1 A 0 B 0 148

149 Decoders The decoder is called n-to-m-line decoder, where m 2 n. the decoder is also used in conjunction with other code converters such as a BCD-to-seven_segment decoder. 3-to-8 line decoder: For each possible input combination, there are seven outputs that are equal to 0 and only one that is equal to

150 Implementation and truth table 150

151 Decoder with enable input Some decoders are constructed with NAND gates, it becomes more economical to generate the decoder minterms in their complemented form. As indicated by the truth table, only one output can be equal to 0 at any given time, all other outputs are equal to

152 Demultiplexer A decoder with an enable input is referred to as a decoder/demultiplexer. The truth table of demultiplexer is the same with decoder. A B E Demultiplexer D0 D1 D2 D3 152

153 3-to-8 decoder with enable implement the 4-to-16 decoder 153

154 Implementation of a Full Adder with a Decoder From table 4-4, we obtain the functions for the combinational circuit in sum of minterms: S(x, y, z) = (1, 2, 4, 7) C(x, y, z) = (3, 5, 6, 7) 154

155 4-9. Encoders An encoder is the inverse operation of a decoder. We can derive the Boolean functions by table 4-7 z = D 1 + D 3 + D 5 + D 7 y = D 2 + D 3 + D 6 + D 7 x = D 4 + D 5 + D 6 + D 7 155

156 Priority encoder If two inputs are active simultaneously, the output produces an undefined combination. We can establish an input priority to ensure that only one input is encoded. Another ambiguity in the octal-to-binary encoder is that an output with all 0 s is generated when all the inputs are 0; the output is the same as when D 0 is equal to 1. The discrepancy tables on Table 4-7 and Table 4-8 can resolve aforesaid condition by providing one more output to indicate that at least one input is equal to

157 V=0 no valid inputs V=1 valid inputs Priority encoder X s in output columns represent don t-care conditions X s in the input columns are useful for representing a truth table in condensed form. Instead of listing all 16 minterms of four variables. 157

158 4-input priority encoder Implementation of table x = D 2 + D 3 y = D 3 + D 1 D 2 V = D 0 + D 1 + D 2 + D 3 158

159 4-10. Multiplexers S = 0, Y = I 0 Truth Table S Y Y = S I 0 + SI 1 S = 1, Y = I 1 0 I 0 1 I 1 159

160 4-to-1 Line Multiplexer 160

161 Quadruple 2-to-1 Line Multiplexer Multiplexer circuits can be combined with common selection inputs to provide multiple-bit selection logic. Compare with Fig4-24. I 0 Y I 1 161

162 Boolean function implementation A more efficient method for implementing a Boolean function of n variables with a multiplexer that has n-1 selection inputs. F(x, y, z) = (1,2,6,7) 162

163 4-input function with a multiplexer F(A, B, C, D) = (1, 3, 4, 11, 12, 13, 14, 15) 163

164 Three-State Gates A multiplexer can be constructed with three-state gates. 164

165 Sequential Circuits A sequential circuit is one whose outputs depend not only on its current inputs, but also on the past sequence of inputs. In other words, sequential circuits must be able to remember (i.e., store) the past history of the inputs in order to produce the present output. The information about the previous inputs history is called the state of the system. A circuit that uses n binary state variables to store its past history can take up to 2 n different states. Since n is always finite, sequential circuits are also called finite state machines (FSM). 165

166 In short, sequential circuits are circuits consisting of ordinary gates and feedback loops X1 X2 Xn switching network Z1 Z2 Zn 166

167 The simplest sequential circuit Two inverters and a feedback loop form a static storage cell The cell will hold value as long as it has power applied bistable cell "1" "0" "stored value" (= state) How to get a new value into the storage cell? selectively break feedback path load new value into cell "remember" D latch 167 "data" "load" "stored value"

168 Latches and Flip-Flops The two most popular varieties of storage cells used to build sequential circuits are: latches and flip-flops. Latch: level sensitive storage element Flip-Flop: edge triggered storage element Common examples of latches: S-R latch, \S-\R latch, D latch (= gated D latch) Common examples of flip-flops: D-FF, D-FF with enable, Scan-FF, JK-FF, T-FF 168

169 S-R (Set-Reset) Latch X Y NOR S-R latch: similar to inverter pair, with capability to force output to 0 (reset=1) or 1 (set=1) R S Q QN 169

170 S-R latch operation S R 0 0 QN =1 Q 0= 0= S R 1 0 QN =0 Q 0= =1 S R S R QN =0 0 0 Q =1 =1 QN =1 0 1 Q =1 =0 170

171 S-R latch operation (cont d) (hold) (reset) (set) (forbidden) Race 171 Both Q and QN are 0 at the same time

172 Improper S-R latch operation QN Theoretically the circuit starts to oscillate Reset Hold Set Reset Set Race 172 R S Q QN

173 R-S latch analysis Break feedback path 173 R S S(t) R(t) Q(t) Q(t+ ) hold reset set X not allowed X Q QN a.k.a. characteristic equation Q(t) S(t) R(t) Q(t) R(t) S(t) X 1 X 1 next state equation: Q(t+ ) = S(t) + R (t) Q(t) Q + = Q * = S + R Q Q(t+ )

174 S-R Latch SN(t) RN(t) Q(t) Q(t+ ) Q(t) hold RN reset SN set X not allowed X X 1 SN(t) 0 0 next state equation: Q(t+ ) = S (t) + R(t) Q(t) Q(t) X Q + = Q * = S + R Q 174 RN(t)

175 D Latch (= Transparent Latch) = 175

176 D-Latch Timing Parameters The D Latch eliminates the S=R=1 problem of the SR latch However, violations of setup and hold time still cause metastability 176

177 Clock signals Clocks are regular periodic signals used to specify state changes 177

178 D Flip-Flop (positive edge Functional Table triggered) Truth Table More compact Truth Table D Q Notice: the little triangle! Next state equation: CLK D Q 178 inputs sampled on rising edge; outputs change after rising edge

179 Setup and hold times for an edge-triggered DFF 179

180 Minimum clock period T? t pinv = 2 ns t pff = 5 ns t suff = 3 ns T = 9 ns T = 15 ns Example with T = 9 ns Example with T = 15 ns 180

181 Minimum clock period T? (cont d) Observation: t hff doesn t affect this calculation t pinv = 2 ns t pff = 5 ns t suff = 3 ns T min = 10 ns 181

182 D Flip-Flop (negative edge triggered) 182 inputs sampled on falling edge; outputs change after falling edge

183 DFF with asynchronous preset and clear 183

184 184 DFF with asynchronous preset and clear (cont d)

185 DFF with enable D EN CLK 0 1 D CK Q Q Reliable alternative 185

186 186 DFF with enable (cont d)

187 JK Flip Flop (rising edge triggered) = Functional Table Truth Table More Compact Truth Table J K Q Q Q Next state equation: 187

188 188 Summary of latches and flip flops

189 Comparison of latches and flipflops D Q QFF CLK positive edge-triggered flip-flop D CLK QFF D Q G CLK Qlatch Qlatch transparent (level-sensitive) latch behavior is the same unless input changes while the clock is high 189

190 Synchronous Sequential Circuit Analysis 190

191 Synchronous Sequential Circuit State Memory A set of n edge-triggered flip-flops that store the current state of the machine All flip-flops are triggered from the same master clock signal All change state together Combinational circuit Next state logic Output logic Mealy and Moore Inputs Combinational circuit Outputs Current State State Memory Next State Clock 191

192 Mealy Model next state = F (current state, inputs) outputs = G (current state, inputs) 192

193 Moore Model next state = F (current state, inputs) outputs = G (current state) 193

194 Analysis - Goals Characterize as Mealy or Moore machine Determine next state equations, i.e., find the function F next state = F (current state, inputs) Determine output equations Meally: outputs = F (current state, inputs), or Moore: outputs = F (current state) Express as machine behavior State table, or State diagram Formulate English description of machine behavior 194

195 An example sequential circuit A sequential circuit with two JK flip-flops State or memory: Q1Q0 One input: X; One output: Z 195

196 State table of example circuit Present State Inputs Next State Outputs Q 1 Q 0 X Q 1 Q 0 Z

197 Output Equations From the diagram, you can see that Z = Q 1 Q 0 X Mealy model circuit!!! Present State Inputs Next State Outputs Q 1 Q 0 X Q 1 Q 0 Z

198 Next State Equations Q(t+1) Find the flip-flop input equations/excitation equations Substitute excitation equations in the flip-flop s characteristic equation J 1 = X Q 0 K 1 = X + Q 0 J 0 = X + Q 1 K 0 = X 198

199 Next State Equations Q(t+1) Excitation equations: J 1 = X Q 0 and K 1 = X + Q 0 J 0 = X + Q 1 and K 0 = X Characteristic equation of the JK flip-flop: Q(t+1) = K Q(t) + JQ (t) Next state equations: Q 1 (t+1) = K 1 Q 1 (t) + J 1 Q 1 (t) = (X + Q 0 (t)) Q 1 (t) + X Q 0 (t) Q 1 (t) = X (Q 0 (t) Q 1 (t) + Q 0 (t) Q 1 (t) ) = X (Q 0 (t) Q 1 (t)) Q 0 (t+1) = K 0 Q 0 (t) + J 0 Q 0 (t) = X Q 0 (t) + (X + Q 1 (t)) Q 0 (t) = X + Q 0 (t) Q 1 (t) 199

200 State Table & Next State Equations Q 1 (t+1) = X (Q 0 (t) Q 1 (t)) Q 1 =0, Q 0 =0, X= 0 => Q 1 (t+1)= 0 Q 0 (t+1) = X + Q 0 (t) Q 1 (t) Q 1 =0, Q 0 =0, X= 0 => Q 0 (t+1)= 0 Present State Inputs Next State Outputs Q 1 Q 0 X Q 1 Q 0 Z

201 State Table & Next State Equations Q 1 (t+1) = X (Q 0 (t) Q 1 (t)) Q 1 =0, Q 0 =1, X= 1 => Q 1 (t+1)= 0 Q 0 (t+1) = X + Q 0 (t) Q 1 (t) Q 1 =0, Q 0 =1, X= 1 => Q 0 (t+1)= 1 Present State Inputs Next State Outputs Q 1 Q 0 X Q 1 Q 0 Z

202 State Table & Next State Equations Q 1 (t+1) = X (Q 0 (t) Q 1 (t)) Q 0 (t+1) = X + Q 0 (t) Q 1 (t) Present State Inputs Next State Outputs Q 1 Q 0 X Q 1 Q 0 Z

203 State Table & Characteristic Table The general JK flip-flop characteristic equation is: Q(t+1) = K Q(t) + JQ (t) We can also determine the next state for each input/current state combination directly from the characteristic table J K Q(t+1) Operation 0 0 Q(t) No change Reset Set 1 1 Q (t) Complement 203

204 State Table & Characteristic Table With these equations, we can make a table showing J 1, K 1, J 0 and K 0 for the different combinations of present state Q 1 Q 0 and input X J 1 = X Q 0 J 0 = X + Q 1 K 1 = X + Q 0 K 0 = X Present State Inputs Flip-flop Inputs Q 1 Q 0 X J 1 K 1 J 0 K

205 State Table & Characteristic Table J K Q(t+1) 0 0 Q(t) Q (t) Present State Inputs FF Inputs Next State Q 1 Q 0 X J 1 K 1 J 0 K 0 Q 1 Q

206 State Table & Characteristic Table J K Q(t+1) 0 0 Q(t) Q (t) Present State Inputs FF Inputs Next State Q 1 Q 0 X J 1 K 1 J 0 K 0 Q 1 Q

207 A different look Present State Inputs Next State Outputs Q 1 Q 0 X Q 1 Q 0 Z Present State Q1 Q0 Next State Input Input X= 0 X= 1 Output Z X= 0 X=

208 State diagrams (Mealy model) We can also represent the state table graphically with a state diagram A diagram corresponding to our example state table is shown below Present State Inputs Next State Outputs Q 1 Q 0 X Q 1 Q 0 Z input output 0/0 1/0 00 1/0 01 0/0 1/1 1/0 0/0 11 0/0 10 state 208

209 Sizes of state diagrams Always check the size of your state diagrams If there are n flip-flops, there should be 2 n nodes in the diagram If there are m inputs, then each node will have 2 m outgoing arrows In our example, We have two flip-flops, and thus four states or nodes. There is one input, so each node has two outgoing arrows. 0/0 1/0 1/ /0 1/1 1/0 0/0 11 0/

210 Another Mealy Circuit 210

211 Excitation Equations D 0 = EN Q 0 + EN Q 0 D 1 = EN Q 1 + EN Q 1 Q 0 + EN Q 1 Q 0 211

212 Next State/Output Equations Q 0 (t+1) = D 0 = EN Q 0 + EN Q 0 Q 1 (t+1) = D 1 = EN Q 1 + EN Q 1 Q 0 + EN Q 1 Q 0 MAX= EN Q 1 Q 0 212

213 Mealy State Table Q 0 (t+1) = D 0 = EN Q 0 + EN Q 0 Q 1 (t+1) = D 1 = EN Q 1 + EN Q 1 Q 0 + EN Q 1 Q 0 MAX= EN Q 1 Q 0 Present State Q1 Q0 Next State Input Input EN= 0 EN= 1 Output MAX X= 0 X=

214 Mealy State Diagram Present State Q1 Q0 Next State Input Input EN= 0 EN= 1 Output MAX X= 0 X=

215 Moore Circuit X Remove input connection to output logic => Moore machine 215

216 Next State/Output Equations X Q 0 (t+1) = D 0 = EN Q 0 + EN Q 0 Q 1 (t+1) = D 1 = EN Q 1 + EN Q 1 Q 0 + EN Q 1 Q 0 MAX= Q 1 Q 0 216

217 Moore State Table Q 0 (t+1) = D 0 = EN Q 0 + EN Q 0 Q 1 (t+1) = D 1 = EN Q 1 + EN Q 1 Q 0 + EN Q 1 Q 0 MAX= Q 1 Q 0 Present State Q1 Q0 Next State Input Input EN= 0 EN= 1 Output MAX

218 Moore State Diagram Present State Q1 Q0 Next State Input Input EN= 0 EN= 1 Output MAX X= 0 X=

219 State Transitions MAX : Output of the Mealy circuit MAXS : Output of the Moore circuit 219

220 Shift register Circuit for simple shift register Basic applications Ring counters Johnson counters Pseudo-random binary sequences and encryption Ready-made shift registers are available as integrated circuits, such as the 165 Conversion of data from serial to parallel and vice versa Large-scale devices such as universal asynchronous receiver transmitters (UARTs) are based on shift registers Same functions available in microcontrollers ( shift and rotate instructions)

221 Basic shift register A basic shift register is simply a chain of D flip-flops with a common clock. serial input D Q D Q D Q D Q serial output clock A B C D Each flip-flop transfers its D input to its Q output at a clock transition. The effect is to transfer data along the register, one flip-flop per clock cycle. This type of register is called a serial input-serial output (SISO).

222 Basic shift register A basic shift register is simply a chain of D flip-flops with a common clock. serial input D Q D Q D Q D Q serial output clock A B C D The table shows the contents of the register after successive clock transitions. The assumption is that the register is initially clear. The number of clock pulses needed to fill the register is equal to the number of flip-flops used to make the register. This is a 4 bit register. clock pulses input Q A Q B Q C Q D

223 Timing for a shift register clock input Q A Q B Q C Q D t pd The pattern in successive flip-flops moves to the right with each clock cycle to shift the pattern into and out of the register.

224 Timing for a shift register clock input Q A Q B Q C input Q A Q B Q C Q D Q D t pd

225 Applications of a basic shift register 1. Delay line N stages delay the signal by N clock cycles 2. Multiplication and division by powers of 2, because this just requires a shift of the binary number (like multiplication or division by 10 in decimal) Example: decimal 3 x 4 = 12 becomes 11 x 100 = 1100 in binary The arithmetic logic unit (ALU) of a computer processor uses a shift register for this purpose. Warning: the sense of a shift left or right is usually based on its effect on binary numbers written in the usual way. For example, is called a left shift. This is clearer if both numbers are written with 8-bits as Similarly, dividing by 2 such as is a right shift. This is the opposite of what we usually draw in a counter circuit, with the least significant bit (LSB) on the left. Take care! There is a rotate operation where the output from the shift register is fed back to the beginning, usually through the carry bit.

226 Ring counter A shift register with its output fed back to its input forms a ring counter. D Q D Q D Q D Q output A B C D clock This can be used to generate an arbitrary binary pattern of length N, where N is the number of stages in the ring counter. It must be preloaded with the sequence desired, which then rotates around the counter indefinitely. One application is to divide down the clock frequency for a slower part of a digital system, while keeping everything synchronous. Modern computers have several buses running at different speeds, where a ring counter is used to create the clocks for the various buses. It is much harder to multiply a given frequency to obtain a higher frequency signal. A phase locked loop (PLL) is often used.

227 Johnson counter A ring counter with the complement of its output fed back is a Johnson counter. D Q D Q D Q D Q output clock A B C D This generates longer sequences than a simple ring counter. For example, a ring counter with 3 stages produces a cycle of 3 states a waste as there are 23 = 8 states in all. A Johnson counter with 3 stages has a cycle of 6 and a separate cycle of 2. It is important to ensure that it follows the correct one!

228 Johnson counter A ring counter with the complement of its output fed back is a Johnson counter. D Q D Q D Q D Q output clock A B C D Q A Q B Q C

229 Pseudo-random number generator A ring counter with feedback through an exclusive-or gate makes a simple pseudo-random number generator. D Q D Q D Q D Q output Pseudo-random sequences of 1s and 0s have many applications, notably in encryption. They appear to be random over short times but the sequence eventually repeats, hence the more accurate term pseudo-random. Also, they can be reproduced perfectly if you know both: the method used to generate the sequence the state in the sequence at which to start This is an important feature! see next sheet. The circuit above has a period of 24 1 = 15 (the missing state is 0000 why?).

230 Pseudo-random binary sequences and encryption your data (plain text) pseudo-random binary sequence sender exclusive or transmit data over insecure link looks like binary noise apparently random receiver?

231 Pseudo-random binary sequences and encryption your data (plain text) pseudo-random binary sequence sender exclusive or transmit data over insecure link looks like binary noise apparently random same pseudo-random binary sequence receiver? exclusive or your data in plain text again if you exclusive-or a bit with the same value (0 or 1) twice, you get the initial value back again.

232 Pseudo-random binary sequences and encryption your data (plain text) pseudo-random binary sequence sender transmit data over insecure link exclusive or looks like binary noise apparently random How do we ensure that both sender and receiver use the same pseudorandom binary sequence? receiver? exclusive or your data in plain text again same pseudo-random binary sequence if you exclusive-or a bit with the same value (0 or 1) twice, you get the initial value back again. This is the basis of the method used to encrypt data sent over the internet (https) or with a digital mobile phone.

233 Transmission of data serial format Data often has to be transmitted from one computer to another, or from a computer to peripheral equipment (printer, modem, ). This can be done in: serial format, one bit at a time parallel format, several bits at a time (e.g. byte at a time, 8 bits) Serial format is most commonly used because it is simpler. Only a few wires are needed: traditional serial COM ports (RS-232) need only 3 wires (transmitted data, received data and ground but more may be used for control) universal serial bus (USB, common on modern computers) uses 4 wires (two for differential data plus power and ground) Traditional serial transmission was slow but modern systems use much faster rates (USB version 1 up to 12 Mbits per second, FireWire 1 up to 400 Mbits per second), version 2 of both even faster. simple serial bit stream

234 Parallel data Where higher speed is required, several bits (usually a small number of bytes, each of 8 bits) may be moved at once. More complicated connections are needed more wires. Common applications include: inside the processor itself, e.g. our microcontroller handles bytes inside a computer system on the bus (e.g. PCI) and interfaces to disk drives (e.g. e.g. SCSI or IDE) but these are now mainly serial Interfaces have changed to serial because it is hard to ensure that all bits on a parallel bus arrive at the same time at the high speed of modern systems.

235 Parallel data Where higher speed is required, several bits (usually a small number of bytes, each of 8 bits) may be moved at once. More complicated connections are needed more wires. Common applications include: inside the processor itself, e.g. our microcontroller handles bytes inside a computer system on the bus (e.g. PCI) and interfaces to disk drives (e.g. e.g. SCSI or IDE) but these are now mainly serial Interfaces have changed to serial because it is hard to ensure that all bits on a parallel bus arrive at the same time at the high speed of modern systems. How do you interface a serial device to a computer? How do we interface an external device that transmits serially with the bus of a computer that transfers one byte (8 bits) at a time? Use a shift register. In practice this would almost certainly be buried inside a larger circuit called a UART (universal asynchronous receiver transmitter) or something similar.

236 Use of shift register to serialize data parallel data in parallel load D Q D Q D Q D Q serial output A B C D Extra logic is added to the basic shift register so that all the flip-flops can be loaded in parallel (simultaneously), controlled by a shift/load input. Once the data have been loaded, the clock is enabled and the values are shifted once per clock cycle. This causes the input data to be transferred to the output, one bit at a time serial output (PISO). The opposite process is used to read in serial data, fill up the shift register, and transfer it in parallel to a bus when the register is full (SIPO). The register can also be parallel input parallel output (PIPO). Shift or rotate instructions can be used for the same process inside a microcontroller (if it doesn t have a UART built in, which many do).

237 ROM The data stored in ROM are always there, whether the power is on or not. A ROM can be removed from the PC, and then replaced, and the data it contains will still be there. Data stored in these chips is unchangeable, provides a measure of security against accidental or malicious changes to its contents. Unlike RAM, which can be changed as easily as it is read We will look at five of them to see how they differ in the way they are programmed, erased, and reprogrammed 237

238 Mask ROM The mask ROM is usually referred to simply as a ROM. A regular ROM is constructed from hard-wired logic, encoded in the silicon itself to perform a specific function that cannot be changed. They consume very little power and reliable but cannot reprogram or rewrite. Several types of user programmable ROMs have been developed to overcome this disadvantage. 238

239 Programmable ROM (PROM) A mask ROM chip is very expensive and time-consuming to create in small quantities from scratch. Mainly, developers created a type of ROM known as programmable read-only memory (PROM). This is basically a blank ROM chip that can be written only once using special equipment called a PROM programmer. PROM chips have a grid of columns and rows just as ordinary ROMs do. 239

240 Programmable ROM (PROM) The difference is that every intersection of a column and row in a PROM chip has a fuse connecting them. Since all the cells have a fuse, the initial (blank) state of a PROM chip is all 1s. The user cans selectively burn/blow any of these fuse links to produce the desired stored memory data. A charge sent through a column will pass through the fuse in a cell to a grounded row indicating a value of

241 Programmable ROM (PROM) To change the value of a cell to 0, you use a PROM programmer to send a specific amount of current to the cell to break the connection between the column and row by burning out the fuse. This process is known as burning the PROM. Very few bipolar PROMs are still available today. TMS27PC256 is a very popular CMOS PROM with a capacity of 32K

242 Erasable Programmable ROM (EPROM) An EPROM is a ROM that can be erased and reprogrammed as often as desired. Once programmed. The EPROM is a non-volatile memory that will hold its stored data indefinitely. A little glass window is provided in the top of the ROM package. Ultraviolet light of a specific frequency can be shined through this window for a specified period of time, which will erase all cells at the same time so that an erased EPROM stores all 1s and allow it to be reprogrammed again. 242

243 Erasable Programmable ROM (EPROM) EPROMs are configured using an EPROM programmer that provides voltage at specified levels depending on the type of EPROM used. Obviously this is much more useful than a regular PROM, but it does require the erasing light. EPROMs are available in a wide range of capacities and access times. The 27C64 is an example of 8K x 8 CMOS EPROM 243

244 Electrically Erasable Programmable ROM (EEPROM) They require dedicated equipment and a laborintensive process to remove and reinstall them each time a change is necessary. The next type of ROM is the EEPROM, which can be erased under software control. This is the most flexible type of ROM, and is now commonly used for holding BIOS programs 244

245 Electrically Erasable Programmable ROM (EEPROM) In EEPROMs the chip does not have to be removed to be rewritten, the entire chip need not be fully erased to change a specific portion of it, and changing the contents does not require additional dedicated equipment. Instead of using UV light, you can return the electrons in the cells of an EEPROM to normal with the localized application of an electric field to each cell. 245

246 Electrically Erasable Programmable ROM (EEPROM) This erases the targeted cells of the EEPROM, which can then be rewritten. EEPROMs are changed 1 byte at a time, which makes them versatile but slow. The Intel 2864 is an example of EEPROM with 8K 8 array with 13 address inputs and eight data I/O pins 246

247 Flash Memory Flash memories are so called because of their rapid erase and write times. EEPROM chips speed is too slow to use in many products that required quick changes to the data stored on the chip. So a new type of EEPROM called Flash memory that uses in-circuit wiring to erase by applying an electrical field to the entire chip or to predetermined sections of the chip called blocks. 247

248 Flash Memory Flash memory works much faster than traditional EEPROMs because it writes data in chunks, usually 512 bytes in size, instead of 1 byte at a time. The 28F256A CMOS IC is an example of flash memory chip, which has a capacity of 32K

249 The SRAM Memory Cell B0 T3 T5 X0 T1 Vdd T6 X1 T2 T4 B1 WL Circuit Schematic: 4 NFETs and 2 PFETs: T1 & T2 called active devices; T3 & T4 called the I/O devices; T5 & T6 sometimes called loads. The cell is comprised of two cross-coupled inverters (positive feedback). 2 vertical lines (bit lines B0 & B1) are used for sensing state of cell and writing data in the cell 1 horizontal line (word line WL) is used to select a row of cells for writing or reading and to prevent the unselected rows of cells from being disturbed. Circuit Operation: The cell has two stable states: 0 and 1 0 State = Node X0 high and Node X1 low; T2 & T5 are ON, T1 & T6 are OFF. 1 State = Node X1 high and Node X0 low; T1 & T6 are ON; T2 & T5 are OFF. No dc current flows in either state. Write: raise WL to Vdd; pull one bit line high & pull the other bit line low Read: raise WL to Vdd; precharge bit lines to ½ Vdd

250 SRAM Memory Array Organization Bit Addr Word Addr Word Decode (Row Decode) Bit Decode (Column Decode) and Write Drivers SRAM Cell 11 SRAM Cell 21 SRAM Cell 31 SRAM Cell 12 SRAM Cell 22 SRAM Cell 32 Sense Amplifiers and Off-Chip Drivers/Buffers SRAM Cell 13 SRAM Cell 23 SRAM Cell 33 Data In READ Operation: Word Decode circuitry selects one of n word lines and drives high to Vdd (say WL2); other word lines held at gnd. Bit Lines all precharged to half Vdd Selected cell s I/O devices turned ON and apply a V to bit line pair Sense amp triggers on bit line V and stores read data 0 or 1 WRITE Operation: Selected WL is driven high to Vdd by word decode circuitry turning ON I/O devices in selected cells Selected bit column has one BL pulled high to Vdd and the other pulled low to gnd, thus writing the selected cell. Unselected bit columns merely perform a READ operation. Data Out

251 Combinational PLDs A combinational PLD is an integrated circuit with programmable gates divided into an AND array and an OR array to provide an AND-OR sum of product implementation. PROM: fixed AND array constructed as a decoder and programmable OR array. PAL: programmable AND array and fixed OR array. PLA: both the AND and OR arrays can be programmed. 251

252 Combinational PLDs 252

253 Programmable Logic Array Fig.7-14, the decoder in PROM is replaced by an array of AND gates that can be programmed to generate any product term of the input variables. The product terms are then connected to OR gates to provide the sum of products for the required Boolean functions. The output is inverted when the XOR input is connected to 1 (since x 1 = x ). The output doesn t change and connect to 0 (since x 0 = x). 253

254 PLA F1 = AB +AC+A BC F2 = (AC+BC) 254

255 Programming Table 1. First: lists the product terms numerically 2. Second: specifies the required paths between inputs and AND gates 3. Third: specifies the paths between the AND and OR gates 4. For each output variable, we may have a T(ture) or C(complement) for programming the XOR gate 255

256 Simplification of PLA Careful investigation must be undertaken in order to reduce the number of distinct product terms, PLA has a finite number of AND gates. Both the true and complement of each function should be simplified to see which one can be expressed with fewer product terms and which one provides product terms that are common to other functions. 256

257 Example Implement the following two Boolean functions with a PLA: F 1 (A, B, C) = (0, 1, 2, 4) F 2 (A, B, C) = (0, 5, 6, 7) The two functions are simplified in the maps of Fig elements 0 elements 257

258 PLA table by simplifying the function Both the true and complement of the functions are simplified in sum of products. We can find the same terms from the group terms of the functions of F 1, F 1,F 2 and F 2 which will make the minimum terms. F1 = (AB + AC + BC) F2 = AB + AC + A B C 258

259 PLA implementation AB AC BC A B C 259

260 Programmable Array Logic The PAL is a programmable logic device with a fixed OR array and a programmable AND array. 260

261 PAL When designing with a PAL, the Boolean functions must be simplified to fit into each section. Unlike the PLA, a product term cannot be shared among two or more OR gates. Therefore, each function can be simplified by itself without regard to common product terms. The output terminals are sometimes driven by threestate buffers or inverters. 261

262 Example w(a, B, C, D) = (2, 12, 13) x(a, B, C, D) = (7, 8, 9, 10, 11, 12, 13, 14, 15) y(a, B, C, D) = (0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15) z(a, B, C, D) = (1, 2, 8, 12, 13) Simplifying the four functions as following Boolean functions: w = ABC + A B CD x = A + BCD w = A B + CD + B D w = ABC + A B CD + AC D + A B C D = w + AC D + A B C D 262

263 PAL Table z has four product terms, and we can replace by w with two product terms, this will reduce the number of terms for z from four to three. 263