FSA2567 Low-Power, Dual SIM Card Analog Switch

Transcription

1 FSA2567 Low-Power, Dual SIM Card Analog Switch Features Low On Capacitance for Data Path: 10 pf Typical Low On Resistance for Data Path: 6 Ω Typical Low On Resistance for Supply Path: 0.4 Ω Typical Wide V CC Operating Range: 1.65 V to 4.3 V Low Pow er Consumption: 1 μa Maximum - 15 μa Maximum I CCT Over Expanded Voltage Range (V IN =1.8 V, V CC =4.3 V) Wide -3 db Bandw idth: > 160 MHz Packaged in: - Pb-free 16-Lead MLP & 16-Lead UMLP 3 kv ESD Rating, >12 kv Pow er/ ESD Rating Applications Cell phone, PDA, Digital Camera, and Notebook LCD Monitor, TV, and Set-Top Box Description The FSA2567 is a bi-directional, low -pow er, dual doublepole, double-throw (4PDT) analog sw itch targeted at dual SIM card multiplexing. It is optimized for sw itching the WLAN-SIM data and control signals and dedicates one channel as a supply-source sw itch. The FSA2567 is compatible w ith the requirements of SIM cards and features a low on capacitance (C ON ) of 10 pf to ensure high-speed data transfer. The V SIM sw itch path has a low R ON characteristic to ensure minimal voltage drop in the dual SIM card supply paths. The FSA2567 contains special circuitry that minimizes current consumption w hen the control voltage applied to the SEL pin is low er than the supply voltage (V CC ). This feature is especially valuable in ultra-portable applications, such as cell phones; allow ing direct interface w ith the general-purpose I/Os of the baseband processor. Other applications include sw itching and connector sharing in portable cell phones, PDAs, digital cameras, printers, and notebook computers. Ordering Information Part Number Top Mark Operating Temperature Range Package FSA2567MPX FSA to +85 C FSA2567UMX GX 16-Lead, Molded Leadless Package (MLP) Quad, JEDEC MO- 220, 3 mm Square 16-Lead, Quad, Ultrathin Molded Leadless Package (UMLP), 1.8 x 2.6 mm 2008 Semiconductor Components Industries, LLC. Publication Order Number: Nov ember-2017, Rev. 2 FSA2567/D

2 Pin Assignments 1V SIM 2RST RST 1 2 V SIM 1RST 2V SIM V CC 2CLK 1DAT CLK (Not connected to ) V SIM V 2V SIM SIM 1RST RST 2RST 1CLK CLK 2CLK 1DAT DAT 2DAT Figure 1. Analog Symbol 1V SIM DAT 2DAT No Connect 2RST 1CLK RST 3 4 V SIM RST 2V SIM V CC 2CLK 1DAT CLK 10 9 DAT 2DAT No Connect 1CLK Figure 2. Pad Assignment MLP16 (Top Through View) Figure 3. Pad Assignment UMLP16 (Top Through View) Pin Definitions Pin ndat, nrst, nclk nv SIM V SIM, DAT, RST, CLK Multiplexed Data Source Inputs Multiplexed SIM Supply Inputs Common SIM Ports Sw itch ect Description Truth Table Function Logic LOW Logic HIGH 1DAT = DAT, 1RST = RST, 1CLK = CLK, 1V SIM = V SIM 2DAT = DAT, 2RST = RST, 2CLK = CLK, 2V SIM = V SIM 2

3 Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit V CC Supply Voltage V V CNTRL DC Input Voltage () (1) -0.5 V CC V V SW DC Sw itch I/O Voltage (1) -0.5 V CC V I IK DC Input Diode Current -50 ma I SIM DC Output Current - V SIM 350 ma I OUT DC Output Current DAT, CLK, RST 35 ma T STG Storage Temperature C ESD Human Body Model, JEDEC: JESD22-A114 All Pins 3 I/O to 12 Charged Device Model, JEDEC: JESD22-C101 2 Note: 1. The input and output negative ratings may be exceeded if the input and output diode current ratings are observed. kv Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit V CC Supply Voltage V V CNTRL Control Input Voltage () (2) 0 V CC V V SW Sw itch I/O Voltage -0.5 V CC V I SIM DC Output Current - V SIM 150 ma I OUT DC Output Current DAT, CLK, RST 25 ma T A Operating Temperature C Note: 2. The control input must be held HIGH or LOW; it must not float. 3

4 DC Electrical Characteristics All typical values are at 25 C, 3.3 V V CC unless otherw ise specified. Symbol Parameter Conditions V CC (V) T A =- 40ºC to +85ºC Min. Typ. Max. V IK Clamp Diode Voltage I IN = -18 ma V V IH V IL Input Voltage High Input Voltage Low 1.65 to to to to I IN Control Input Leakage V SW = 0 to V CC µa I nc(off), I no(off), Off State Leakage R OND R ONV R OND I CC I CCT Data Path Sw itch On Resistance (3) V SIM Sw itch On Resistance (3) nrst, ndat, nclk, nv SIM = 0.3 V or 3.6 V Figure 10 V SW = 0, 1.8 V, I ON = -20 ma Figure 9 V SW = 0, 2.3 V, I ON = -20 ma Figure 9 V SW = 0, 1.8V, I ON = -100mA Figure 9 V SW = 0, 2.3 V, I ON = -100 ma Figure 9 Units na Data Path Delta On Resistance (4) V SW = 0 V, I ON = -20 ma Ω Quiescent Supply Current Increase in I CC Current Per Control Voltage and V CC V CNTRL = 0 or V CC, I OUT = µa V CNTRL = 2.6 V, V CC = 4.3 V µa V CNTRL = 1.8 V, V CC = 4.3 V µa Notes: 3. Measured by the voltage drop betw een ndat, nrst, nclk and relative common port pins at the indicated current through the sw itch. On resistance is determined by the low er of the voltage on the relative ports. 4. Guaranteed by characterization. V V Ω Ω 4

5 AC Electrical Characteristics All typical value are for V CC =3.3V at 25 C unless otherw ise specified. Symbol Parameter Conditions V CC (V) t OND t OFFD t ONV t OFFV Turn-On Time to Output Turn-Off Time to Output Turn-On Time to Output (V SIM ) Turn-Off Time to Output (V SIM ) t PD Propagation Delay (5) t BBMD t BBMV Q O IRR Xtalk Break-Before-Make (5) Break-Before-Make (5) (V SIM ) Charge Injection Off Isolation Non-Adjacent Channel Crosstalk R L = 50 Ω, C L = 35 pf V SW = 1.5 V Figure 11, Figure 12 R L = 50 Ω, C L = 35 pf V SW = 1.5 V Figure 11, Figure 12 R L = 50 Ω, C L = 35 pf V SW = 1.5 V Figure 11, Figure 12 R L = 50 Ω, C L = 35 pf V SW = 1.5 V Figure 11, Figure 12 C L = 35 pf, R L = 50 Ω Figure 11, Figure 13 R L = 50 Ω, C L = 35 pf V SW1 = V SW2 = 1.5 V Figure 15 R L = 50 Ω, C L = 35 pf V SW1 = V SW2 = 1.5 V Figure 15 C L = 50 pf, R GEN = 0 Ω, V GEN = 0 V R L = 50 Ω, f = 10 MHz Figure 17 R L = 50 Ω, f = 10 MHz Figure 18 T A =- 40 C to +85 C Min. Typ. Max. Units 1.8 (5) ns 2.7 to ns 1.8 (5) ns 2.7 to ns 1.8 (5) ns 2.7 to ns 1.8 (5) to ns ns 2.7 to ns 2.7 to ns 2.7 to pc 2.7 to db 2.7 to db BW -3 db Bandw idth R L = 50 Ω, C L = 5 pf Figure to MHz Note: 5. Guaranteed by characterization. 5

6 Capacitance Symbol Parameter Conditions T A =- 40 C to +85 C Min. Typ. Max. C IN Control Pin Input Capacitance V CC = 0 V 1.5 C OND RST, CLK, DAT On Capacitance (6) V CC = 3.3 V, f = 1 MHz Figure 20 C ONV V SIM On Capacitance (6) V CC = 3.3 V, f = 1 MHz Figure 20 C OFFD RST, CLK, DAT Off Capacitance V CC = 3.3 V, Figure 19 3 C OFFV V SIM Off Capacitance V CC = 3.3 V, Figure Note: 6. Guaranteed by characterization Units pf 6

7 RON (Ohms) Typical Performance Characteristics C 25 C -40 C V IN, V CC = 2.7V Figure 4. R ON Data Path Off Isolation (db) Crosstalk (db) Gain (db) RON (Ohms) Frequency Response 85 C 25 C -40 C V IN, V CC = 2.7V Figure 5. R ON V SIM Frequency (MHz) V CC = 2.7V Figure 6. Off Isolation Frequency Response Frequency (MHz) V CC = 2.7V Figure 7. Crosstalk Frequency Response Frequency (MHz) C L = 5pF, V CC = 2.7V Figure 8. Bandwidth 7

8 Test Diagrams nv SIM, nrst, nclk, or ndat V SW V SW nv SIM, nrst, nclk,or ndat V ON R ON = V ON / I ON V SIM, RST, CLK, or DAT V = 0 or V CC Figure 9. On Resistance V SIM, RST, CLK,or DAT C L R L I ON R L and C L are functions of the application environment (see tables for specific values). C L includes test fixture and stray capacitance. V CC 90% NC I na(off) A V SW V = 0 or V CC Figure 10. Off Leakage t RISE = 2.5ns t FALL = 2.5ns 90% 90% Input V V CC /2 V CC /2 10% 10% VOH 90% Output - V OL t ON t OFF Figure 11. AC Test Circuit Load Figure 12. Turn-On / Turn-Off Waveforms t RISE = 2.5ns t FALL = 2.5ns V CC 90% 90% Input - V SW 10% V OH V CC /2 V CC /2 10% Output - VOUT 50%50% V OL t plh t phl Figure 13. Propagation Delay nv SIM, nrst, nclk, or ndat V SIM, RST, CLK, or DAT V CC Logic Input Off On Off V SW C L R L 0V Figure 14. Charge Injection Q = C L 8

9 Test Diagrams (Continued) V SEL V SW1 nv SIM, nrst, nclk or ndat V SW2 trise = 2.5ns V V CC SIM,RST, CLK or DAT Input- V 10% 0V C L RL VOUT 0.9 R L and C L are functions of the application environment (see tables for specific values). C L includes test fixture and stray capacitance. Figure 15. R S and R T are functions of the applica tion environment (see tables for specific values). Break-Before-Make Interval Timing Network Analyzer R S V IN R T V S V 90% V CC /2 t BBM R T R S and R T are functions of the application environment (see tables for specific values). 0.9 Network Analyzer R S V IN R T V S Off isolation = 20 Log ( / V IN ) Figure 16. Bandwidth Figure 17. Channel Off Isolation NC Network Analyzer R S V V IN V S R T R T R S and R T are functions of the application environment (see tables for specific values). Crosstalk= 20 Log ( / V IN ) Figure 18. Non-Adjacent Channel-to-Channel Crosstalk Capacitance Meter nv SIM, nrst, nclk, or ndat f = 1MHz nv SIM, nrst, nclk, or ndat V = 0 orv CC Capacitance Meter f = 1MHz V SIM, RST, CLK, or DAT nv SIM, nrst, nclk, or ndat V = 0 or V CC Figure 19. Channel Off Capacitance Figure 20. Channel On Capacitance 9

10 Physical Dimensions 2X PIN#1 IDENT 0.10 C 0.08 C 0.05 C 0.025± ±0.05 (15X) DETAIL A PIN#1 IDENT 1.80 TOP VIEW 0.50± X SEATING C PLANE SIDE VIEW 1.80± A B C 0.15± ± (16X) RECOMMENDED LAND PATTERN 0.50± ± DETAIL A SCALE : 2X (15X) 2.90 NOTES: BOTTOM VIEW ±0.05 (16X) A. PACKAGE DOES NOT FULLY CONFORM TO JEDEC STANDARD. B. DIMENSIONS ARE IN MILLIMETERS C A B 0.05 C C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, D. LAND PATTERN RECOMMENDATION IS EXISTING INDUSTRY LAND PATTERN. E. DRAWING FILENAME: MKT-UMLP16Arev5. F. TERMINAL SHAPE MAY VARY ACCORDING TO PACKAGE SUPPLIER, SEE TERMINAL SHAPE VARIANTS. LEAD SHAPE AT PACKAGE EDGE R0.20 PACKAGE EDGE LEAD OPTION 1 SCALE : 2X LEAD OPTION 2 SCALE : 2X Figure Lead Ultrathin Molded Leadless Package (UMLP) 10

11 Physical Dimensions Figure Terminal Molded Leadless Package (MLP) 11

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