FSA1208 Low-Power, Eight-Port, High-Speed Isolation Switch

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1 1A 2A 3A 4A 5A 6A 7A 8A FSA1208 1B 2B 3B 4B 5B 6B 7B 8B FSA1208 Low-Power, Eight-Port, High-Speed Isolation Switch Features Low On Capacitance: 6 pf Typical Low On Resistance: 15 Ω Typical Low Pow er Consumption: 1 A Maximum 10 μa Maximum ICCT over an Expanded Voltage Range (VIN=2.3 V, VCC=4.3 V) Wide -3 db Bandw idth: > 400 MHz Packaged in Space-Saving 20-Lead MLP (2.5 x 4.5 mm) 7.5 kv ESD Rating; >16 kv Pow er/ ESD Rating Low C OFF Capacitance: 2.5 pf Typical Applications Description The FSA1208 is a low -pow er, eight-port, high-speed sw itch. This part is configured as a single-pole, singlethrow sw itch and is optimized for isolating a highspeed source, such as a DDR memory bus. The FSA1208 features an extremely low on capacitance (C ON) of 6 pf Superior channel-to-channel crosstalk minimizes interference. The FSA1208 contains special circuitry on the A & B pins that allow s the device to w ithstand an over-voltage condition. This device is also designed to minimize current consumption even w hen the control voltage applied to the /OE pin is low er than the supply voltage (V CC). Applications include port isolation and sw itching in DDR memory modules, portable cell phones, PDAs, digital cameras, printers, and notebook computers. DIMM DDR Memory Ordering Information Part Number Top Mark Operating Temperature Range FSA1208BQX F to +85 C Package 20-Lead, Quad, Molded Leadless Package (MLP), 2.5 x 4.5 mm DIMM OE V CC DIMM DIMM Slot Figure 1. Analog Symbol 2008 Semiconductor Components Industries, LLC Publication Order Number: October-2017, Rev. 2 FSA1208/D

2 Pin Configurations B1 B2 B3 B4 B5 B6 B7 B /OE NC 1 10 VCC A1 A2 A3 A4 A5 A6 A7 A8 Figure 2. Pin Assignments for MLP (Top Through View ) Pin Definitions Pin # Name Description 20 /OE Sw itch Enable 2-9 A1-A8 A Side of Bus B8-B1 B Side of Bus 11 NC No Connection 1 VCC Pow er 10 Ground Truth Table /OE HIGH LOW Function Disconnect A1-A8=B1-B8 2

3 Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VCC Supply Voltage V V CNTRL DC Input Voltage (/OE) (1) V CC V VSW DC Sw itch I/O Voltage (1) V I IK DC Input Diode Current -50 ma IOUT DC Output Current 50 ma TSTG Storage Temperature C All Pins 7.5 ESD Human Body Model, JEDEC: JESD22-A114 I/O to 8 Pow er to 16 kv Charged Device Model, JEDEC: JESD22-C The input and output negative ratings may be exceeded if the input and output diode current ratings are observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit VCC Supply Voltage V V CNTRL (2) Control Input Voltage (S, /OE) 0 V CC V V SW Sw itch I/O Voltage -0.5 V CC V TA Operating Temperature C 2. The control input must be held HIGH or LOW; it must not float. 3

4 DC Electrical Characteristics All typical values are at 25 C unless otherw ise specified. Symbol Parameter Conditions V CC (V) T A =- 40ºC to +85ºC Min. Typ. Max. Units V IK Clamp Diode Voltage I IN=-18 ma V VIH V IL Input Voltage High 2.3 to V V Input Voltage Low 2.3 to V V IIN Control Input Leakage VSW=0 to VCC µa IOZ Off State Leakage 0 A, B 3.6 V µa R ON Sw itch On Resistance (3) VSW=0 V, ION=-10 ma Figure 3 VSW=1.8 V, ION=-10 ma Figure I CC Quiescent Supply Current V IN=0 or V CC, I OUT= µa I CCT Increase in ICC Current Per Control Voltage and V CC V IN=1.8 V µa 3. Measured by the voltage drop betw een A and B pins at the indicated current through the sw itch. On resistance is determined by the low er of the voltage on the tw o (A or B ports). AC Electrical Characteristics All typical values are for V CC=2.5 V at 25 C unless otherw ise specified. Symbol Parameter Conditions V CC (V) t on t uff Turn-On Time, /OE to Output Turn-Off Time, /OE to Output R L=50 Ω, C L=5 pf V SW=1.8 V Figure 4, Figure 5 R L=50 Ω, C L=5 pf VSW=1.8 V Figure 4, Figure 5 (4) t ad Propagation Delay RL=50 Ω, CL=5 pf Figure 4, Figure 6 OIRR Xtalk BW Off Isolation Non-Adjacent Channel Crosstalk -3dB Bandw idth 4. Guaranteed by characterization. R L=50 Ω, f=400 MHz Figure 11 R L=50 Ω, f=100 MHz Figure 12 R L=50 Ω, C L=0 pf Figure 10 RL=50 Ω, CL=5 pf Figure 10 T A =- 40ºC to +85ºC Min. Typ. Max. Units 2.3 to ns 2.3 to ns ns 2.3 to db 2.3 to db 2.3 to MHz 750 MHz 4

5 High-Speed-Related AC Electrical Characteristics Symbol Parameter Conditions V CC (V) T A =- 40ºC to +85ºC Min. Typ. Max. Units tsk(o) Channel-to-Channel Skew (5) CL=5 pf ps t SK(P) Skew of Opposite Transitions (5) CL=5 pf ps of the Same Output tsk(pkg) Package-to-Package Skew (5) CL=5 pf ps 5. Guaranteed by characterization. Capacitance Symbol Parameter Conditions T A =- 40ºC to +85ºC Min. Typ. Max. Units CIN Control Pin Input Capacitance VCC=0.2 V, f=1 MHz 2.0 CON D+/D- On Capacitance V CC=2.5 V, /OE=0 V, f=1 MHz Figure pf C OFF D1n, D2n Off Capacitance V CC and /OE=2.5 V, f=1 MHz Figure

6 Test Diagrams V O N V S W A n B n I O N /O E V S e l = 0 r V c c R = O o N Figure V O / I O N N 3. On Resistance V S W V Sel R, R L S, and C L a re fun c tio n s of the a pp l ica ti o n e nvi ro n m ent (see AC tabl es for speci fi c val ues). i ncl udes test fix t ure and stray capa c it a nce. C L R S A n Bn C L R L Figure 4. AC Test Circuit Load V OU T t RISE = 2.5ns t FALL = 2.5ns V CC 90% 90% Input V /OE, V Sel 10% V OH V CC /2 V CC /2 10% 90% 90% Output- V OUT V OL t ON t OFF Figure 5. Turn-On / Turn-Off Waveforms t RISE= 500ps t FALL = 500ps +400mV -400mV 10% 0V 90% 90% 10% Output Figure 6. Propagation Delay (t ry t o 500ps) t PHL t PLH Figure 7. Intra-Pair Skew Test tsk(p) C ap ac i tanc e M eter A n /OE V S el = 0 or V cc C ap ac itance Met er A n /OE V Sel = 0 or V c c B n B n Figure 8. Channel Off Capacitance Figure 9. Channel On Capacitance 6

7 Test Diagrams (Continued) Network Analyzer R S V IN V S V Sel R T V OUT R S and R T are functions of the application environment (see AC Tables for specific values). Figure 10. Bandw idth N e t w o r k A n a l y z r R S e V S e l V I N R V S T V OU T R andr ar S T fun c t i o n s o f the a p p li c a t i o n e n v i r o n m e n e t ( s ee A C t a b l e s f o r s p ec i f i c Va l u e s). R T Off isolation = 20 Log (V OUT / V IN ) Figure 11. Channel Off Isolation N C Networ k Anal y z r R e S V IN V S V Sel G ND G ND R T V OUT R T R and R ar S T functions o f the application envi ronment (s eeac tabl e es for s pec i fi c val ues). Crosstalk = 20Log ( V OUT / V IN ) Figure 12. Non-Adjacent Channel-to-Channel Crosstalk 7

8 Physical Dimensions Figure Lead, Molded Leadless Package (MLP) 8

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