Review Paper: Transparent Amorphous Oxide Semiconductor Thin Film Transistor

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1 Electronic Materials Letters, Vol. 7, No. 1 (2011), pp DOI: /s x Published 27 March, 2011 Review Paper: Transparent Amorphous Oxide Semiconductor Thin Film Transistor Jang-Yeon Kwon, Do-Joong Lee and Ki-Bum Kim* Department of Materials Science and Engineering, Seoul National University, Seoul , Korea Thin film transistors (TFTs) with oxide semiconductors have drawn great attention in the last few years, especially for large area electronic applications, such as high resolution active matrix liquid crystal displays (AMLCDs) and active matrix organic light-emitting diodes (AMOLEDs), because of their high electron mobility and spatial uniform property. This paper reviews and summarizes recent emerging reports that include potential applications, oxide semiconductor materials, and the impact of the fabrication process on electrical performance. We also address the stability behavior of such devices under bias/illumination stress and critical factors related to reliability, such as the gate insulator, the ambient and the device structure. Keywords: Oxide semiconductor, thin film transistor, transparent, reliability 1. INTRODUCTION Active matrix liquid crystal displays (AMLCDs) are nowadays the major device of flat panel display products that are conventionally driven by an amorphous Si (a-si) thin film transistor (TFT). Drastic improvement of the driving technology and the electrical performance of a-si TFTs make it possible not only to switch pixels but to integrate the gate driver. However, the growth of the high-end commercial market with high resolution, such as pixels, a high frame rate (>240 Hz), and sizes larger than 70 inches requires a higher electrical performance than the a-si TFT has achieved. At least 3 cm 2 /Vs of field-effect mobility is required to satisfy such demands, [1] which is not so easy to achieve by modifying the conventional amorphous silicon material. First of all, oxide semiconductor materials are promising alternatives due to a relative high electron mobility (3-50 cm 2 /Vs) [2,3], which is large enough to fabricate a high-speed transistor for driving the AMLCDs mentioned above. In addition, oxide semiconductor materials have an amorphous phase in general, which shows uniform electrical properties even with a large-area substrate and is strongly advantageous for the display applications. [4] The second potential application for oxide semiconductor TFTs is the active matrix organic light-emitting diode (AMOLED). For mobile devices such as cellular phones, navigation, and notebook PCs, low temperature poly Si (LTPS) TFTs currently drive AMOLEDs because it exhibits a more sufficient and stable current supply into the organic *Corresponding author: kibum@snu.ac.kr KIM and Springer light-emitting diode (OLED) than the a-si TFT. However, the LTPS TFT has a problem with the spatial distribution of electrical performances originating from non-uniformity of grain sizes in the poly-si film. Consequently, the LTPS TFT is not suitable for the AMOLED TV. Even for a small size AMOLED (below 5 inches), a compensation circuit for pixels is required in order to obtain uniform image quality for the LTPS TFT. As a backplane for the AMOLED TV, the stability of the oxide semiconductor TFT is superior to that of a-si, and at the same time, the uniformity is much better than the LTPS TFT. These aspects have motivated many demonstrations of AMOLEDs driven by the oxide semiconductor TFT. [1,5-7] Another apparent advantage of the oxide semiconductorbased TFTs over silicon-based TFTs is that most oxide semiconductors are transparent in the visible light region and thereby they can be used to realize transparent electronics, including transparent displays. Such transparent devices can be realized with the combination of a transparent insulator, a transparent conductor, and a transparent semiconductor. Most insulators, such as SiO 2 and SiN x, do not absorb visible light, and transparent conducting oxides (TCOs), such as indium-tin oxide (ITO), Al-doped zinc oxide (AZO), and indium zinc oxide (IZO), are well known and easily fabricated materials with advanced technologies. Above all, the oxide semiconductor could be the last key invisible material. For instance, a transparent display is applicable to automobile displays so that people can get information from the transparent display as well as from a real environment, such as in traffic situations while driving a car. Another promising application may involve a see-through mobile phone that would allow users to access both sides of the panel as inde-

2 2 J.-Y. Kwon et al.: Transparent Amorphous Oxide Semiconductor Thin Film Transistor pendent touch screens and thereby to provide resourceful user interfaces. Oxide semiconductor TFTs fabricated on a flexible polymer substrate have also been reported. [8] Because the deposition of oxide semiconductors does not require a high temperature process, typically via sputtering at room temperature, device performances comparable to a substrate on glass are achievable on a flexible substrate. Beyond the display applications, some researchers are investigating oxide semiconductor devices for functional circuits such as an inverter, [9] an oscillator, [10] a non-volatile memory, [11] and photo-sensors. [12] 2. OXIDE SEMICONDUCTOR MATERIALS 2.1. Binary oxide materials: properties of In 2 O 3, ZnO, and SnO 2 Combining conventional TCOs, including In 2 O 3, ZnO, and SnO 2 In 2 O 3, ZnO, and SnO 2 In 2 O 3, ZnO, and SnO 2 In 2 O 3, ZnO, and SnO 2 In 2 O 3, ZnO, and SnO 2 been introduced. These binary oxides have a wide band gap (>3.0 ev) that allows transmission of the visible rays. [13] In addition, they exhibit much higher electrical conductivity (10-2 Ω -1 cm 1 to 10 3 Ω -1 cm 1 ) than the other insulating ionic compounds. This has been attributed to the existence of native defects, such as oxygen vacancies, cation interstitials, and substitutional/ interstitial hydrogen, that act as shallow donors. [14-16] Because of these donors, the TCOs have a high carrier concentration of cm -3 to cm -3. Furthermore, a more important factor is that these oxides have high electron mobility (~10 cm 2 /Vs or higher) even if they are in the amorphous phase. [2,17,18] Those TCOs commonly consist of heavy post transition metal cations with an electronic configuration of (n-1)d 10 ns 0, where n is the principle quantum number of the cations ( n 5 ). Those vacant s-orbitals are spherical, which indicates they are non-directional, and exhibit a large spatial spread. Therefore, electron conduction can easily occur even in the amorphous oxides via direct overlap of the s-orbitals in the neighboring cations. For these reasons, the In 2 O 3, ZnO, and SnO 2 have been widely considered as base materials for amorphous semiconductors. However, those oxides themselves are polycrystalline and thereby are not appropriate as a channel material of the TFT due to poor uniformity. [2,15,19] Therefore, formation of the amorphous oxides by combining those individual TCOs has been one of the critical issues in ensuring large-area uniformity Multicomponent oxide materials One of the principles of forming amorphous materials is mixing multi-components with different crystal structures. The TCOs discussed above satisfy that criterion. For example, In 2 O 3 and ZnO have bixbyite and wurtzite structures, respectively, and also exhibit different coordination numbers to the oxygen as InO 6 and ZnO 4. [15] These aspects allow In- Zn-oxide (IZO) to have an amorphous phase. Consequently, IZO has become an essential component for both the transparent electrodes for flat-panel displays and the active layer for TFTs. [20-23] By varying the composition and the deposition conditions, IZO has exhibited a wide range of the resistivity, 10-4 cm -3 to 10 8 Ω cm. For instance, IZO films with 10 wt.% ZnO is mostly used in electrode applications, [20,24] while the films with a comparable composition of In/Zn (typically In 60:40 Zn) exhibit semiconducting behavior in the resistivity range of Ω cm. [25] In addition, amorphous IZO has shown extremely high thermal stability even up to 600 C. [26] Due to these advantages, amorphous IZO (a- IZO) has been one of the most extensively investigated TCOs and semiconducting oxides for display applications. Even though a-izo films have exhibited adequate properties as a component of TFTs, such as excellent uniformity and large mobility (>20 cm 2 /Vs), one of the critical issues with this material is the controllability of the carrier concentration. Because IZO typically exhibits a high carrier concentration of >10 17 cm -3, this can lead to large off-current and small on-off ratios. [18,19] Therefore, to reduce the carrier concentration below that, doping has been conducted into the a- IZO. For instance, Nomura et al. inserted Ga into IZO (IGZO is most widely used semiconducting oxide currently). [2] Their approach demonstrated that the carrier concentration of amorphous IGZO can be lowered below <10 17 cm -3 whileits electron mobility (~10 cm 2 /Vs) remains high. The decrease of the carrier concentration has been attributed to the high ionic potential of Ga 3+ ions, which allows them to tightly bind oxygen ions and thereby suppress the formation of oxygen vacancies. [2,18,19,27] Since the demonstration of IGZO, similar approaches have been tried by inserting Hf, Zr, Mg, La, Sc, and Si into a a-izo matrix and tested as the active layer of the TFTs. [28-33] As in the case of the IGZO, those oxides exhibited semiconducting behavior and had amorphous or nanocrystalline-embedded amorphous phases. Besides the IZO-based semiconducting oxides, there is another class which contains SnO 2 in which Sn 4+ is one of the heavy post transition cations that satisfies n 5. [18,27,34] Similar to IZO, ZnO and SnO 2 easily form an amorphous phase due to different crystal structures (ZnO: Wurtzite, SnO 2 : rutile) and the coordination number to the oxygen (ZnO 4 / SnO 6 ). [15] This zinc tin oxide (ZTO) is cheaper than the IZO-based materials by excluding the In, one of the scarce and expensive elements. [34,35] For the same aim as with IGZO, there have been several attempts to dope ZTO with various elements, such as Al and Zr, and the device performance of those oxides have been tested. [36,37] Detailed issues of semiconducting oxides as the active layer of TFTs, in terms of the process and the electrical performances, will be covered in the following sections.

3 J.-Y. Kwon et al.: Transparent Amorphous Oxide Semiconductor Thin Film Transistor 3 3. DEVICE CONFIGURATION There are four major classes of configuration of oxide semiconductor TFTs: (1) back channel etch (BCE) structure, [1] (2) etch stopper (ES) structure, [38] (3) top gate (TG) structure, [39] and (4) double gate (DG) structure [40] (Fig. 1). First, the BCE structure is almost the same as the conventional a-si TFT, so it is easily adapted to process and design current TFT-LCD mass production. However, because an oxide semiconductor layer is exposed to a plasma environment which can be an energy source during the subsequent deposition of the sour/drain electrode and passivation layer, additional charge carriers could be generated, and the threshold voltage moves to the negative direction. [41] In addition, because an oxide semiconductor is easily etched by a weak acid, such as acetic acid (CH 3 COOH), the source/drain electrodes should be etched via dry etch with a reasonable etch selectivity between the semiconductor and electrodes. In spite of these obstacles, the BCE structure is one of the ultimate configurations for cost competitive TFTs. The second class of configuration is the etch stopper structure. By inserting an etch stopper layer between the semiconductor and source/drain electrode, most process obstacles mentioned for BCE can be overcome. The source/drain electrode and passivation layer can be formed without changing the semiconductor properties, and the chip wet-etch process for the source/drain can be carried out based on a high selectivity between the electrodes and the etch stopper layer. In this configuration, the deposition of the etch stopper layer and an additional photo lithography process is inevitably required. The next configuration, the top gate structure, has an advantage in the electrical performance of the devices over the first two kinds of TFTs. For example, there is no overlap between the gate and the source/drain electrode, and consequently, it does not create a signal delay from the parasitic capacitance. For LCD applications, however, because light from the backlight unit reaches the semiconductors without being blocked by the gate electrode, the stability of oxide semiconductor for light illumination should be strengthened. In addition, high power plasma is an additional process obstacle to increasing the insulating ability of a gate insulator deposited on the semiconductor. Finally, the double gate is a good candidate for device structure, if two problems, the complexity of the driving scheme and the low electrical performance of the passivation layer, are resolved, because it demonstrates higher electron mobility and stability than the other three kinds of single gate structures. 4. IMPACT OF A UNIT PROCESS ON ELEC- TRICAL PERFORMANCES OF OXIDE SEMI- CONDUCTOR THIN FILM TRANSISTOR Fig. 1. Device configurations of oxide semiconductor (a) back channel etch (BCE) structure (b) etch stopper (ES) structure (c) top gate (TG) structure (d) double gate (DG) structure. (a), (b) from [38]. (c) from [39]. (d) from [40] Gate insulator material and process Silicon oxide and silicon nitride have been most widely used as gate insulators for oxide semiconductor TFTs and as well as for conventional Si-based transistors. For instance, P. F. Carcia et al. compared silicon oxide and silicon nitride as a gate insulators for oxide TFTs. [42] They prepared several kinds of ZnO films as a semiconductor by varying the oxy-

4 4 J.-Y. Kwon et al.: Transparent Amorphous Oxide Semiconductor Thin Film Transistor gen partial pressure (po 2 ) during the deposition, which means the electrical conductivity of the ZnO films was controlled. Additionally, they fabricated TFTs with silicon oxide and silicon nitride as gate insulators, respectively. The silicon oxidewas thermally grown. They prepared two samples of silicon nitride. One was deposited by conventional plasma enhanced chemical vapor deposition (PECVD), so the silicon nitride contained around 30% hydrogen in the film. The other contained a relatively low hydrogen concentration and was formed by the sputtering method. Figure 2 shows the electron mobility of the TFT as a function of oxygen partial pressure for the mentioned gate insulators. At a low po 2, the mobility converged to around 5 cm 2 /Vs regardless of the gate dielectrics. In contrast, as the po 2 increased, the mobility for thermally grown silicon oxide decreased by several orders of magnitude, whereas the decrease for silicon nitride was much less. In the ZnO film deposited on a silicon nitride, oxygen vacancies were formed, which brought about an increase in both the mobile electron concentration and the electron mobility of the device. However, the ZnO grown on silicon oxide contained accepter defects that resulted in a decrease of the electron concentration by trapping the defects. They concluded that photo luminescent results as a proof for oxygen vacancies and accepter defects. Besides SiO 2 and SiN x, many kinds of high-k dielectric materials, such as AlO x, [43] HfO x, [43,44] TiO x, [45] AlN, [46] BaSr- TiO x, [47] and HflaO x [48], have been used for gate insulators in order to reduce the driving voltage and improve sub-threshold properties. The gate insulator plays an important role in TFTs in terms of not only the initial electrical property of the device but also the stability of the device under bias/illumination stresses, because trapping holes induces an external stress into the gate insulator and thereby degrades the device performances. Therefore, controlling the trap defects in a gate insulator is one of the key technologies necessary for improving the reliability of the devices. This will be discussed further in section Source/drain electrode In order to reduce the RC signal delay, the resistivity of both the gate electrode and the source/drain electrode should be decreased. Low resistivity materials, such as molybdenium, aluminium, and copper, are suitable for the source/ drain electrode. The contact resistance between the semiconductor and the source/drain electrode are other considerable factors for determining a material and a process for electrodes. High contact resistance can induce the current crowding at output characteristics and finally increase the signal delay even though the resistivity of the electrode material is enough low. For example, Y. Shimura et al. measured and compared the contact resistance between IGZO and various metallic electrodes, including Ag, Au, In, Pt, Ti, ITO, and IZO. [49] All the materials except Au and Pt exhibited a linear relation of current-voltage characteristics, while Au and Pt resulted in Schottky contacts. They also reported that a decreasing work function of the electrode material leads to a reduction of the contact resistance and, finally, to high performance of the devices (Fig. 3). Copper, which is a kind of ultimate solution for an electrode, reacts with oxygen in the oxide semiconductor and forms copper oxide which increases the contact resistance. Furthermore, copper could Fig. 2. po2 dependence of saturation mobility for ZnO TFTs on different gate dielectrics grown on Si. Mobility data on 100 nm and 430nm SiNx:H are indicated as u(100) and u(430), respectively, in the figure legend, while data on sputtered SiNx and SiO2 are indicated by u(sin) and u(sio2). Data from [42]. Fig. 3. Specific contact resistance obtained as a function of the work function (φ) of the electrode materials. Ti contacts have a large distribution in ρc ( Ω cm 2 ), probably due to the formation of an oxidized interface layer. The φ values are 4.26 ev for Ag, 5.1 ev for Au, 4.12 ev for In, 5.65 ev for Pt, 4.33 ev for Ti, ev for ITO, and ev for a-izo. The φ values of ITO and a-izo vary in a wide range depending on surface state and bulk carrier density. Data from [49].

5 J.-Y. Kwon et al.: Transparent Amorphous Oxide Semiconductor Thin Film Transistor 5 be also oxidized during the deposition of SiO 2 as a passivation layer which is necessary to improve the stability of device. In spite of these obstacles, W.-S Kim et al. demonstrated good performance of a device with a copper electrode as a clue to low resistance metallization. [50] 5. STABILITY In this section, we discuss the stability of oxide semiconductor TFTs under bias and illumination. There are many parameters for the stability of devices, such as an oxide semiconductor material, the material composition, the device structure, the gate insulator, the environment for stressing, the electrical biasing conditions, and the intensity of the illuminated light. This makes it difficult to compare quantitative responses precisely and to summarize the phenomena of stability succinctly. Based on the common results reported by multiple researchers, we tried to understand the reliability of the devices Bias stressing Positive bias stressing R.B.M. Cross et al. reported the reliability of oxide TFTs under bias stress. [51] They applied a gate bias of up to 30 V and measured the change of the device parameters, such as electron mobility (u), threshold voltage (V th ), and subthreshold swing (S.S.). Interestingly, bias stressing produces a parallel shift of V th to the positive direction and no or little change in u and S.S. values (Fig. 4). Similar results were reported by J.-M Lee et al. [52] (Fig. 5). For the case of stress under gate and drain biases at the same time, Fujii et al. reported an increase of V th shift with an increasing gate bias. [53] However, the shift was not strongly dependent on the drain bias. Similar results were also reported for a thermal SiO 2 gate insulator, [54] PECVD SiO 2, SiNx, [55] and Al 2 O 3. [56] Fig. 4. Threshold voltage shift as a function of time for various positive bias stress voltage. Data from [51]. Fig. 5. Linear transfer IDS-VGS curve of a-igzo TFTs as a function of stress time (tst). The inset shows the bias-stress-induced shift of log_ids-vgs curve. The sweep was done at VDS=0.5 V in both curves. Data from [52]. Positive bias stressing has usually been tested for the AMOLED applications, because the TFT must supply a stable current for the entire operating time of the OLED. In such a case, instability measurement is generally carried out under a V g =V d >0 condition in order to supply a constant current. A similar phenomenon was observed for constant current stress experiments, which means the observation of only a parallel V th shift. [57-61] An instability mechanism of the conventional a-si TFT under bias stress was interpreted by two models. [62,63] One was the defect creation in a channel and the other was trapping in a gate insulator or at the interface between the channel and the insulator. The former resulted in the degradation of mobility and S.S., while the latter showed only a parallel shift of V th. Based on these observations, the instability of oxide TFTs under positive bias stress was also explained based on the charge trapping model, and the time evolution of V th was described by the stretched-exponential equation. [52] Even though most reports showed a positive shift of V th and little change of electron mobility under positive bias stress, A. J. Flewitt et al. reported an increase of mobility by increasing the occupancy of defects near the IZO conduction band. [64] Negative bias stressing In general, oxide semiconductors have n-type characteristics, so applying negative voltage at the gate is required for turning-off the device. In particular, the total duration of the negative gate bias applied on the switching transistor is larger than that of the positive gate bias by more than 500 times in the case of AMLCD products. For an AMOLED, the driving TFT must supply current for emission of light and requires high stability under positive bias stressing as

6 6 J.-Y. Kwon et al.: Transparent Amorphous Oxide Semiconductor Thin Film Transistor mentioned in However, switching the TFT is also required for the AMOLED as is exactly in the same bias situation as that of the AMLCD. Therefore, a high reliability with a negative bias stress is an indispensable requirement for operating an active matrix display. For instance, A. Suresh et al. reported a negligible shift of not only mobility and the S.S. value but also V th under negative bias stress. [65] They observed a shift of over 5 V under a +30V gate bias stress after 500 s. However, there was only aslight change of the transfer curve between before and after the negative gate bias stress (-30V). In another study, J. Y. Kwon et al. observed a negative bias stability for both back channel etch structure devices and etch stopper structure devices under w/ and w/o illumination. [38] For both structures, bias induced a small negative shift (below 1V) at the early stage of the stress and little change for further stressing time. K. H. Lee, [66] H. S. Seo [67] and T.Z. Fung [68] also reported a little degradation of those properties, but it could be recovered with the following annealing process. Similar to the positive shift, the negative shift of V th could be explained by a positive charge trap in the gate dielectrics. However, most oxide semiconductors are n-type and contain little positive charge to trap and to induce V th shift in particular. Meanwhile, in the commercial AMLCD device, TFT experiencing a continuous pulsed gate voltage is also exposed to the light, which is inevitable due to the presence of the back light unit underneath. Thus, the device degradation under a negative bias and illumination stress at the same time (called negative bias illumination temperature stress, NBITS) is a critical issue to be resolved. It will be discussed in next section Bias and illumination stressing Stressing of bias and light at the same time (bias illumination temperature stress, BITS) is a more realistic test scheme for display applications than stressing of only bias (bias temperature stress, BTS). In the case of a conventional a-si TFT, the shift of transfer curve by bias stressing and the increase of off-current by illumination stress could be observed. However, no drastic degradation under simultaneous bias and light stresses was found compared to under individual stress. In contrast for the oxide semiconductor TFTs, the shift of V th was accelerated under BITS. Figure 6 shows the evolution of the transfer curve under BTS and BITS, respectively. [69] For the positive bias stress, there was little difference between under BTS and BITS. However, the transfer curve moved to the negative direction fast under BITS, while no remarkable change was observable under BTS for negative bias stress. This movement of transfer curve became faster when the intensity was increased as shown in Fig. 7. Since n-type oxide semiconductors have negligible holes in the valence band, hole trapping in a gate insulator or at the interface between the semiconductor and the gate dielectric is extremely difficult even under the negative gate Fig. 6. Changes in the ID-VG characteristics of ZnO TFTs (W/L =40 µm/20 µm) under 10 V gate bias stress with (a) Pill of 0 mw/cm 2 and (b) 1.0 mw/cm 2 and under -10 V gate bias stress with (c) Pill of 0 mw/cm 2 and (d) 1.0 mw/cm 2. VD is 15 V during the VG sweep. Data from [69].

7 J.-Y. Kwon et al.: Transparent Amorphous Oxide Semiconductor Thin Film Transistor 7 Fig. 7. Von vs. stress time (a) and unified stress time t(1+ηpill) (b), when the ZnO TFTs (W/L=40 µm/20 µm) are biased in the strong off state (VG_ST=-10 V) during illumination with Pill of 0 to 2.6 mw/cm 2 (Lines are theoretical calculations). Data from [69]. bias. However, abundant holes could be generated by light exposure. Drift of those toward the gate insulator and subsequent trapping by the negative electric field would result in remarkable shift of V th. In that report, this phenomenon was explained by using the modified stretched exponential model Gate insulator In order to improve the BITS characteristics, the effect of device components, such as gate insulator, [44,70,71] environment, [54,66,72,73] passivation layer, [74,75] and device structure [38,76], on the stability has been studied. One of the key parameters among them is the gate insulator because the trapping process of photo-generated holes is strongly related to the material and properties of the gate insulator. For example, J.-Y. Kwon et al. compared several materials as a gate insulator under BITS (Fig. 8). [44] The device with SiO 2 and AlO x showed quite stable performances, which is well reconciled with their wide band gap (over 8e V) prohibiting trap of holes into the gate insulators. In contrast, the inferior stability of the device with a SiN x gate dielectric can be attributed to the enhanced hole injection or trapping due to the smaller valence offset (~0.15V). The higher trap density of SiN x compared to SiO 2 was also supported by the fact that SiN x film is often used as the charge trap layer in flash memory devices. The worst reliability of HfO x, even though it has larger valence offset than SiNx, is probably caused by a high leakage conduction via Poole-Frenkel trapping centers which are easily observed in high-k dielectric materials. K. H. Ji et al. also announced the superior reliability of a SiO 2 gate insulator to a SiN x. [70] As another method, the BITS property could be also improved by controlling the mechanical stress of the SiN x film Ambient interaction and passivation layer It is well known that metal oxides are surface sensitive to molecules in an ambient atmosphere. [77-79] The adsorption of oxygen onto the surface of the metal oxides introduces an accepter-like surface state. When oxygen chemisorbs on the surface, it is negatively charged by capturing an electron from the conduction band, and consequently, surface of oxide semiconductor is depleted. On the other hand, H 2 O acts as a donor-like surface state based on a similar explanation. For instance, Jeong et al. discussed how bias stressing is able to lead to field induced adsorption and desorption of O 2 or H 2 O and how it affects device instability by varying the carrier concentration of the oxide semiconductors (Fig. 9). [72] Other experimental results for the effects of ambience was reported by Lee et al. [66] They carried out a BITS test in a humid environment. As the humidity of environment increased, V th moved to the negative direction faster (Fig. 10). In that report, it was suggested that water molecules supplied by the ambient condition generated metastable gap states which brought about a large number of trapped electrons and eventually an increase of hole carriers in the oxide semiconductors, and finally the devices exhibited a negative shift of the threshold voltage. To improve stability by protecting the device from the environment, a passivation layer becomes one of the key parameters. SiO 2 film was suggested as a superior passivation layer for SiN x film. [74] However, not only stability of the device but of the interconnection should be considered in selecting the passivation layer. Especially for a copper electrode as a source/drain, which is indispensible for reducing signal delay time, SiN x film is more stable than SiO 2 film in general Device configuration Device configuration could be another considerable factor

8 8 J.-Y. Kwon et al.: Transparent Amorphous Oxide Semiconductor Thin Film Transistor Fig. 8. Evolution of the transfer characteristics for the (a) SiNx/HfOx/HIZO, (b) SiNx/HIZO, and (c) SiNx/SiOx/HIZO devices as a function of the NBTIS time. (d) Vth shift as a function of the applied NBITS time for the HIZO TFT with various gate dielectric materials and structures. Data from [44]. Fig. 9. (a) Schematic showing the electric-field-induced adsorption of oxygen molecules from the ambient atmosphere under the application of PGVS. (b) Schematic showing the electric-field-induced desorption of water molecules into the ambient atmosphere under positive VGS stress. Data from [72]. for improving stability. The general merits and demerits for each device structure has been already discussed in section 2. The etch stopper (ES) structure shows a quite stable BITS performance compared to the BCE structure [38] because the etch stopper layer plays a role as another protection layer to the ambient conditions (Fig. 11). In addition, a device with a double etch stopper layer has been also suggested. [80] The double ES layer consisted of a lower ES layer for minimizing variation of oxide semiconductor properties during deposition and an upper ES layer for protecting molecule penetration from the ambient conditions. Another interesting configuration is the double gate structure. Even though it is relatively complicated due to the fabrication of another gate on a passivation layer, it shows more stability than any other single gate devices (Fig. 12). [76]

9 J.-Y. Kwon et al.: Transparent Amorphous Oxide Semiconductor Thin Film Transistor 9 Fig. 10. The Vth shift values as a function of the applied NBITS time for various humidity conditions. Data from [66]. Fig. 12. Time evolution of VT during PBTS (VGS=+20 V, VDS= +0.1 V, and Temperature=60 C), NBTS (VGS=-20 V, VDS=+10 V, and Temperature=60 C), and NBITS (NBTS with backlight luminance =3000 cd/m 2 ) of DG and SG GIZO TFTs. Data from [76]. Fig. 11. Vth variations for BCE and ES structures. For comparison, the variations in the Vth values for both devices without light illumination under the identical stress condition were included The Vth values were evaluated at the gate voltage inducing the I DS of L/W 10-8 A. Data from [38]. 6. SUMMARY The oxide semiconductor thin film transistor is a great candidate for the backplane for next generation AMLCDs and AMOLEDs because of its high electrical performance and the good spatial uniformity. From the viewpoint of cost, it is comparable to the conventional a-si thin film transistor, which is well-known as a low-cost device. It is thought that the oxide semiconductor thin film transistor could be the only candidate for next display module until now. Despite the discussed strong advantages, research on stability is still an emerging field. Not only material and process but also structure and even environment are strongly related to reliability. A more serious issue is the lack of basic understanding of the ionic bonding-based semiconducting material itself and of the mechanism of operating and degrading of devices under various conditions. However, since the first report on the oxide TFT in 2003, many obstacles have been overcome by the efforts of dedicated researchers within a shorter time than it took for the Si device technology to be developed. If we consider the oxide TFT as a new material and device, not a device derived from Si technology, it will lead to a bright future for oxide TFTs. REFERENCES 1. J. Y. Kwon, K. S. Son, J. S. Jung, T. S. Kim, M. K. Ryu, K. B. Park, B. W. Yoo, J. W. Kim, Y. G. Lee, C. Park, S. Y. Lee, and J. M. Kim, IEEE Electron Device Lett. 29, 1309 (2008). 2. K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, Nature 432, 488 (2004). 3. K. Nomura, A. Takagi, T. Kamiya, H. Ohta, M. Hirano, and H. Hosono, Jpn. J. Appl. Phys. 45, 4303 (2006) (2006).

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