Carbon Nanotube Synaptic Transistor Network for. Pattern Recognition. Supporting Information for

Transcription

1 Supporting Information for Carbon Nanotube Synaptic Transistor Network for Pattern Recognition Sungho Kim 1, Jinsu Yoon 2, Hee-Dong Kim 1 & Sung-Jin Choi 2,* 1 Department of Electrical Engineering, Sejong University, Seoul 05006, Korea 2 School of Electrical Engineering, Kookmin University, Seoul 02707, Korea *Correspondence to S. J. C. (sjchoiee@kookmin.ac.kr). S-1

2 1. Microscopy image of the fabricated devices Figure S1. Microscopy images of the fabricated devices. The channel length and width ranges were deliberately controlled to obtain deviations in the optimized analog channel conductance, which were not due to fabrication variation. Although we initially attempted to obtain a dependency of channel conductance change ( G) characteristics by controlling the channel area (lengths and widths ranging from µm and µm, respectively), we found that the modulation of the channel conductance change was not significantly determined by the channel area (length width), especially with such a large area. S-2

3 2. Electrical properties of CNT synaptic transistors and their variability In this study, we experimentally utilized inkjet-printed synaptic transistors created with a preseparated, semiconducting enriched single-walled CNT solution (90%) processed by a density gradient ultracentrifuge separation method. S1 The selective removal of metallic CNTs has been shown to dramatically reduce the leakage path, enabling the realization of high I on /I off. -I DS (A) V DS = -0.5 V 1 min 3 min 5 min 7 min W = 300 ~ 490 µm L = 170 ~ 480 µm V GS (V) Log(I on /I off ) W = 300 ~ 490 µm L = 170 ~ 480 µm Deposition time (min) Figure S2. Transfer characteristics (drain current, I D versus gate voltage, V G ) and summarized on/off ratio (I on /I off ) of four sets of the devices (total 288 devices) produced with different deposition time of 1 min, 3 min, 5 min, and 7 min. Figure S2 shows the transfer characteristics of a total of 288 devices in four different sets (1 min, 3 min, 5 min, and 7 min) for the deposition time of solution-processed 90% semiconducting CNTs. The results clearly show that as the CNT deposition time was increased from 1 min to 7 min, the average log(i on /I off ), decreased from 4.81 to We correspondingly selected the short 1 min deposition time for a CNT synaptic transistor because it showed a significantly higher S-3

4 on/off ratio compared with those obtained using a longer deposition time (3 min, 5 min, and 7 min), which can provide a larger range of analogue conductance modulation. The device-to-device variability is demonstrated by the transfer characteristics of the CNT synaptic transistors, which arises from the variation in the number of connecting paths between source and drain electrodes. However, variability is still less than that in conventional twoterminal-based resistive devices (i.e., conventional memristor), which is a significant advantage for the implementation of a large-scale synaptic transistor network. The variability can further be improved using higher semiconducting enriched nanotube solutions and a higher density in the network channel of transistors. S2 S-4

5 3. Hysteresis in CNT synaptic transistors The hysteresis of CNT transistors has already been studied in depth in other studies; it is generally accepted that charge trapping by water is an important cause of the hysteresis of CNT transistors exposed to the ambient environment. It has been shown experimentally S2-S6 that two types of water charge traps exist. Type-I traps involve water molecules that are weakly adsorbed on the CNT surface; these molecules can be easily removed by pumping in a vacuum. However, type-ii traps involve SiO 2 surface-bound water in close proximity to the CNT. It is well known that a monolayer or submonolayer of hydrogen-bonded water remains on SiO 2 and cannot be removed by pumping in a vacuum over extended periods of time at room temperature. The thermally grown SiO 2 surface consists of Si-OH silanol groups and is hydrated by a network of water molecules that are hydrogen-bonded to the silanols. Consequently, a multilayer of surfacebound water could exist in ambient air due to the hydrogen bonding among water molecules. This is responsible for the residual hysteresis observed with the CNT transistors. This hysteresis of channel conductance with long-term retention is an invaluable characteristic for the implementation of synaptic functions. Channel conductance can be modulated in an analogue manner using this method, which is of particular importance because it is not easily obtainable from other nanoelectric devices or even memristors. S-5

6 4. Long-term effect of STDP The long-term characteristic of STDP is verified by measuring the memristor conductance hours and days after the application of the spikes. Figure S3 shows that the modulated conductance states exhibit no sign of decay even 7 days after the application of the spike pairs. This long-term behavior is because the conductance change caused by the trapping/detrapping effect is long-term. initial read 3.5 V, 50 ms potentiation or depression -3.5 V, 7 ms 1 st read 2 nd read 3 rd read 4 th read -3 V pre-spike (V pre- ) post-spike (V post- ) 1 min 1 day 3 days 7 days time G/G (%) G/G (%) st read (after 1 min) rd read (after 3 days) t (ms) nd read (after 1 day) th read (after 7 days) t (ms) Figure S3. Long-term effect of STDP behavior. The device conductance was measured 1 min, 1 day, 3 days and 7 days after the application of the spikes, and no decay in the conductance was observed. S-6

7 5. Pattern recognition simulation parameters All simulations are performed using C++ code. The code runs on a traditional personal computer, and the simulation time was approximately 6 hours per run on an Intel i7-3630qm CPU running at 2.4 GHz with 8 GB of memory. Conductance, G [µs] potentiation depression Pulse Number Figure S4. Analogue conductance-switching behavior and its fitting curve (red line). As shown in Fig. S4, analogue conductance switching in a synaptic transistor can be fitted by a simple exponential model, as discussed in the primary text (Eqs. (1) and (2)): δ G = γ + α e (for potentiation) p p p G Gmin β p Gmax Gmin δ G = γ + α e (for depression). d d d Gmax G β d Gmax Gmin The fitting parameters for analogue conductance switching are defined as G min = 0.79 µs, G max = µs, α p = , α d = , β p = β d = 4.739, and γ p = γ d = To simulate neuron operation, the following simple equation should be solved (Eq. (3)): dx τ dt + X = I input, where τ = 100 ms and X th = 90 µa. In addition, to implement homeostasis in S-7

8 the simulation, the following equation (Eq. (4)) that adjusts X th should be solved: dx th dt =γ ( A T ), where A is the firing rate of each neuron, T is the target activity, and γ is a multiplicative positive constant (γ = 0.05). In this study, T is set equal to 1/10 because ten different digits will be learned with ten output neurons. To achieve learning, the full MNIST training database (60,000 digits) is processed by the system. Each input neuron is connected with one pixel of the image and fires pre-synaptic spikes (V pre- ) that are proportional to the pixel intensity (the pulse width of V pre- (t pre ) is proportional to the pixel intensity). The initial channel conductance synaptic transistor network is random (G min = 0.79 µs, G max = µs). The input neurons fire pre-synaptic spikes corresponding to a given digit within 300 ms, after which they fire spikes corresponding to another digit. No type of preprocessing is used on the digits, and the set is not augmented with distortions. The network is then tested on the MNIST test database, which consists of 10,000 digits that were not available to the system during training. S-8

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