incidence log(fault weight)

Transcription

1 Fault Modeling and Defect Level Projections in Digital ICs J.T. Sousa, F.M. Goncalves, J.P. Teixeira, T.W. Williams INESC/IST, 117 Lisboa CODEX, PORTUGAL IBM, Boulder, Colorado , USA Keywords: VLSI chips, Physical Defect, Layout Fault Extraction, Stuck-at Fault Model, Yield, Fault Coverage, Defect Level Abstract This paper presents a new model for evaluating the Defect Level, DL, in VLSI circuits as a function of the yield, Y, and the stuck-at fault coverage, T. It is shown that the observed DL(T ) curve can be accurately modeled using non equally probable, realistic faults predicted from defect statistics data and IC layout. The deviation of DL(T ) from the one estimated by the Williams-Brown equation is shown to be caused by two eects. First, the topology of the most likely realistic faults determine their susceptibility, which is typically lower than the stuck-at fault susceptibility. Second, the incompleteness of a given test set and the detection technique (such as static voltage testing) determine a non 1% defect coverage. The suitability of the model was assessed by means of layout fault extraction and switch-level fault simulation, and the results obtained agree with previously published DL(T ) experimental results on actual ICs. 1 Introduction The nal objective of testing is to prevent faulty devices to arrive to the market. As this is a very greedy goal, one should be able to, at least, estimate and minimize the number of shipped faulty chips. Williams and Brown [1] have derived a well known formula for computing the defect level DL as a function of the yield Y and of the fault coverage T : DL = 1? Y 1?T (1) The computed fault coverage is usually the single line stuck-at fault coverage. In the Williams-Brown model, dies are assumed to have equally probable stuck-at faults to model the impact of actual defects. The yield value can be predicted using some existing methods [2, 3] or can be approximately measured by means of experimental procedures, as well as the defect level value [4]. It was observed that the DL(T ) experimental curve largely deviates from the curve predicted by equation (1) [4, 5]. Agrawal et al [6] have postulated a Poisson distribution for the number of faults on a faulty chip, being n the average number of faults on a faulty chip. This hypothesis is related to the fact that a physical defect usually corresponds to a multiple fault [7]. This approach has led to a new equation relating yield, fault coverage and defect level, which is additionally characterized by the n parameter: DL = (1? T )(1?Y)e?(n?1)T (2) Y + (1? T )(1?Y)e?(n?1)T The n parameter can be determined by curve tting equation (2) to the experimental curve. By selecting an adequate value of n, a good matching with experimental data can be obtained [4]. However, only by admitting fault multiplicity, this last model does not solve the problem of an hypothetical, abstract fault model. Moreover, it is well known that a simple voltage test, e.g. in CMOS chips, is not sucient to cover all faults induced by physical defects. To solve this problem, other detection techniques are being investigated, such as delay fault testing [8] or I DDQ current testing [9]. As a consequence, 1% coverage of stuck-at faults is not synonymous of 1% defect coverage. Recently, a number of authors have suggested that the presence of unmodeled faults could be responsible for another possible cause for the observed deviation between the Williams-Brown and experimental results [1, 11, 12]. According to [12], if unmodeled faults are taken into account to explain the deviation from the Williams-Brown model, one has to admit that there are roughly as many unmodeled faults as there are modeled faults.

2 Coping with the task of generating a defect induced fault list demands for layout analysis. In this approach, known by IFA (Inductive Fault Analysis) [13], every fault is originated by a likely physical defect. In this work, we have used the methodology presented in [14] to extract a list of weighted defect induced faults, modeled at transistor-level. An alternative defect level model is given in [15]. This model is meant to predict the test lenght necessary for random testing. However, no comparison is made with the available experimental data on actual measured defect level values. In a previous work [16], equation (1) was extended to non equally probable realistic faults. The reformulated equation (3) replaces T by, which is a realistic weighted fault coverage measure. DL = 1? Y 1? (3) Each fault is weighted by a factor w j =?ln(1?p j ) (4) that reects its probability of occurrence p j and is calculated in terms of the physical defect densities and critical areas [2]. It can be shown [17], that w j has the physical signicance of the average number of inducing defects for fault j, i.e., w j = A j D j, where A j is the critical area of fault j and D j is its average defect density. As a consequence, Y and are given respectively by: Y = e?p n j=1 wj (5) P m j=1 = w j P n i=1 w i (6) where n is the total number of extracted faults, and m is the number of detected faults. Obviously, the fault set is sorted in such a way that the rst m faults are the detected ones. With this more complete fault model, in this paper, detection probabilities [18] or, equivalently, fault susceptibilities [19] are investigated and compared to stuck-at fault susceptibilities, when random test vectors are applyed. Also it is observed the inability of stuck-at test vectors together with simple voltage detection techniques to cover all the modeled faults. Therefore, a new equation is proposed in this paper, relating DL to Y and T, as in the Williams-Brown model, but exhibiting a dependence on two additional parameters. One parameter reects the discrepancy between the stuck-at faults and realistic faults susceptibilities, and the other one expresses the maximum T(k) (k) e+6 Figure 1: (k) and T (k) for = e 3 2, T = e 3 and max = :96 realistic fault coverage that is possible to achieve with a given test pattern. This paper is structured as follows. In the next section, the proposed model is derived. In section 3, an experimental overview is given. In section 4, simulation results are presented and discussed. Finally, in section 5, the main conclusions are outlined. 2 Defect Level Model Using a fault simulator tool, one can plot the stuckat fault coverage as a function of the number of test vectors. As it is known [19], this curve can be predicted with reasonably accuracy by the following equation: T (k) = 1? e? ln(k) ln( T ) (7) where k is the number of random applyed vectors and T is the fault susceptibility. We assume, for the sake of simplicity, that in the stuck-at fault set the redundant faults can be neglected, so that T (k)! 1 when k! 1. In the same manner, for the weighted realistic fault coverage, one can write: (k) = max (1? e? ln(k) ln( ) ) (8) where max is the maximum coverage that is possible to achieve by using k! 1 vectors and a voltage detection technique. In gure 1, a typical situation is depicted: T (k) and (k) are plotted for T = e 3 ; = e 2 3 and max = :96.

3 By eliminating k in (7) and (8), the relationship between and T is found to be:? = max 1? (1? T ) R (9) where R is the susceptibility ratio given by R = ln( T )=ln( ) (1) That is, if the stuck-at fault susceptibility is greater than the realistic fault susceptibility, then the realistic fault coverage converges faster to max than the stuck-at fault coverage converges to 1. Note that, typically, T > > 1 and, thus, R > 1. R depends on the susceptibility of realistic faults when compared to the susceptibility of stuck-at faults. The susceptibility of a fault set depend, by its turn, on the individual fault detection probabilities. In [2], probabilities of fault detection are used to calculate a more robust fault susceptibility. In summary, R depends on the type of the present faults which is determined by the layout style and by the defect statistics. In fact, fault probability distribution determines the most relevant faults; this, together with the topology of the more relevant faults, determine the global susceptibility of realistic faults. Substituting (9) into (3), it is possible to express the defect level in terms of stuck-at fault coverage, as DL = 1? Y 1?max(1?(1?T )R ) (11) The parameters R and max can be determined by experimental curve tting. For R = 1 and max = 1, equation (11) simply reduces to the Williams-Brown formula (1). In gure 2, DL(T ) for Y = :75 is plotted, both for the Williams-Brown model and for equation (11), with R = 2 and max = :96 (a typical case). Equation (11), which adequately reproduces the shape of experimental fallout data [4], maintains the elegancy of equation (1) and does not rely on assumptions about fault multiplicity of abstract, equally probable stuck-at faults, as in equation (2). Next, two examples are presented to illustrate the usage of the derived model. The former example assumes max = 1, that is, completeness of the test set, but R = 2:1, i.e., higher realistic fault susceptibility. The later example assumes incompleteness of the test set ( max = :99) and neglects fault susceptibilities inequality (R = 1). EXAMPLE 1: how much fault coverage is enough for a chip with Y = :75; max = 1; R = 2:1 and with a required DL = 1ppm? By using (11), the value of T = 97:7% is found. If the Williams-Brown equation was used, we would found the value T = 99:97% which is a much more stringent requirement DL(T ) Williams-Brown DL(T; max = :96; R = 2) Figure 2: DL(T ) (Williams-Brown) and for R = 2; max = :96, with Y = :75 EXAMPLE 2: How much is the defect level for a chip with Y = :75 and 1% stuck-at fault coverage, but having max = :99 and R = 1? By using (11), the value DL = 2279ppm is obtained. If the Williams-Brown model was used, a zero defect level was expected, since T = 1. These two examples show the two additional features of the proposed model, as compared to the Williams-Brown model: the eects of dierent fault susceptibilities and the incompleteness of the test set, for the target detection technique. If R > 1, this means that faults mostly contributing for yield degradation are easier to detect than stuckat faults, in the sense that the required test length is shorter. When bridging faults are dominant, what happens when positive photoresist technology is used [21], it is demonstrated experimentally and by simulation that the global fault susceptibility is lower than the susceptibility T exhibited by stuck-at faults and thus, R is greater than 1. In the Agrawal et al. model, quantied by equation (2), this higher fault detectability is expressed by admitting stuck-at fault multiplicity. This assumption indirectly models reality in fact, bridging faults usually aect multiple nodes in a circuit. However, correlation between hypothetical, equally probable multiple stuck-at faults and realistic non equally probable faults is hard to establish, specially at the design phase. The parameter max, being lower than 1, models the incompleteness of the test set. It clearly demonstrates that testing for stuck-at faults cannot assure 1% of defect coverage and that more elaborated tests, such as current or delay tests, must be developed

4 in order to aim a zero-defect strategy. The quantity 1? Y 1?max has the signicance of a residual defect level, associated with a given detection technique, that one cannot get rid of, if e.g. only steady-state voltage tests are applyed. 3 Experimental Setup The study described in this paper is based on transistor-level fault extraction and simulation, using test vectors generated using the stuck-at fault model. The layout to circuit and fault extraction tool, lift [22], uses a layout-level circuit description, a set of circuit extraction rules and a set of fault extraction rules. In the fault extraction rules le, geometrical rules for fault extraction are given for each defect type, as well as the statistical defect density and size distributions (characterized for fault weighting). The defect density statistics are similar to the ones given in [23, 21]. The extracted faults are shorts and opens with dierent topologies and weights. After fault extraction, an histogram of fault weights is plotted, in order to study the distribution of weights. As it will be shown, this distribution widely inuences the fault coverage results. Switch-level fault simulation using the fault simulator swift [24] produces the weighted fault coverage value,. The test vectors used in fault simulation were obtained using an ATPG for stuck-at faults. The rst vectors are random vectors, being the last vectors deterministically generated using the FAN algorithm [25]. More than 8% fault coverage is in general achieved with random vectors. One can argue that equation (11) was derived assuming that only random test sequences are applyed and so, it is not valid for deterministically generated vectors. Nonetheless, this problem does not seriously aect the results, as we used ATPG vectors in our experiment. In fact, by using only random patterns, the test length would be longer and eventually more non-modeled faults could be detected; however, the main limitation seems to reside in the detection technique steady-state voltage measurement rather than in the test length. Although some other examples were examined, only one example is discussed in this paper. This example is a 2-metal, CMOS implementation of the c432 ISCAS benchmark circuit [26], whose layout was obtained with a commercial standard cell design system. For this circuit, the yield value was scaled to the value of Y = :75 in order to easily compare the simulation results with the theoretical examples given in section 2. Note that scaling the yield value can be interpreted as if the circuit has a dierent size but maintains the same testability features. A test vector sequence t 1 ; t 2 ; :::; t k ; :::; t N was applyed and the values of T (k) and (k) were obtained by gate-level and switch-level fault simulation, respectively. To assess the importance of fault weighting, the values of the non weighted switch-level fault coverage,?(k), were also obtained. Explaining better, for?(k), faults are the same as for (k), but they are considered as having equal probability of occurrence. By plotting T; and? as a function of the vector index k, it is possible to study the susceptibilities and saturation limits for the three curves, as it is shown in the next section. Using equation (3), the value of DL((k)) was computed. Then, assuming that DL((k)) quanti- es the actual defect level, it is pertinent to plot the parametric curve, with parameter k, given by (T (k); DL((k))). This allows us to compare the shape of this curve and the shape of the experimentally measured DL as a function of T as it appears in [4]. Moreover, it can be analyzed how the curve (T (k); DL((k))) deviates from the Williams-Brown equation (1). Assuming that fault weighting is not important, the defect level would be predicted by DL = 1? Y 1??. Therefore, it is also relevant to plot the parametric curve (?(k); DL((k))) and to compare it with the analytical curve DL = 1? Y 1??. In this way, the accurate defect level estimation using (k) can be compared to the estimation that only takes into account the value of?(k), in order to study the possibility of using? in DL projections. 4 Results The histogram of the fault weights, obtained for the used physical design of circuit c432, is plotted in gure 3. This histogram shows that fault weights, or equivalently, occurrence probabilities have a large value dispersion, ranging approximately from 1?9 to 1?6, which cannot be ignored. This clearly invalidates the assumption made by Huisman [12], that this eect could be negligible. Fault weights heavily depend on defect statistics, which vary from process line to process line, and on layout styles. Defects induce dierent fault types, according to their nature. On the other hand, dierent fault types have dierent susceptibilities, which, as explained previously, determines the shape of the experimental DL curve.

5 incidence T (k) (k)?(k) log(fault weight) Figure 4: Fault coverage (%) as a function of the number of test vectors, k, for the c432 circuit. Figure 3: Histogram of fault weights. In gure 4, curves T (k); (k) and?(k) are depicted for the c432 circuit. From this gure it is clear that? > T >. The reason why?(k) < T (k) for high k values is because of the presence of open faults which, as it is known, are harder to detect than bridging faults [27, 28], and are considered with equal likelihood. is much smaller than T and?, due to the defect statistics used, which put emphasis on bridging faults (the practical case in CMOS process lines). DL(T ) given by Williams-Brown formula (1), is plotted in gure 5 together with the simulation obtained points with coordinates (T (k); DL((k))). This simulation data reproduces the concavity also exhibited by actual fallout data [4] and predicted by equation (11). In the same gure there can be seen the curve DL(T; max = :96; R = 1:9). The values max = :96 and R = 1:9 were chosen to best t the simulation curve (T (k); DL((k))). As gure 5 shows, the theoretical curve matches very well the simulation data, what illustrates the suitability and the accuracy of the proposed model. In gure 6, the curve DL = 1?Y 1?? is plotted and labeled as DL(?), together with the simulation points (?(k); DL((k))). A similar deviation, as the one observed in the plot (T (k); DL((k))) of gure 5, can be observed between the theoretical points and the experimental ones. This can be easily inferred from gure 4, where both plots T (k) and?(k) exhibit close values of fault susceptibility. Thus, only by having a complete but non weighted fault set, one cannot accurately predict DL by using the non weighted fault coverage?(k) in the Williams-Brown equation. The fault set must be weighted according to equation (4), in order to determine the accurate fault susceptibility value,. 5 Conclusions Rather than using abstract, single or multiple fault models, such as the stuck-at fault model, it is worthwhile to understand and model the physical mechanisms behind faults. In fact, abstract models either lead to inaccurate DL(T ) projections (case of the stuck-at fault model), or lead to a posteriori DL(T ) projection, empirically obtained by curve tting (case of the Agrawal et al. model [6]). Inductive fault analysis can, in fact, overcome the problem of considering non realistic faults and consequently, the uncertainty of covering actual physical defects. In this perspective, fault occurrence probabilities are important to dene the relative weight of each fault in the fault set. Fault detectabilities vary among the dierent fault types. Computing the relative weights of the dierent fault types leads to the determination of a realistic fault susceptibility, which is an important parameter for defect level estimation. The stuck-at fault model, together with a simple steady-state voltage test analysis are not sucient to ensure high quality levels for VLSI circuits. Transistor-level bridging and open faults and more

6 Williams-Brown DL(T ) DL(T; max = :96; R = 1:9) (T (k); DL((k))) concavity of the DL(T ) curve. Furthermore, the limitations of the test set and of the detection technique, for each realistic fault set, dene max, and the product residual defect level, 1? Y 1?max. Our results were validated, as they are in accordance with actual fallout data and with switch-level fault simulation results. Conversely, the proposed model can be used, together with DL(T ) experimental curves, to tune assumed defect statistics in a process line Figure 5: Defect level as a function of stuck-at fault coverage, T, for the c432 circuit DL(?) (?(k); DL((k))) Figure 6: Defect level as a function of non weighted fault coverage? for the c432 circuit sophisticated detection techniques, like delay and/or current testing, must become part of the production routine, if a zero defect level strategy is aimed. This is already being understood by industry. In this paper, a new model for the accurate evaluation of DL(T ) was proposed to account for fault occurrence probability dispersion and the incompleteness of the traditional stuck-at fault model. The model can be fully characterized by experimental procedures with no need to make abstract assumptions about the nature of faults. Predictions of Y; DL; R and max can be obtained at the design phase, and can be ascertained during test application, in IC production. It was demonstrated that the topology of the most likely faults determine their susceptibility, and the observed Acknowledgements The work reported in this paper was partially supported by the EC, in the context of Esprit 717 Project, ARCHIMEDES. Support from JNICT is also appreciated. References [1] T.W. Williams and N.C. Brown. "Defect Level as a Function of Fault Coverage". IEEE Transactions on Computers, C-3(12):987{988, Dec [2] C. H. Stapper, F. Armstrong, and K. Saji. "Integrated Circuit Yield Statistics". Proc. IEEE, 71:453{47, Mar [3] Jose Pineda de Gyvez. "IC Defect-Sensitivity". PhD thesis, Tech. Univ. Eindhoven, April [4] P.C. Maxwell and R.C. Aitken. "The Eect of Dierent Tests Sets on Quality Level Prediction: When is 8% Better than 9%?". In Proc. Int. Test Conference (ITC), pages 358{364, [5] D.V. Das and S.C. Seth. "An Experimental Study on Reject Ratio Prediction for VLSI Circuits: Kokomo Revisited". In Proc. Int. Test Conference (ITC), pages 712{72, 199. [6] V.D. Agrawal, S.C. Seth, and P. Agrawal. "Fault Coverage Requirement in Production Testing of LSI Circuits". IEEE Journal of Solid State Circuits, SC-17(1):57{61, Feb [7] V.K. Agarwal and A.S.F. Fung. "Multiple Fault Testing of Large Circuits by Single Fault Test Sets". IEEE Transactions On Computers, C- 3(11):855{865, Nov [8] E.S. Park, M.R. Mercer, and T.W. Williams. "A Statistical Model for Delay-Fault Testing". IEEE Design and Test of Computers, 6(1):45{55, February 1989.

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