Automatic Test Pattern Generation for Resistive Bridging Faults

Transcription

1 Automatic Test Pattern Generation for Resistive Bridging Faults Piet Engelke 1 Ilia Polian 1 Michel Renovell 2 Bernd Becker 1 1 Albert-Ludwigs-University Georges-Köhler-Allee Freiburg i. Br., Germany {engelke polian becker}@informatik.uni-freiburg.de 2 LIRMM UMII 161 Rue Ada Montpellier, France renovell@lirmm.fr Abstract An ATPG for resistive bridging faults is proposed that combines the advantages of section-based generation and interval-based simulation. In contrast to the solutions introduced so far, it can handle arbitrary non-feedback bridges between two nodes, including ones detectable at higher resistance and undetectable at lower resistance, and faults requiring more than one vector for detection. Keywords: ATPG, Resistive short defects, Bridging faults, SAT. 1 Introduction Resistive bridging faults [1, 2] have recently received increased attention. Several authors considered modeling [3, 4, 5] and simulation [6, 7, 8, 9] of this fault class. It has also been employed for analysis of low-voltage testing [10, 11, 8, 12]. The main difficulty in handling resistive bridging faults is the presence of a continuous parameter that is unknown in advance, the bridge resistance R sh. A resistive bridging fault induces intermediate voltages (between 0 and DD ) at the bridged lines. A gate G with inputs fed by these lines (we call such a gate a successor gate) interprets these voltages as logical values 0 or 1 according to its input threshold Th G. The voltage and hence the interpreted logic value is a function of R sh. For sufficiently high values of R sh, the successor gate interprets the same logical value as in the fault-free circuit (good-value). In general, G interprets the faulty-value for R sh lower than a certain bridge resistance R G. R G is called critical resistance of G. The critical resistance is a function of the fault considered, the successor gate (there might be several of them with different thresholds) and the logical values on the inputs of the gates that drive the bridged lines (Multiple Strengths Problem [9]). For a given fault, there are m > 0 critical resistances R 0 := 0Ω < R 1 < < R m <. 1 R max := R m 1 Note that the highest possible number of critical resistances is dependent on the set of logic gates occurring in a circuit but not on the size of the circuit. is called the maximal critical resistance. 2 Fault simulation for resistive bridging faults determines for which values of R sh a given fault is detected by a test vector. These values form an Analogue Detectability Interval (ADI) [3]. The ADI has often the form [0, R max ], but in some cases it is actually a union of disjoint intervals [4]. If more than one vector is applied, the union of ADIs is called C-ADI (covered ADI). C-ADI includes all the R sh values for which at least one vector detects the fault. C-ADI of the exhaustive test set is called G-ADI (global ADI). G-ADI contains those bridge resistances for which the fault is detectable; for all other R sh values it is redundant. As for ADI, both C-ADI and G-ADI are often [0, R max ], but they could also be subsets of [0, R max ], and even disjoint unions of several intervals. To assess the quality of a test set, its C-ADI is related to G-ADI, weighted by the bridge resistance distribution, resulting in probabilistic fault coverage metrics [4]. See [9] for a discussion on different fault coverage definitions. Automatic test pattern generation for resistive bridging faults has been targeted in [8, 14, 15]. The goal of [14] is to guarantee the application of all possible values at the bridge site without detailed electrical analysis. In [8], a PODEMlike approach is used. The emphasis is on identifying the highest R sh value for which the fault can be detected. So, if one vector detects the fault for R sh [0,R 1 ] and another vector detects the fault for R sh [0,R 2 ] (R 1 > R 2 ), the method from [8] would try to obtain the first vector. The approach is based on trying to justify and propagate the fault effect for the largest possible value of R sh. However, a vector that detects a fault for a high R sh value does not necessarily detect it for all lower resistances [4]. There are also faults which need more than one vector (one that detects it in, say, [0,R 3 ], and the other detects it in [R 4,R 5 ], R 4 < R 3 < R 5. The fault is detectable in [0,R 5 ] but there is no single vector that achieves this). The approach in [8] does not generate multiple vectors for a single fault. ATPG results are reported in [8] for three ISCAS circuits generated using a prototype implementation in tcl/tk. The sectioning approach from [15] considers the critical 2 See [13] for a discussion on the dependence between the critical resistance concept and noise effects.

2 resistances R 0 := 0Ω,R 1,...,R m in ascending order. A section is an interval [R i,r i+1 ] with no other critical resistances in it. For m critical resistances, there are m sections. A resistive bridging fault between the lines a and b is then substituted by m sectioned faults (the ith of them is a bridging fault between a and b with a bridge resistance from the ith section, i. e. between R i and R i+1 ). Such faults have Boolean behavior, i. e. it is possible to specify a Boolean function for the faulty behavior. This avoids the need for dealing with the intervals, and improves the test vector quality compared with [8], but the number of considered faults grows. The technique is particularly inefficient if there are many sections with identical behavior for almost all test vectors. There are no experimental results for ATPG in [15]. In this work, we combine the advantages of the intervalbased and the sectioning approach. We generate vectors targeting a section. We target the section with the highest boundaries first, because it is probably the most difficult one to detect and because a test vector for this section is likely (but is not guaranteed) to detect lower sections of the same fault. The test generation itself is implemented by constructing a conjunctive normal form (CNF) of the fault-detecting circuit and invoking the SAT solver Chaff [16]. Then, the R sh ranges are identified for which the generated test vector detects the fault. This is done using interval-based fault simulation [9] (of the target fault as well as of all other faults). By doing so, we avoid the need to simulate many sections with almost identical behavior, which would be required in the pure sectioning-based approach. All faults for which the whole G-ADI has been covered are dropped. It is possible that the target fault is not dropped, although a test vector for the highest section has been found. In this case, the highest section not covered yet is targeted by ATPG. In this way, faults requiring multiple test vectors are treated accurately. If no test vector for a section can be found, then the section under consideration is redundant, and it is excluded from G-ADI (initially, G-ADI is set to [0,R max ], which is its superset). Consequently, we get accurate values of G-ADI in the end of the ATPG run as a by-product. The only approach for calculating G-ADI known so far was based on exhaustive simulation which was only feasible for small circuits. The remainder of the paper is organized as follows: in Section 2, basic concepts are illustrated on a small example circuit. The ATPG algorithm is introduced in Section 3. In Section 4, experimental results are reported. Section 5 concludes the paper. 2 Introductory example The example circuit in Figure 1 illustrates a situation in which two vectors are required to detect a fault for all resistances for which it is detectable. 3 Here, the fault in question 3 Note that we consider static test application in this paper. This is in contrast to two-pattern testing required to detect delay faults. In delay fault a b Th A Th B/F Th A Th B/F a R sh b A B Figure 1: Example circuit R B R A R F (i) (ii) c d F a b R sh b a R sh Figure 2: R sh - -diagram for the vector 10 (i) and 01 (ii) is the resistive bridging fault between the lines a and b. The fault-free circuit computes the equivalence (XNOR) function (a b) on the output e and propagates the value of a to the output f. The behavior of the faulty circuit depends on the logical values interpreted by the gates A (an inverter), B and C (both are identical buffers) driven by the bridged lines a and b, as shown in the figure. These logical values are a function of the voltages a ( b ) on the line a (b) and the thresholds Th A (Th B/F ) of the gate A (B and F, which are of the same type). The voltage, in turn, depends on the resistance R sh. The faulty behavior of the circuit might be exposed by one of the test vectors 10 and 01, because the vectors 00 and 11 do not excite the bridge. The R sh - diagrams in Figure 2 (i) and (ii) show possible characteristics of a and b as a function of R sh for the vectors 10 and 01, respectively. For small R sh values, the voltage a is close to b, but for a higher R sh the impact of the fault is weaker and the voltage difference becomes higher. For an infinite R sh (effectively, testing, the two vectors must be applied at-speed and their order is relevant. Neither of this is required for the detection considered here. Resistive bridging faults may also result in delay faults (see [17] for details). f e

3 there is no fault at all), a and b correspond to the fault-free values. The thresholds of the inverter A, Th A, and of the buffers B and F, Th B/F, are also shown in Figure 2 (obviously, the thresholds of the gates are independent from R sh ). We assume Th A > Th B/F. Consider the vector 10 (Figure 2 (i)). R A is the projection of the intersection of a and Th A to the abscissa, and R B is the projection of the intersection of b and Th B. For R sh < R B, the gate A interprets logic-0 on a, resulting in c = 1. B interprets logic-1 on b, hence d = 1 and e = 0 (which is also the fault-free value). For R B < R sh < R A, A interprets logic-0 (c = 1) and B interprets logic-0 (d = 0, e = 1, fault is detected on the output e). For R sh > R A, A interprets logic-1, and B interprets logic-0 (resulting in c = d = e = 0 and thus no detection on e). The buffer F interprets logic-1 irrespectively of R sh, so vector 10 does not detect the fault on f. For the vector 01 (Figure 2 (ii)), the voltage on a is interpreted as logic-0 by the inverter A and the voltage on b is interpreted as logic-1 by the buffer B for all values of R sh. Consequently, the fault-free value e = 0 is assumed independent of the bridge resistance. The buffer F, in contrast, interprets logic-1 on a for R sh < R F and logic-0 for all other R sh values and also in the fault-free case. Observe that R F = R B, because both are identical buffers. Hence, the vector 01 detects the fault for R sh < R B. Overall R B = R F and R A are critical resistances, R A is R max, and [0,R B ] and [R B,R A ] are sections. The vector 10 detects the fault in the section [R B,R A ] but not in the section [0,R B ], while the vector 01 detects the fault in the section [0,R B ] but not in the section [R B,R A ]. Consequently, both vectors are required for detection of the fault in the maximal R sh range. Now, we outline the ATPG procedure capable of generating a test set also for such non-trivial cases. We determine the Boolean function of the fault-free circuit, bf, and also the Boolean function for each section. In our example, bf(a,b) = (e(a,b),f(a,b)) = ((a b),a). For the section [0,R B ], the function is bf [0,RB](a,b) = ((a b),(a b)). For the section [R B,R A ], the function is bf [RB,R A](a,b) = ((a b),a). The ATPG procedure targets the section [R B,R A ] first, because it is higher than [0,R B ]. It is often more difficult to detect a fault for a higher R sh than for a lower R sh. Consequently, a test vector that detects the fault for R sh [R B,R A ] is more likely to detect it for R sh [0,R B ] than vice versa. To generate the test vector, the ATPG algorithm computes bf(a,b) bf [RB,R A](a,b) = ((a b) (a b),a a) = (a b,0). The test vector must set at least one component of bf bf [RB,R A] to 1, so the only test vector is ab = 10. Unfortunately, the vector 10 does not detect the fault in the section [0,R B ]. Hence, the ATPG procedure targets that section separately, resulting in bf(a,b) bf [0,RB](a,b) = Procedure Res ATPG Input: Circuit C, fault list F = f 1,f 2,... Output: Test set = v 1,v 2,... that cover G-ADIs of all faults in F (1) := ; (2) for each f F begin (3) Compute R max ; (4) G f := [0,R max ]; L f := [0,R max ]; (5) end for (6) while (F not empty) begin (7) f := the first fault from F ; (8) Compute critical resistances for f: 0Ω = R 0 < R 1 < < R m < ; (9) int j := max{k [R k 1,R k ] L f }; (10) vector v := gen test(c, f, [R j 1,R j ]); (11) if (no v found) begin (12) G f := G f \ [R j 1,R j ]; (13) L f := L f \ [R j 1,R j ]; (14) if (L f == ) drop f; (15) end if (16) else begin (17) := {v}; (18) for each f F begin (19) interval D := fsim(c, f, v); (20) L f := L f \ D; (21) if (L f == ) drop f ; (22) end for (23) end else (24) end while (25) return ; end Res ATPG Figure 3: ATPG procedure for resistive bridging faults ((a b) (a b),a (a b)) = (0,ab) and the test vector 01 (which is the only vector detecting the fault). Overall, the vector 01 is required for detecting the fault in section [0,R B ], and the vector 10 is needed for detecting the fault in section [R B,R A ]. In our notation, the C-ADI of a test set {01} that contains only one vector 01 is [0,R B ], and the C-ADI of the test set {10} is [R B,R A ]. The G-ADI, [0,R A ], cannot be covered by any single vector. Thus, the fault requires two vectors for the best possible detection. In the next section, we describe the ATPG procedure in more detail. 3 ATPG Procedure We denote the fault list as F = {f 1,f 2,...}. If f 1 is dropped from the list, then f 2 becomes f 1, and so forth. For a fault f, the interval G f denotes the G-ADI of this fault (it is accurate only in the end of the computation and is overapproximated in the beginning). L f is an interval which contains those R sh ranges which are left to detect. When L f becomes empty, the fault is dropped. The ATPG algorithm is shown in Figure 3. First, both intervals G f and L f are set to [0,R max ] for each fault (Lines

4 2 5). Note that the value of R max may be different for different faults. It is calculated using local analysis of the fault site. The main loop of the algorithm includes Lines Faults from the fault list F are targeted until all faults are dropped. A fault is dropped if each of its sections is either detected by one of the test vectors generated so far or proven redundant. Critical resistances for fault f under consideration are computed (Line 4) using exhaustive simulation at the fault site (i. e. all possible values are applied to the inputs of the gates driving the bridged lines). For two-nodes-bridges which we consider, 2 n1+n2 vectors are applied, where n 1 and n 2 are the numbers of inputs of the driving gates, so the computational cost of this operation is acceptable. Note that, in general, some of these vectors cannot be justified from the primary inputs of the circuit. The list of critical resistances is calculated only for the fault f. This is in contrast to the pure sectioning-based approach, where all the critical resistances for all the faults have to be known at the same time. Moreover, a fault could be dropped before having been considered. For such a fault, no critical resistance computation is required at all. Once the list of critical resistances is available, the highest section [R j 1,R j ] not covered so far is identified (line 9). In line 10, Procedure gen test is called. It is a subroutine that takes a circuit, a resistive bridging fault and a section and tries to generate a test vector. It works in the following manner: let a circuit have n inputs and p outputs. Procedure gen test constructs the Boolean function of the fault-free circuit, bf C : B n B p, and the Boolean function of the faulty circuit, bf C,f,[Rj 1,R j] : B n B p. bfc i and bfc,f,[r i j 1,R j] denotes the Boolean function of the ith output of C. Test generation is performed by finding an assignment for x 1,...,x n satisfying the formula p i=1 ( ) bfc(x i 1,...,x n ) bfc,f,[r i (x j 1,R j] 1,...,x n ). The SAT solver Chaff [16] is used for this purpose. (It is used as a sub-routine for test generation; it would be possible to use an other, e. g. circuit-structure-based, algorithm for this purpose as well.) If test generation fails (SAT instance unsatisfiable), then the section in question is redundant and must be excluded from both G f and L f (Lines 11 13). If all other sections of the fault f under consideration have been either covered or proven redundant, f is dropped. If the SAT instance could be satisfied, the returned variable assignment yields a test vector. (In the version of Chaff we used, the variable assignment is completely specified, i. e. the test vector has no don t care values.) It is added to the list of vectors generated so far (Line 17). Then, the fault f as well as all other faults are simulated with this vector using the routine fsim. fsim takes a circuit, a fault and a test vector, and returns the R sh interval D in which the test vector detects the fault. See [9] for details of the fault simulation procedure. If D is not empty, then the intervals L f (which contain the bridge resistances left to detect) are reduced. This decreases the number of sections that will have to be targeted later on. If L f becomes empty, the fault f can even be dropped (Line 18 23). If the found vector could not cover all the sections, the while loop is repeated, until each section is either covered by a vector or proven redundant. In the (theoretical) worst case, the while loop is entered m times, where m is the number of sections. However, this guarantees accurate handling of the faults requiring more than one vector for best detection. 4 Experimental Results The ATPG procedure was applied to ISCAS 85 and the combinational parts of ISCAS 89 benchmark circuits. The fault set consisted of 10,000 randomly selected non-feedback resistive bridging faults, where available. 4 All measurements were performed on a 2GHz Linux machine with 2GB RAM. The results are summarized in Table 1. Columns 2 4 contain the number of faults in the fault list, the number UF of faults that turned out to be undetectable for any value of R sh, and the number of generated test vectors. Note that a fault with m sections is counted as one fault, not m faults. The column Eff quotes the efficiency of the ATPG, defined as the number of faults divided by the number of generated vectors. The number US of undetectable sections is given in the column US. The column G-ADI contains the relation of G-ADI to [0,R max ] averaged over all faults (explained below). The next column quotes the run time of the program in CPU seconds. We compare the efficiency of our ATPG with the RBFTG system from [14], which is based on locally exhaustive test generation. The number of faults used in [14] is given in column 9 (it results from 1,000 randomly selected faults with feedback faults excluded). The number of vectors ( ec ) is the better one achieved by one of the two methods proposed in [14], RDM (based on random pattern simulation) and ALG (based on deterministic ATPG). The last five columns contain information on the performance of state-of-the-art stuck-at ATPG systems ATOM [18] and SPIRIT [19], quoted for comparison purposes. Similarly to our tool, ATOM and SPIRIT incorporate fault simulation, but no post-processing for compaction such as reverse-order simulation or reshuffle. The information given includes the number of collapsed stuck-at faults and, for ATOM and SPIRIT, the number of generated test vectors and the efficiency (number of faults divided by number of vectors). A call of the SAT solver results in either a test vector, a proof that a section is undetectable, or an abort (for the 4 10,000 faults were selected randomly. In an industrial setting, a subset of faults would be extracted from the circuit layout using a procedure such as Indictive Fault Analysis [20]. Unfortunately, no layout information for ISCAS circuits is available to us. The faults used are identical to the ones used in [9] for random pattern simulation.

5 Circuit Resistive ATPG RBFTG [14] #sa- ATOM [18] SPIRIT [19] Faults UF ec Eff US G-ADI [0,R max] Time faults ec Eff faults ec Eff ec Eff c n/a n/a n/a 22 n/a n/a c n/a n/a n/a n/a n/a n/a n/a n/a c n/a n/a n/a c n/a n/a n/a c n/a n/a n/a c n/a n/a n/a c n/a n/a n/a c n/a n/a n/a c n/a n/a n/a c n/a n/a n/a c n/a n/a n/a cs cs cs cs n/a n/a n/a cs cs cs cs cs cs n/a n/a cs cs n/a n/a cs cs n/a n/a cs cs n/a n/a cs n/a n/a cs cs cs cs cs cs cs cs cs Table 1: Experimental results circuits quoted in the table there were no aborts). Hence, the number of calls to the SAT solver equals to the sum of the values in columns ec and US. The number of undetectable sections is quite high, and often higher than the number of generated vectors. To assess the impact of the undetectable sections, we relate the computed G-ADI (which contains only detectable sections) to the interval [0,R max ] which consists of all considered sections. For this purpose, we compute the following number and average it for all the faults in the circuit: ( ) ( ) G-ADI Rmax := 100% ρ(r)dr / ρ(r)dr, [0,R max ] G-ADI 0 where ρ(r) be the probability density function of the short resistance r extracted from the manufacturing data. We used the distribution from [6] which is based on the analysis in [21]. Thus, G-ADI and [0,R max ] are weighted by ρ, in order to account for the short defects that are more likely to occur than others. If the number is 100%, then G-ADI and [0,R max ] perfectly match for all the faults. The larger the difference between 100% and the actual number, the less accurate is the approximation. Overall, the impact of the undetectable sections is much less than what one would expect given their high number: the poorest result is 94.15% (for cs00349), the best result is (for cs13207), and the average over all circuits is 97.65%. This indicates that the undetectable sections are relatively small and include high values of R sh for which the bridge resistance probability is low. The values seem to be largely independent from the size of the circuit. G-ADI is required for accurate calculation of coverage of resistive bridging faults [4, 9]. In the previous work [7, 8, 12], G-ADI was (over)approximated by [0,R max ]. The relation between G-ADI and [0,R max ] given in column 7 of the table also allows us to estimate the accuracy loss induced by this approximation. Although less than 1,000 faults are targeted in [14] (compared to mostly 10,000 faults used here), the sizes of our test

6 sets are comparable and often even smaller. Hence, the efficiency of our ATPG is higher. In addition, our ATPG uses much more realistic assumptions about the model. The number of test vectors generated by our ATPG is generally higher than the number of stuck-at test vectors generated by ATOM and SPIRIT (three notable exceptions being c0499, c1355, c7552 and cs00386). 5 The main reason for this is the higher number of target faults. The picture changes completely when the efficiency is considered: here, our ATPG is considerably better for all but the largest circuits. This is somewhat surprising, as one would expect that there are resistive bridging faults with very specific detection conditions. Such faults would have only a few vectors detecting them, and these vectors may be not useful in detecting other faults. Moreover, at least theoretically, there might be faults that require more than one test vector, as demonstrated in Section 2. On the other hand, a vector that sensitizes an output of a gate might be efficient for detection several bridging faults with that output involved, but only two stuck-at faults. Overall, however, it seems that the vectors that satisfy the detection conditions for the highest values of R sh are also highly effective in detecting other faults. 5 Conclusions We proposed an Automatic Test Pattern Generation system for resistive bridging faults. For the first time, all kinds of non-feedback faults involving two nodes can be treated, including special cases with non-trivial behavior. As a byproduct, it yields the exact value of G-ADI (global analogue detectability interval) that is useful for simulation of such faults. Experimental results are given for ISCAS circuits. Surprisingly, the efficiency of our algorithm is higher than the efficiency of state-of-the-art ATPG methods for stuck-at faults. Our algorithm combines the advantages of sectioningbased test generation implemented by calling a SAT solver, and interval-based fault simulation. There is potential for improving the run time of the algorithm by better utilization of the properties of the SAT instances (for instance, many identical clauses can be re-used by several SAT instances). It is also possible to explore other methods than SAT for actual test generation. Moreover, post-processing approaches like reverse-order simulation or random reshuffle would lead to more compact test sets. Acknowledgment We are grateful to Emil Gizdarski (Synopsis) for providing us with unpublished data on the number of test vectors generated by SPIRIT. 5 Note, however, that for most circuits the fault list is actually a random sample of 10,000 faults, so the expressive power of the comparison may be limited. 6 References [1] H. Hao and E.J. McCluskey. Resistive shorts within CMOS gates. In Int l Test Conf., pages , [2] M. Renovell, P. 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