Electronic Design Automation for Digital Circuits

Transcription

1 Electronic Design Automation for Digital Circuits Tutorial Notes Lecturer: U. Schlichtmann Teaching Assistant: M. Barke Room 296, T barke@tum.de Address: Arcisstr Munich German Telephone: Internet: Contents of Lecture: Microelectronics overview, design flow for microelectronic sstems, design space (Y-chart), implementation fabrics; Logic Snthesis, binar Boolean functions, optimization of combinational circuits (two-level, multi-level), FSMs, optimization of sequential circuits; Logic Simulation, event-driven simulation, modelling and simulation using VHDL; Testing of digital circuits, automatic test pattern generation (ATPG) for combinational circuits, fault simulation, test pattern generation for sequential circuits, scan path, built-in self-test. Issue: Februar 4, 22

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3 Contents I. Logic Snthesis 3 Tutorial : Binar Boolean Functions Tutorial 2: Snthesis of Combinational Circuits using the Method of Quine and McCluske Tutorial 3: Snthesis of Combinatorial Circuits b Methods of Design Automation. 25 Tutorial 4: Binar Decision Diagrams, Tautolog Proof II. Simulation 58 Tutorial 5: Simulation of Digital Circuits Tutorial 6: VHDL III.Testing 72 Tutorial 7: Fault Covering Tutorial 8: Boolean Difference Tutorial 9: Fault Simulation Tutorial : Automatic Test Pattern Generation (ATPG) Tutorial : Snchronous Sequential Circuits CONTENTS

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5 I. Logic Snthesis Tutorial : Binar Boolean Functions Problem Consider the four Boolean functions of the form {,,,} {,} defined as: f (,) =, g(,) = +, h(,) = +, k(,) =. a) Represent the four Boolean epressions b their truth tables. b) For the functions f, g, h and k determine the set of value assignments for which the function value equals one (on-set). c) Represent the four functions b arrow diagrams in which the arrows point from variable value assignments to function values. d) Which of the functions are equal? Which law of Boolean algebra epresses this equalit? e) Draw the decision trees for the functions and epand first w.r.t. and then w.r.t. (order of variables). f) Determine the truth tables, on-sets and arrow diagrams for the following Boolean epressions (product terms, cubes):,,,. How can the mapping function (algebraic form) of an Boolean function with two variables be constructed using these cubes? g) Using these cubes construct the following Boolean epressions:, +, +,,, + and +. For the last four epressions the laws A(3), (4) and (8) should be considered. Note: e.g. = ( + ) = + + = ( + ) = cube graph for n = 2 Logic Snthesis: Problems for Tutorial () 3

6 Problem 2 Consider the 6 Boolean functions of the form {,} 2 {,} defined as: w i = f i (,); i =,,5 i f i (,) i f i (,) i f i (,) i f i (,) = = = = a) Represent the 6 Boolean epressions b their truth table. b) How man different functions eist for n variables ( f : {,} n {,})? c) Obviousl the following holds: = + and = +. Show that the following equations are correct using the laws of Boolean algebra: ( + ) ( + ) = and ( + ) + ( + ) = d) Determine which of the 6 functions have just one element in their on-set and which have just one element in their off-set. e) Determine the on-sets of the following Boolean functions: f 3, f 5, f, f 2, f, f 5 f) Draw the gate level realization of the functions f, f 2, f 7, f 8, f, f 4 How could the functions f 3, f, f, f 5 be realized on gate level? What is the peculiarit of the gate level realizations of the functions f 6 and f 9? Logic Snthesis: Problems for Tutorial (2) 4

7 Problem 3 Consider the five minterms (-cubes) of a Boolean function f of the form f : {,} 3 {,}, m = z, m 2 = z, m 4 = z, m 6 = z, m 7 = z. a) Determine the on-set of each of the minterms and of the Boolean function f. Determine the truth table of f. b) Consider the mapping consisting of onl -cubes: w = f (,,z) = m + m 2 + m 4 + m 6 + m 7. Tr to find a representation with fewer literals using -cubes. For this purpose determine the on-set of f in the simplified notation using the Don t-care smbol. c) Determine the simplest mapping function of w = f (,,z) b using a 2-cube. Determine the on-set of f in further simplified notation. Draw a gate level realization of f. d) Visualize the Boolean function f using a cube graph (n = 3). z z cube graph for n = 3 Logic Snthesis: Problems for Tutorial (3) 5

8 Solution of Tutorial : Problem, Solution a) Truth table: f (,) g(,) h(,) k(,) + + b) On-sets: f = g = {,,}; h = k = {}; c) Arrow diagrams: B 2 f,g B B 2 h,k B d) f = g, h = k Law of De Morgan of the Boolean algebra (see A()) Logic Snthesis: Solution () 6

9 e) Decision trees: + = = = = = = = = f) Truth table: m m m 2 m 3 On-sets: m = {} m = {} m 2 = {} m 3 = {} Arrow diagrams: B 2 m B m : ;,, m : ;,, m 2 : ;,, m 3 : ;,, The elements of the on-set of a Boolean function f are constructed b disjunction (ORing) of the corresponding cubes (building blocks). Representation of f b a sum of products (SOP form). Logic Snthesis: Solution (2) 7

10 g) = The function itself is one of the building blocks. } + = + Each of the functions consists of two + = + building blocks. = + = ( + ) = = + = ( + ) = + = + + = = + + = + + = = + -Cubes Cubes On-Sets + + {} {} {} {} Building blocks for the elements of the on-set of Boolean functions with two variables. Problem 2, Solution a) Representation for f : {,} 2 {,} w i = f i (,); i =,,...,5 i Truth table of all 2 (2n) different Boolean functions with n = 2 variables Logic Snthesis: Solution (3) 8

11 b) Number of functions from A to B m r Number of functions Zf Zf = r r... r (m-times) Zf = r m A f B For m = 2 n and r = 2 results A : input set B : output set Zf = 2 (2n ) A = m B = r m arguments r function values (image elements) For each argument eists eactl one function value. (No fanouts, onl fanins are allowed, uniqueness!) c) Numbering of equivalent epressions ) ( + ) ( + ) = Used laws 2) = A(), (3) 3) = A(4), (8) 4) = A(7), (6) ) ( + ) + ( + ) = 2) = A(2), () 3) = ( + ) + ( + ) A(3) 4) = + A(8), (6) 5) = A(8) d) Onl one element in the on-set: f =, f 2 =, f 4 =, f 8 = Onl one element in the off-set: f 7 = +, f = +, f 3 = +, f 4 = + e) on-sets: f 3 = {,}, f 5 = {,}, f = {,}, f 2 = {,}, f = {} = /, f 5 = {,,,} = B 2 Logic Snthesis: Solution (4) 9

12 f) f f 2 f 7 f 8 f f 4 f 3 f 3 : = + f 3 (high compleit) f 3 (high compleit) (practical situation) f : = ( + ) f f : f f 5 : f 5 ( + ) Own Gate smbol for f 6 and f 9 Implementation with AND/OR-Gates f 6 f 6 f 9 f 9 Logic Snthesis: Solution (5)

13 Problem 3, Solution a) On-Sets: m = {}, m 2 = {}, m 4 = {}, m 6 = {}, m 7 = {}; f = m m 2 m 4 m 6 m 7 f = {,,,, } Function: f (,,z) = z + z + z + z + z z f (,,z) Truth table b) w = f (,,z) = = z + z + z + z + z }{{} + z Idempotence A(4) = ( + ) z + ( + ) z + (z + z) A(3) = z + z + A(8) f = {,, }, simplified notation c) w = ( + ) z + = + z A(3),(8) f = {, }, simplified notation z w Logic Snthesis: Solution (6)

14 d) w = f = m + m 2 + m 4 + m 6 + m 7 five -cubes z w = z + z + three -cubes z w = + z one -cube and one 2-cube z Logic Snthesis: Solution (7) 2

15 Tutorial 2: Snthesis of Combinational Circuits using the Method of Quine and McCluske Problem Consider the on-set of the Boolean function f of the form f : {,} 4 {,} f ={,,,,,,, } f = m + m + m 8 + m 3 + m 5 + m 7 + m 4 + m 5 a) Determine the CSOP for v = f (,,z,w). b) Determine all prime implicants of f using the method of Quine. c) Determine the MinSOP of f using the method of Quine and McCluske. d) Visualize the determination of the MinSOP b a cube graph (n = 4). e) Draw a gate level realization of the MinSOP of f. How man literals could be saved w.r.t. the CSOP of f? Problem 2 Consider a half adder (HA) and a full adder (FA) (addition of two bit binar numbers) with given truth table and gate level realization a b HA Input signals: Output signals: c o s a, b c o (carr-out) s (sum) a c i b FA Input signals: Output signals: c o s a, b, c i (carr-in) c o (carr-out) s (sum) Logic Snthesis: Problems for Tutorial 2 () 3

16 a b c o s (â plus ˆb = ĉ o ŝ) Truth table (TT) HA a b c i c o s (â plus ˆb plus ĉ i = ĉ o ŝ) Truth table (TT) FA a b c o a b HA s = a b c o s = a b c o FA c o c o c o s s = a b c i HA HA s = a b + (a b) c i c i s c o c o = a b = a b = s c i c o = c o + c o s = s c i Eample of a 4 bit adder (ripple-carr-adder) Block diagram (Iterative Structure): a 3 b 3 a 2 b 2 a b a c o,3 c i,3 c o,2 c i,2 c o, c i, c o, c o,3 FA FA FA HA s 3 s 2 s s b Addition: â 3 â 2 â â plus ˆb 3 ˆb 2 ˆb ˆb = ĉ o,3 ŝ 3 ŝ 2 ŝ ŝ e. g. plus Logic Snthesis: Problems for Tutorial 2 (2) 4

17 a) Verif the algebraic epressions for c o and s for the HA and the FA using the corresponding truth tables. b) Determine the MinSOP of c o and s of the FA starting from the TT-FA using the method of Quine and McCluske. Visualize each of the MinSOPs of c o and s in a cube graph (n=3). c) Draw the block diagram of a 2 bit Ripple-Carr-Adder and determine the truth table with output variables c o,, s and s and input variables a, a, b and b. For each line of the TT holds: ĉ o, ŝ ŝ = â â plus ˆb ˆb. d) Determine the MinSOP of the 2 bit Ripple-Carr-Adder for c o,, s and s using cube graphs (n=4). Problem 3 Consider the specification of a combinational circuit for comparing two 2-digit binar numbers (comparator). â â > ˆb ˆb ; â â, ˆb ˆb {,,,} In order to realize the circuit, a mapping function w = f (a,a,b,b ) is emploed with the following specification: ŵ = â â > ˆb ˆb. a) Determine the truth table of the Boolean function f. b) Determine the CSOP of f. c) Determine all prime implicants of f using the method of Quine and determine the Min- SOP of f using the method of Quine and McCluske. d) Visualize the determination of the MinSOP from the CSOP using a cube graph (n=4). e) Draw a gate level realization with a minimal number of gates/literals. Logic Snthesis: Problems for Tutorial 2 (3) 5

18 Solution of Tutorial 2: Problem, Solution a) Function: f (,,z,w) = z w + z w + z w + z w + z w + z w + z w + z w b) Quine s Method: CompSOP of f from CSOP b table of prime implicants m ν -cube A -cube A 2-cube A m z w z p z w p 2 m z w m 8 z w w w p 5 z w m 3 z w m 5 z w z w w m 7 z w m 4 z w z w p 3 z p 4 m 5 z w CompSOP: f = z + z w + z w + z + w f = p + p 2 + p 3 + p 4 + p 5 f = {,,,, } prime cover: pcov( f ) = {p, p 2, p 3, p 4, p 5 } Logic Snthesis: Solution 2 () 6

19 c) Covering of minterms b prime implicants C = (m p + m p 2 ) (m p + m p 5 ) (m 8 p 2 ) (m 3 p 5 ) (m 5 p 5 ) (m 7 p 3 + m 7 p 5 ) (m 4 p 4 ) (m 5 p 3 + m 5 p 4 ) ν C = (τ + τ 2 ) (τ + τ 5 ) τ 2 τ 5 τ 5 (τ 3 + τ 5 ) τ 4 (τ 3 + τ 4 ) due to A(5) holds: τ 2 (τ + τ 2 ) = τ 2 ; τ 5 (τ + τ 5 ) = τ 5 ; (absorption!) τ 5 (τ 3 + τ 5 ) = τ 5 ; τ 4 (τ 3 + τ 4 ) = τ 4 ; C = τ 2 τ 4 τ 5 = MinSOP: f = p 2 + p 4 + p 5 = z w + z + w Comment: Selected are p 2, p 4, p 5, i.e. τ 2 =, τ 4 =, τ 5 =. Not selected are p, p 3, i.e. τ =, τ 3 =. Representation b covering table: m p m m m 8 m 3 m 5 m 7 m 4 m 5 p p 2 p 3 p 4 p 5 Option : Determination of the essential prime implicants p 2 (due to m 8 ), p 4 (due to m 4 ) and p 5 (due to m 3 or m 5 ). Option 2: The reduced covering table shows, that the covering condition is alread met (compare to the structure of C). Deletion of m (due to dominance b m 8 ), m 5 (due to m 4 ), m and m 7 (due to m 3 or m 5 ). Note: From the reduced covering table, the prime implicants p 2, p 4 and p 5 must be selected (compare to the structure of C). For ver large covering problems additional heuristic methods are applied. Logic Snthesis: Solution 2 (2) 7

20 d) All prime implicants and the MinSOP (bold lines) of f are marked in the cube graph. p 3 z w p 4 = z p 5 = w p z w Cube graph (n = 4) p 2 = z w e) Gate level realization: z w 32 8 = 24 literals 24 of 32 literals could be saved v Logic Snthesis: Solution 2 (3) 8

21 Problem 2, Solution a) TT-HA from c and s is trivial. TT-FA from c and s: m ν a b c i a b a b (a b) c i c s m m m 2 m 3 m 4 m 5 m 6 m 7 TT-FA The algebraic epressions are described correctl b the truth tables. b) Step : Determination of the CSOP from the TT-FA c o = m 3 + m 5 + m 6 + m 7 = a b c i + a b c i + a b c i + a b c i s = m + m 2 + m 4 + m 7 = a b c i + a b c i + a b c i + a b c i The CSOP of s consists of onl minterms with pairwise distance δ = 2. Due to that the specialized consensus can not be applied. Thus holds for s: CSOP = CompSOP = MinSOP Step 2: Determination of all prime implicants of c o m ν -cube A -cube A m 3 a b c i b ci p m 5 a b c i a ci p 2 m 6 a b c i a b p3 m 7 a b c i CompSOP of c o : c o = b c i + a c i + a b table of prime implicants Step 3: Determination of the MinSOP of c o Covering condition: C = (m 3 p ) (m 5 p 2 ) (m 6 p 3 ) (m 7 p + m 7 p 2 + m 7 p 3 ) C = τ τ 2 τ 3 (τ + τ 2 + τ 3 ) = τ τ 2 τ 3 p, p 2, p 3 are essential prime implicants. The MinSOP of c o is: c o = b c i + a c i + a b = p + p 2 + p 3 c o = a b + (a + b) c i Obviousl holds: c o = a b + (a + b) c i = a b + (a b) c i Logic Snthesis: Solution 2 (4) 9

22 a b c i p 3 p p 2 a b c i m 7 m m 2 m 4 c o = p + p 2 + p 3 s = m + m 2 + m 4 + m 7 c) Block diagram of a 2 bit adder: a b a b c o, = c i, = a b c o, c o, c i, FA c o, HA s = a b s = a b a b s s c o, = a b + (a + b ) a b Truth table of a 2 bit adder: ĉ o, ŝ ŝ = â â plus ˆb ˆb a a b b c o, s s a a b b c o, s s Version 2 Version Logic Snthesis: Solution 2 (5) 2

23 d) p a a b b p 3 p 2 Cube graph (n = 4) for c o, c o, = p + p 2 + p 3 c o, = b a b + a a b + a b c o, = a b + (a + b ) a b a a b b p 2 p Cube graph (n = 4) for s s = p + p 2 s = a b + a b s = a b Logic Snthesis: Solution 2 (6) 2

24 a a b b m 5 m 5 p 4 p p 2 p 3 Cube graph (n = 4) for s s = m 5 + m 5 + p + p 2 + p 3 + p 4 s = a a b b + a a b b + a a b + a b b + a a b + a b b s = a b (a b + a b + (a + b ) (a b + a b ) s = a b (a b ) + a b (a b ) s = a b a b Problem 3, Solution a) Truth table of f : a a b b w ŵ = â â > ˆb ˆb b) CSOP of f : w = a a b b + a a b b + a a b b + a a b b + a a b b + a a b b Logic Snthesis: Solution 2 (7) 22

25 c) Table of prime implicants: m ν -Cube A -Cube A 2-Cube A m 4 a a b b a b b p m 8 a a b b a a b a b p 3 a b b m 9 a a b b m 2 a a b b a b b a a b m 3 a a b b a a b p 2 m 4 a a b b CompSOP: f = p + p 2 + p 3 = a b b + a a b + a b f = a b + (a b ) a b Minterm covering: C = (m 4 p ) (m 8 p 3 ) (m 9 p 3 ) (m 2 p + m 2 p 2 + m 2 p 3 ) (m 3 p 3 ) (m 4 p 2 ) C = τ τ 3 τ 3 (τ + τ 2 + τ 3 ) τ 3 τ 2 = τ τ 2 τ 3 = MinSOP: f = p + p 2 + p 3 (MinSOP equals CompSOP) d) Cube graph (n = 4): a a b b p 3 p 2 p a a b b f = p + p 2 + p 3 p = a b b p 2 = a a b p 3 = a b Logic Snthesis: Solution 2 (8) 23

26 e) Gate level realization: Implementation w = a b b + a a b + a b Implementation 2 a a b b w = a b + (a + b ) a b a b w a b w 2 levels 3 levels Logic Snthesis: Solution 2 (9) 24

27 Tutorial 3: Snthesis of Combinatorial Circuits b Methods of Design Automation Problem : Resolution Method Consider the SOP forms of the four Boolean functions f, f 2, f 3 : B 4 B and f 4 : B 3 B. f = z w + z w + w + z w + z w f 2 = z w + z + z w + z w + z f 3 = z w + z w + w + z + z w f 4 = + z + + z a) Determine the on-sets of the Boolean functions using the simplified notation c i {,, } 4 or c i {,, } 3. b) Determine the CompSOP (all prime implicants) directl from the given SOP forms. Emplo the resolution method in the form of the laer algorithm. c) Visualize the determination of the CompSOP from the SOP for each of the four Boolean functions using cube graphs. Use separate graphs for SOP and CompSOP for each function. d) Determine the MinSOP for all four functions b inspection. Logic Snthesis: Problems for Tutorial 3 () 25

28 Problem 2: Combinatorial Optimization (Heuristic Minimization, Suboptimal Solutions!) Consider the CompSOP forms (prime covers, prime closures) of the following Boolean functions: f : B 4 B, f = p + p 2 + p 3 + p 4 + p 5 p = z, p 2 = z w, p 3 = z w p 4 = z, p 5 = w f 2 : B 4 B, f 2 = p + p 2 + p 3 + p 4 + p 5 p = z, p 2 = z, p 3 = z w p 4 = z w, p 5 = w f 3 : B 4 B, f 3 = p + p 2 + p 3 p = w, p 2 = z w, p 3 = z f 4 : B 3 B, f 4 = p + p 2 + p 3 + p 4 + p 5 + p 6 p =, p 2 = z, p 3 = z p 4 =, p 5 = z, p 6 = z a) Determine the MinSOP forms (mincov( f ) pcov( f )) from the given CompSOP forms of the Boolean functions f, f 2 and f 4. Use a local search and check the possibilities for removing redundant prime implicants b tautolog checks. pcov( f ) \ {p i } = cov(h i ) ; f = p i + h i p i can be removed, IF: p i h i or (h i ) pi =. Draw a configuration graph for the situation of the local search. Use the results of problem in case ou don t want to perform all inclusion checks. b) Check which prime implicant can be removed from the CompSOP form of f 3. c) Draw the gate level realizations for the MinSOP forms of the functions f 2, f 3 and f 4. Logic Snthesis: Problems for Tutorial 3 (2) 26

29 Problem 3: Combinational Optimization (Heuristic Minimization, Method in General not Eact!) Consider the SOP form f 5 : B 3 B f 5 = + z + z The task is to find the smallest possible cover of f 5 b local optimization using methods of cube removal and cube epansion (single literal removal). Feasibilit check removal of a cube removal of a single literal f = c + h = h, f = c + h = c l + h, IF c h IF c l f or c l l h Problem 4: CompSOP form from POS form Consider the SOP forms of the Boolean functions f 3 : B 4 B and f 4 : B 3 B. f 3 = z w + z w + w + z + z w (see problem ) f 4 = + z + + z (see problem ) a) Draw the ROBDD( f 4 ) with the following oder of variables: z. b) Draw the ROBDD( f 4 ) with no further computation. c) Read off a valid SOP form for f 4 from the ROBDD( f 4 ) and from that determine a valid POS form for f 4. Then, determine the CompSOP form of f 4 from the POS form of f 4. d) Consider the SOP form of f 3 and determine the cofactors ( f 3 ) and ( f 3 ). Which propert of f 3 becomes apparent from the cofactors? Is this propert also apparent from the CompSOP form of f 3? See also problem. e) Draw the ROBDD( f 3 ) and the ROBDD( f 3 ) with the order of variables z w. Take into account the results of d). f) Read off a valid SOP form for f 3 from the ROBDD( f 3 ) and from that determine a valid POS form for f 3. Then, determine the CompSOP form of f 3 from the POS form of f 3. Logic Snthesis: Problems for Tutorial 3 (3) 27

30 Solution of Tutorial 3: Problem, Solution a) On-sets: f = {,,,, } f 2 = {,,,, } f 3 = {,,,, } f 4 = {,,, } b) SOP : f Laer z w + z w + w + z w + z w + z + z w + w + z + z + w 2 CompSOP: f = z + z w + z w + z + w f = p + p 2 + p 3 + p 4 + p 5 see Tutorial 2, Problem! SOP : f 2 Laer z w + z + z w + z w + z + z + z w + w + z w + z 2 CompSOP: f 2 = z + z + z w + z w + w f 2 = p + p 2 + p 3 + p 4 + p 5 SOP : f 3 Laer z w + z w + w + z + z w + w + z w + z w + z + z w + w + z w + z 2 CompSOP: f 3 = w + z w + z f 3 = p + p 2 + p 3 Logic snthesis: Solution 3 () 28

31 SOP : f 4 Laer + z + + z + z + z CompSOP: f 4 = + z + z + + z + z f 4 = p + p 2 + p 3 + p 4 + p 5 + p 6 c) zw zw SOP: f zw w zw zw zw zw CompSOP: f p 3 p 4 (MinSOP: f = p 2 + p 4 + p 5 ) p 5 p p 2 zw Logic snthesis: Solution 3 (2) 29

32 zw zw z SOP: f 2 zw zw z zw zw p f 2 CompSOP: (MinSOP: f 2 = p + p 2 + p 4 ) p 5 p 4 p 2 p 3 zw Logic snthesis: Solution 3 (3) 3

33 zw SOP: f 3 zw zw w z zw zw zw f 3 CompSOP: (MinSOP: f 3 = p + p 3 ) p p 3 p 2 zw Logic snthesis: Solution 3 (4) 3

34 SOP: f 4 CompSOP: f 4 z z z p 6 p p 5 p 2 (MinSOP: f 4 = p + p 3 + p 5 or p 2 + p 4 + p 6 ) z p 4 p 3 z z d) MinSOP: f = p 2 + p 4 + p 5 f 2 = p + p 2 + p 4 f 3 = p + p 3 f 4 = p + p 3 + p 5 or f 4 = p 2 + p 4 + p 6 Problem 2, Solution a) Local search in pcov( f ) pcov( f ) = {p, p 2, p 3, p 4, p 5 } {,2,3,4,5} For eample: (h ) p = (p 2 + p 3 + p 4 + p 5 ) z = h (,,,w) (h ) p = w + w = (h 3 ) p3 = + = (h,3 ) p3 = + = (h,3 ) = p 2 + p 4 + p 5 } {{ } The prime implicants p and p 3 can be removed together from the prime cover. (h 2 ) p2 = (h 4 ) p4 = w (h 5 ) p5 = z + z } {{ } p 2, p 4 and p 5 are essential prime implicants Result: mincov( f ) = {p 2, p 4, p 5 } Logic snthesis: Solution 3 (5) 32

35 Configuration graph for a local search in pcov( f ): {2,3,4,5} {,2,3,4,5} 5 p {,2,4,5} {,2,3,4} is not a feasible solution (no cover of f ). p 5 is essential (as well as p 2 and p 4 ). 3 {2,4,5} = mincov( f ) Number of checks needed: 6 Local search in pcov( f 2 ) pcov( f 2 ) = {p, p 2, p 3, p 4, p 5 } {,2,3,4,5} (h 3 ) p3 = + = (h ) p = w (essential) (h 4 ) p4 = + = (h 2 ) p2 = w (essential) (h 5 ) p5 = z + z = (h 4,5 ) p5 = z (h 3,5 ) p5 = z + z = (h 3,4 ) p4 = Result: mincov( f 2 ) = {p, p 2, p 4 } Configuration graph for a local search in pcov( f 2 ): {,2,3,4,5} {,2,4,5} 5 4 {,2,4} = mincov( f 2 ) 5 {,2,3,5} {,2,3,4} 3 Number of checks needed: 8 Logic snthesis: Solution 3 (6) 33

36 Local search in pcov( f 4 ) pcov( f 4 ) = {p, p 2, p 3, p 4, p 5, p 6 } {,2,3,4,5,6} (h i ) pi = for all i =,2,3,4,5,6 Hence the further search is performed in the sens of a depth-first search where onl one alternative is considered; in this case cov( f 4 ) = h 2 = {,3,4,5,6}. (h 2 ) p2 = + = (h 2,4 ) p4 = z + z = (h 2,5 ) p5 = + = (h 2,6 ) p6 = + = (h 2,4,6 ) p6 = + = (h 2, ) p = z (h 2,3 ) p3 = (h 2,4,5 ) p5 = (h 2,5,6 ) p6 = Result: mincov( f 4 ) = {p, p 3, p 5 } Configuration graph for a local search in pcov( f 4 ): 3 {,3,5,6} 5 {,2,3,4,5,6} {2,3,4,5,6} 2 {,3,4,5,6} This alternative and other alternatives with 5 prime implicants are 5 not considered further. 4 6 {,3,4,6} 6 {,3,4,5} {,3,5} = mincov( f 4 ) b) CompSOP: f 3 = w + z w + z = p + p 2 + p 3 Solution approach : w + }{{} z w + z = w + z ; z w = p 2 can be removed from the CompSOP. resolvent MinSOP: f 3 = w + z = p + p 3 Solution approach 2: (z w + z) w = z w z w + z ( w + z) z w = + = z w w + z ( w + z w) z = w z w + z w p 2 = z w can be removed from the CompSOP. Logic snthesis: Solution 3 (7) 34

37 c) z w v= f 2 (,,z,w) v= f 3 (,,z,w) w v z v MinSOP: f 2 = z + z + z w MinSOP: f 3 = w + z z w = f 4 (,,z) z w = f 4 (,,z) w w MinSOP: f 4 = + z + z Version MinSOP: f 4 = z + + z Version 2 Problem 3, Solution f 5 = + z + z A) Removal of a literal: f 5 = + z + z, IF z ( + z + z) i.e. ( + z + z) z = + = or IF z ( + z) i.e. ( + z) z = f 5 + z + z, because ( + z) z = f 5 = + z + z, IF ( + z) z =, z and z are prime implicants, because no other literal can be removed. E.g. ( + z) z = B) Removal of a cube: See eample (3) in the lecture notes! f 5 = z + z, IF ( z + z) = z + z = Logic snthesis: Solution 3 (8) 35

38 Problem 4, Solution a) f 4 + z + + z b) f 4 f = + z f = + z f = z z z f = z z z ROBDD( f 4 ), z ROBDD( f 4 ), z c) f 4 = z + z Consider all paths in ROBDD( f 4 ) from to! f 4 = ( + + z) ( + + z) POS form for f 4 from SOP form for f 4 CompSOP: f 4 = + z + + z + z + z d) ( f 3 ) = ( f 3 ) = resolvents z w + z w + z w + w + z = z w + w + z z w + w + z + z w + z w = z w + w + z Resolution: ( f 3 ) = ( f 3 ), i.e. f 3 = ( f 3 ) Conclusion: f 3 is independent of e) f 3 ( f 3 ) ( f 3 ) ( f 3 ) z w ( f 3 ) z w ( f 3 ) ROBDD( f 3 ) ROBDD( f 3 ) f) f 3 = z + w, f 3 = ( + z) ( + w) CompSOP: f 3 = w + z + z w Logic snthesis: Solution 3 (9) 36

39 Tutorial 4: Binar Decision Diagrams, Tautolog Proof Problem : ROBDD Consider the Boolean functions f : B 4 B, f 2 : B 3 B, and f 3 : B 3 B. f = w + z w f 2 = ( + ) z + ( + ) z f 3 = z Note: =, = a) Draw the ROBDD( f ) for the Boolean function f using the following order of variables: z w. b) Draw the ROBDD( f ) for the Boolean function f using the following order of variables: w z. c) From the ROBDD representations of a) and b) determine the corresponding SOP forms. Therefore all paths from the root verte to the leaf verte have to be considered. Perform the resolvent method to show that both SOP forms correspond to the given Min- SOP form f = w + z w. d) Draw the ROBDD( f 2 ) and the ROBDD( f 3 ) considering the order of variables z. Which conclusion for f 2 and f 3 could be drawn from the representation of the ROBDDs? Logic Snthesis: Problems for Tutorial 4 () 37

40 Problem 2: ROBDD, Multipleer Consider the multipleer circuit MUXS with four data inputs and one data output consisting of three sub-circuits MUX, MUX2 and MUX3. z MUX3 w v MUX MUX2 a b c d selector inputs data inputs Multipleer Circuit MUXS Switching functions: MUX3: z = β(,w,v) MUXS: z = f (,,a,b,c,d) z = β(, β(,a,b), β(,c,d)) MUX: w = β(,a,b), MUX2: v = β(,c,d) Note regarding the equation of the multipleer, e.g. for MUX β(,a,b) = a + b β(,a,b) = a, β(,a,b) = b a) Compute the SOP form of the switching function of MUXS emploing the Shannon epansion z = f (,,a,b,c,d) = ( + ) ( + ) f = f + f + f + f b) Draw a ROBDD( f ) for the switching function f (,,a,b,c,d) of MUXS using the order of variables a b c d. c) Draw a ROBDD( f ) for the switching function f (,,a,b,c,d) of MUXS using the order of variables a b c d. d) From the ROBDD representations of b) and c) determine the corresponding SOP forms. Use the resolution rule to show that both SOP forms describe the same Boolean function. e) Draw the gate level implementation for the multipleer circuit MUXS as a 2-level and a 4-level realization. For the 4-level realization onl gates with two inputs are permitted. Draw implementations of both circuits consisting of onl NAND gates. Logic Snthesis: Problems for Tutorial 4 (2) 38

41 Problem 3: Tautolog Proof, Shared ROBDD Consider the two Boolean functions f : B 4 B and f 2 : B 5 B f = + + z w + z w + z w + z w + z w + z w f 2 = z v + w v + z w + z w z + z + z + z Consider further a so called Shared ROBDD where compleit is reduced as two (or more) functions h and h 2 share parts of the diagram. h h 2 w z h : B 4 B, h 2 : B 3 B, v = h (,,z,w) u = h 2 (,z,w) Shared ROBDD(h,h 2 ) a) Emplo the resolution method to show that f is a tautolog. b) Construct the ROBDD( f ) with the ordering z w. Therefore compute those cofactors of f which are needed for the construction of ROBDD( f ). c) Visualize the SOP form of f with a cube graph. d) In order to identif if the function f 2 and its cofactors are unate w.r.t. one or more variables an analsis of its structure is required. Perform such an analsis with regard to a proof of tautolog for f 2. e) Use the results of d) to prove the tautolog for f 2 with the resolvent method and with a ROBDD. f) Read off the SOP forms of h and h 2 from the shared ROBDD(h,h 2 ) and transform them into MinSOP forms. g) From the MinSOP form of the pair of functions h = (h,h 2 ) draw a circuit with the output variables v and u onl consisting of gates with two inputs. Logic Snthesis: Problems for Tutorial 4 (3) 39

42 Problem 4: Functional Decomposition Consider the following MinSOP form: f = f should be realized with as few 4-LUTS (look-up tables) as possible. (With a 4-LUT an arbitrar combinational Boolean function with 4 variables can be realized) a) Construct a ROBDD for each of the orderings and b) Which of the variables would ou choose as bound variables and which as free variables? c) Consider and 3 as free variables. Determine the decomposition function h( 2, 4, 5 ). Assign as few output values of h as possible. d) Determine the composition function g(h( 2, 4, 5 ),, 3 ). α) Without using don t-cares. β) With using don t-cares for simplifing g. Problem 5: Snthesis of Sequential Circuits Consider the state transition graph: / / / S / / / / / / / S S 2 / / / / S 3 S 4 S 5 S 6 a) Determine the state output table. b) Minimize the number of states. c) Draw the minimized state transition graph. Determine the minimized state output table. d) Determine a coding of the states and compute the state transition function and the output function. e) Draw the circuit implementation of the automaton. Logic Snthesis: Problems for Tutorial 4 (4) 4

43 Problem 6: Snthesis of circuits with multiple outputs Given are the following si functions: f = z + z ; g = w + z + z w ; h = w + z + z w ; f 2 = z + z g 2 = z w + w + z h 2 = z w + w + z The functions f and f 2, g and g 2, and h and h 2 should be realized as one circuit with two outputs, respectivel. a) Determine the multiple implicants f f 2, g g 2 and h h 2. b) Determine the CompSOPs for all functions. c) Find the optimal covering of the functions b using the multiple implicants. d) For which cases is it sensible to use the multiple implicants? Visualize the computation in the cube graph. Draw the resulting multiple output functions. Logic Snthesis: Problems for Tutorial 4 (5) 4

44 Solution of Tutorial 4: Problem, Solution a) ROBDD( f ) for z w ( f ) = w + z w, ( f ) = z w; ( f ) = z w; ( f ) = w + z w = w; ( f ) z = w; w + z w = = w + z w 2 = = z w 3 z w= w z= z= 4 w w= Shannon epansion ROBDD( f ) 4 vertices (without terminal vertices) b) ROBDD( f ) for w z ( f ) = w + z w w w z + z w = f z w = ( f ) ( f ) w = + z ( f ) w = z z z = ( f ) w = ( f ) w ROBDD( f ) 5 vertices (without terminal vertices) Logic snthesis: Solution 4 () 42

45 c) ROBDD( f ) with z w SOP: f = w + z w + z w + z w }{{} +... MinSOP: f = w + z w resolvent ROBDD( f ) with w z SOP: f = w + w z + w z + w z }{{} +... MinSOP: f = w + w z resolvent d) ( f 2 ) = z + z, ( f 2 ) = z, ( f 2 ) = z ( f 2 ) = z + z, ( f 2 ) = z, ( f 2 ) = z ( f 3 ) = z, ( f 3 ) = z, ( f 3 ) = z ( f 3 ) = z, ( f 3 ) = z, ( f 3 ) = z }{{} ROBDD( f 2 ) ROBDD( f 3 ) f 2 f 3 f f f = f z z f = f ROBDD( f 2 ) ROBDD( f 3 ) f 2 = f 3 Logic snthesis: Solution 4 (2) 43

46 Problem 2, Solution a) f = β(, β(,a,b), β(,c,d)) = β(,a,b) f = β(, β(,a,b), β(,c,d)) = β(,c,d) f = a, f = b, f = c, f = d SOP: z = f (,,a,b,c,d) = a + b + c + d b) ROBDD( f ) with a b c d f (,,a,b,c,d) f = β(,a,b) β(,c,d) = f f = a a f = b b c c = f d d = f ROBDD( f ) 7 vertices (without terminal vertices) Logic snthesis: Solution 4 (3) 44

47 c) ROBDD( f ) with a b c d f = β(, β(,a,b), β(,c,d)) f a = β(, β(,,b), β(,c,d)), f a = β(, β(,,b), β(,c,d)) f ab = β(,, β(,c,d)), f ab = β(,, β(,c,d)) f ab = β(,, β(,c,d)), f ab = β(,, β(,c,d)) f ab =, f ab =, f ab =, f ab = f ab = f ab = f ab = f ab = β(,c,d) = g(,c,d) g = c, g = d a f (a,b,,,c,d) f a b b f a f ab f ab f ab = β(,c,d) = g(,c,d) c d g = c g = d ROBDD( f ) 2 vertices (without terminal vertices) d) SOP form from ROBDD( f ) with a b c d SOP: f = a + b + c + d SOP form from ROBDD( f ) with a b c d SOP: f = a b + a b + a b + (a b + a b + a b + a b ) ( c + d) = a + b + } a {{ b } + (a + a) (b + b) ( c + d) resolvent f = a + b + c + d Logic snthesis: Solution 4 (4) 45

48 e) z = a + b + c + d z = ( a + b) + ( c + d) a a b z b z c c d d a a b z b z c c d d Problem 3, Solution a) Resolution method: SOP: f Laer + + z w + z w + z w + z w + z w + z w + z w + z w + z w + z w + z + w + w + z + z + w + w + z In the sense of a depth-first search not all resolvents were generated. Logic snthesis: Solution 4 (5) 46

49 b) Cofactors of f : ( f ) = + z w + z w + z w + z w ( f ) = + z w + z w + z w + z w ( f ) =, ( f ) = z w + z w + z w + z w ( f ) =, ( f ) = z w + z w + z w + z w ( f ) = ( f ) = ( f ) z = w + w, ( f ) z = w + w, i.e. f (,,z,w) = OBDD( f ) with z w: f ( f ) ( f ) z ( f ) = ( f ) = w w ( f ) z = ( f ) z = w + w = c) Cube graph for f (,,z,w): zw zw zw zw f is a tautolog Logic snthesis: Solution 4 (6) 47

50 d) Structure analsis to find out if f 2 is unate: f 2 (,,z,w,v) = v ϕ(,,z,w) + w ψ(,,z) + g(,,z) ϕ(,,z,w) = z + w, ψ(,,z) = z + z, g(,,z) = + + z + z + z + z The variable v appears onl in positive form in f 2 ; that means: ( f 2 ) v = ϕ + w ψ + g ( f 2 ) v = w ψ + g ( f 2 ) v ( f 2 ) v ( f 2 ) v = ( f 2 ) v + ( f 2 ) v f 2 is positive unate in v Result : From ( f 2 ) v = ( f 2 ) v = = f 2 = ( f 2 ) vw = ψ + g and ( f 2 ) v = = ( f 2 ) v = results ( f 2 ) v = = f 2 =. For the proof of the tautolog f 2 = it is sufficient to prove the tautolog ( f 2 ) v =. The variable w appears onl in negative form in ( f 2 ) v ; that means: ( f 2 ) vw = g ( f 2 ) vw ( f 2 ) vw ( f 2 ) vw = ( f 2 ) vw + ( f 2 ) vw ( f 2 ) v is negative unate in w Result 2: From ( f 2 ) vw = ( f 2 ) vw = = ( f 2 ) v = and ( f 2 ) vw = = ( f 2 ) vw = results ( f 2 ) vw = = ( f 2 ) v =. For the proof of the tautolog ( f 2 ) v = it is sufficient to prove the tautolog ( f 2 ) vw =. Result and 2: From ( f 2 ) vw = ( f 2 ) v = = f 2 = and ( f 2 ) vw = = ( f 2 ) v = results ( f 2 ) vw = = f 2 =. For the proof of the tautolog f 2 = it is sufficient to prove the tautolog ( f 2 ) vw =, i.e. it is sufficient to prove g(,,z) =. The variables, and z appear in g(,,z) in positive and negative form; that means it is harder to determine if g(,,z) is unate in one of these variables. Logic snthesis: Solution 4 (7) 48

51 e) Proof of tautolog for f 2 : The structure analsis to find out if f 2 is unate has low compleit and shows that it is sufficient to prove g(,,z) = in order prove the tautolog of f 2. OBDD(g) with z Resolution method: g SOP: g Laer + + z + z + z + z z + z + z + z f f z f f = z + z f) resolvents SOP of h : v = w + z w + z w + z w +... MinSOP : v = w + z w resolvents SOP of h 2 : u = w + z w + z w MinSOP : u = w + z w g) Circuit from the Shared ROBDD(h, h 2 ): z w u = w + z w v = w + z w Logic snthesis: Solution 4 (8) 49

52 Problem 4, Solution a) bound free b) free variables: left: -, right: {, 3 } (all others 4-LUT to small) c) Assignment (from ROBBD):,,,,, z = = = z 2 = = d) Composition function α) w = z z 2 + z z 2 ( + 3 ) + z z 2 ( + 3 ) = z z 2 + z z 2 + z z z z 2 + z z z 2 + z = = z z z z z 2 + z β) w = z z z z z 2 + z Addition of an terms with z z 2 : = z z z z z 2 + z + z z z z 2 = z z z z z 2 + z + z z 2 + z z z z 2 + = z z z Logic snthesis: Solution 4 (9) 5

53 Problem 5, Solution a) State output table: µ = = S S / S 2 / S S 3 / S 4 / S 2 S 5 / S 6 / S 3 S / S / S 4 S / S / S 5 S / S / S 6 S / S / b) Minimization of states -equivalence µ = = S S / A S 2 / A S S 3 / A S 4 / B S 2 S 5 / A S 6 / B A S 3 S / A S / A S 5 S / A S / A S 4 S / A S / A S 6 S / A S / A B 2-equivalence µ = = S S / B S 2 / B S 3 S / A S / A A S 5 S / A S / A S S 3 / A S 4 / C S 2 S 5 / A S 6 / C B S 4 S / A S / A S 6 S / A S / A C 3-equivalence µ = = S S / S 2 / A S 3 S / S / S 5 S / S / B S S 3 / S 4 / S 2 S 5 / S 6 / C S 4 S / S / S 6 S / S / D Equivalence: S 3 S 5, S S 2, S 4 S 6 Minimized table: Minimized automaton: µ = = S S / S / S 3 S / S / S S 3 / S 4 / S 4 S / S / / / / S S / / / / / S 3 S 4 Logic snthesis: Solution 4 () 5

54 c) State coding: S s s 2 S s s 2 S 3 s s 2 S 4 s s 2 d) state net state S S S S S S 3 S S 4 S 3 S S 3 S S 4 S S 4 S s s 2 z z 2 = s s 2 z = s s 2 + s s 2 = s s 2 ; z 2 = s s 2 + s s 2 + s s 2 = s s 2 + s e) s Q D z s 2 Q D z 2 clock Logic snthesis: Solution 4 () 52

55 Problem 6, Solution a) multiple implicants MI f f 2 = ( z + z) ( z + z) = z g g 2 = ( w + z + z w) ( z w + w + z) = z w h h 2 = ( w+ z+ z w) ( z w+ w+ z) = z w+ z w = z b) f, f 2, g and g 2 are alread CompSOP forms. h laer w + z + z w + z + z w + w h 2 laer z w + w + z + z + w + z w c) f : z z MI z f = z + z + z f 2 : z z MI z f 2 = z + z g : g 2 : w z z w MI z w g = z w + w + z w z w w z MI z w g 2 = z w + z w + z Logic snthesis: Solution 4 (2) 53

56 h : *) w z 2 z w z z w 2 w 2 MI z When using heuristics, several solutions eist: chosen: z and MI: h = z + z + z w + z w chosen: z w and MI: h = z + z w + w (better) h 2 : *) z w w z 2 z w 2 z w 2 MI z When using heuristics, several solutions eist: chosen: z and MI: h 2 = z + z + z w + w chosen: w and MI: h 2 = z + w + z w (better) *) Number of covered minterms after choosing MI. d) f, f 2 : f = z + z+ z f 2 = z+ z z Two separate functions: = literals; Multiple output: = literals. Appling multiple implicant not useful. z z MI: z Logic snthesis: Solution 4 (3) 54

57 g,g 2 : g = w + z w+ z w g 2 = z w + z+ z w Two separate functions: = 6 literals; Multiple output: = 5 literals. Appling multiple implicant useful. g : w z g 2 : w z w MI: z w z w z Logic snthesis: Solution 4 (4) 55

58 h,h 2 : h = z w + w+ z h 2 = w + z w+ z Two separate functions: = 8 literals; Multiple output: = 5 literals. Appling multiple implicant useful. h : z z w w h 2 : MI: z w z z w Logic snthesis: Solution 4 (5) 56

59 circuits: z f z w g z w h f 2 g 2 h 2 Logic snthesis: Solution 4 (6) 57

60 II. Simulation Tutorial 5: Simulation of Digital Circuits Problem Consider the schematic of a simple SR-latch (RS-Flip-Flop in german): R Nand_a Q n S Nand_b Q a) Based on Boolean logic, devise a look-up table which describes the logic function of the circuit. Which condition is necessar for correct function of the latch? b) Develop a simulation model of the circuit using gate and wire delas. c) Determine the circuit function Q t = f(q t,r t,s t ). For wire delas use τ w =, for gate Nand a use τ d = and for gate Nand b use τ d = (basic time units). d) Carr out the simulation steps for a single input event. For wire delas use τ w =, for gate Nand a use τ d = and for gate Nand b use τ d = 2 (basic time units). Initial state: R =, S =, Q = Input event: E E = ( S,,, ) e) Devise a look-up table for a simple NAND-gate based on three-valued logic (,, X ). Simulation: Problems for Tutorial 5 () 58

61 Problem 2 D-latch: single data input, staticall triggered. D D n R Nand_a Q n C S Nand_b Q For all gates use: τ =. a) Describe the effects of the additional gates for the functionalit of the flip-flop. b) Assume an initial state Q = and Q n =. Carr out the simulation for the given input waveforms: t D C D n R S Q n Q Simulation: Problems for Tutorial 5 (2) 59

62 Problem 3 RS flip-flop: edge triggered. Clocked latches transfer input values to the outputs while the clock signal is asserted to or. In contrast, the output of flip-flops can onl change, when a clock edge occurs. R I I 3 Nand_a N N3 Q n C S N2 I 2 N4 I 4 Nand_b Q input preparation main latch The flip-flop above consists of two parts. Gates Nand a and Nand b build a normal latch (compare with eercise ). Gates N to N4 prepare the input signals and suppl the main latch with signals I 3 and I 4. Simulating the loading of the flip-flop once with and then with leads to the following waveforms: t R S C I I 2 I 3 I 4 Q Q n Simulation: Problems for Tutorial 5 (3) 6

63 Assume infinitesimal small gate delas for questions a) to c). a) Wh is I 3 = I 4 = impossible? b) What are the values of I 3 and I 4 for C =? c) What is the influence of C = on the main latch Nand a/nand b? (Hint: Compare with latch of eercise ) d) Wh does the positive edge of S at t = 5 (or R at t = 5) have no influence on Q and Q n, although the value of C is still? Show the feedback loops, which are responsible for this effect. e) What has to happen, before the net data value can be taken over from the inputs S and R to the outputs Q and Q n? Edge triggered circuits often require, that input signals have to be stable before and after a clock edge for a certain time span in order to get a defined value at the output signals. These times are called setup time (t sup ) and hold time (t hld ). When all gate delas in the circuit of this eercise are τ d =, two conditions eist for the signals R and S (under the assumption R + S = ): t s > t sup = t h > t hld = t t s t h R / S C t sup t hld f) Which signal path is responsible for the setup time limit (t sup = ) of this flip-flop? g) Which signal path is responsible for the hold time limit (t hld = ) of this flip-flop? Simulation: Problems for Tutorial 5 (4) 6

64 Solution of Tutorial 5: Problem, Solution a) R S Q Q n previous state not allowed, because R = S = followed b R = S = would lead to an unknown state condition: R + S = b) R τ w Nand_a τ da τ w3 Q n τ w5 τ w6 S τ w2 Nand_b τ db τ w4 Q c) Q t = S t Q t n Q t n = R t Q t together: Q t = S t R t Q t = S t + R t Q t d) evaluated new events t R S Q n Q components (signal,val,t gen,t ee ) initial state (S,,, ) Nand b (Q,,, 3) 3 Nand a (Q n,, 3, 4) 4 Nand b Simulation: Solution 5 () 62

65 t R S Q n Q e) NAND X X X X X Problem 2, Solution a) condition R + S = is enforced C = R = S = previous state C = ; D = S = Q = C = ; D = R = Q = circuit function: Q follows D when C = else Q keeps previous value. b) t D C D n R S Q n Q Simulation: Solution 5 (2) 63

66 Problem 3, Solution a) Gates N3 and N4 build a secondar latch. I 3 = would automaticall lead to I 4 = and vice versa, because: I 4 = I 3 C I 2 = C I 2 = = and I 3 = I 4 C I = C I = = (proof b contradiction) I 3 and I 4 cannot be simultaneousl. The condition of eercise.a) is alwas fulfilled for Nand a/nand b. b) I 3 = I 4 C I = I 4 I = = and I 4 = I 3 C I 2 = I 3 I 2 = = I 3 = I 4 = c) C = leads to I 3 = I 4 =. This means, that the main latch Nand a/nand b keeps its value. d) At t = 5, I 4 is alread and blocks an change of S b the feedback loop to N2. Further, changes of R cannot propagate to I 3, because I 4 is connected to N3, too. At t = 5 and I 3 = the situation is smmetrical. e) Clock C has to return to the value in order to open the blocking mentioned in eercise d). I 3 and I 4 will then return to the value. The main latch Nand a/nand b will keep its value at least until a change of I 3 or I 4 occurs. This is onl possible on the net positive edge of clock line C. It will cause the propagation of the values of I and I 2 to I 3 and I 4 and the blocking mechanism will be activated again. f) Before a positive clock edge, signal changes of R or S have to propagate through N or N2 to I and I 2, respectivel, in order to appear in time at the inputs of gates N3 or N4. These paths include one gate each and thus the setup time is in both cases. g) After a rising edge on clock line C, the blocking mechanism described in eercise d) must become active, before a change of R or S ma be allowed. It takes one gate dela after a rising edge on clock input until I 3 = or I 4 =, which blocks the corresponding input. Therefore R and S must be stable for at least basic time units after the rising edge on C. Simulation: Solution 5 (3) 64

67 Tutorial 6: VHDL Problem : RS-Flip-Flop in NOR-Logic a) Determine an interface description in VHDL (ENTITY) for the RS flip-flop displaed at the right. Inputs and outputs are of tpe bit. S Nor_a Q n b) Determine an implementation of the RS flip-flop b a behavioral description. Use the NOR-operator to link the input signals. Note that signals of direction out in the interface description R Q ma not be omitted in the according ARCHITECTURE. Nor_b c) Determine an implementation of the RS flip-flop b a structural description. Assume that the component Nor2 alread has an ARCHITECTURE in the WORK librar and is made available under the name fast arch. d) Create a testbench with an ENTITY and an ARCHITECTURE. Create a CONFIGURATION for the behavioral description and the structural description respectivel. e) Consider the two following processes: Nor_a: PROCESS (S, Q) BEGIN Qn <= S NOR Q; END PROCESS; Nor_b: PROCESS (R, Qn) BEGIN Q <= R NOR Qn; END PROCESS; The variables R and S are stimulated as displaed below. Let the initial state be Q= and Q n =. Complete the time diagram. Determine the delta ccles performed b the simulator. t S R Q Q n Simulation: Problems for Tutorial 6 () 65

68 Problem 2 Consider the following implementation of a dela element: PROCESS(I) BEGIN Ot <= transport I after tpd; Oi <= I after tpd; END PROCESS; I τ pd O t O i The dela element is stimulated b the following input signal: t I a) Show the computation of the output signals. For this purpose determine the entries in the signal drivers for all relevant times. Let τ pd be 3 time units. b) Draw the signals O t and O i : t O t O i Problem 3 Consider the two processes below. Show how each transaction is scheduled in the driver. What effect has the insertion of a new transaction on alread eisting transactions? (The initial state for St and Si is ). P: PROCESS BEGIN St <= transport after ns; St <= transport 2 after 2 ns; St <= transport 3 after 3 ns; St <= transport 4 after 5 ns;... END PROCESS; P2: PROCESS BEGIN Si <= after ns, 2 after 2 ns, 3 after 3 ns, 4 after 4 ns; Si <= 5 after 5 ns, 6 after 6 ns; Si <= 6 after 7 ns; Si <= 6 after 55 ns;... END PROCESS; Simulation: Problems for Tutorial 6 (2) 66

69 Solution of Tutorial 6: Problem, Solution a) ENTITY rsff IS PORT( R, S : in bit; Qn, Q : out bit ); END rsff; b) Inside the architecture the signals Qn and Q can onl be written but not read out, as the were declared as out in the entit. But the are needed inside the architecture as inputs for the NOR gates and thus the intermediate signals Qn tmp and Q tmp are introduced. Note: If the signals Qn and Q had been declared as buffer in the entit, the could be read out. ARCHITECTURE dataflow OF rsff IS SIGNAL Q_tmp, Qn_tmp: bit; BEGIN PROCESS (R, S, Q_tmp, Qn_tmp) BEGIN Q_tmp <= R NOR Qn_tmp; Qn_tmp <= S NOR Q_tmp; Q <= Q_tmp; Qn <= Qn_tmp; END PROCESS; END dataflow; c) ARCHITECTURE structure OF rsff IS COMPONENT Nor2 PORT (i, i2: in bit; o: out bit); END COMPONENT; SIGNAL Q_tmp, Qn_tmp: bit := ; BEGIN Nor_a: Nor2 PORT MAP(S, Q_tmp, Qn_tmp); Nor_b: Nor2 PORT MAP(R, Qn_tmp, Q_tmp); Q<=Q_tmp; Qn<=Qn_tmp; END structure; Simulation: Solution 6 () 67

70 d) ENTITY rsff_test IS END rsff_test; ARCHITECTURE rsff_testarch OF rsff_test IS COMPONENT rsff PORT(R, S: in bit; Qn, Q: out bit); END COMPONENT; SIGNAL R, S, Qn, Q: bit; BEGIN RSFF_: rsff port map(r, S, Qn, Q); S <=, after ns, after 5 ns, after 2 ns; R <=, after 5 ns, after 5 ns; END rsff_testarch; CONFIGURATION rsff_setup_dataflow OF rsff_test IS FOR rsff_testarch FOR RSFF_: rsff USE ENTITY WORK.rsff(dataflow); END FOR; END FOR; END rsff_setup_dataflow; CONFIGURATION rsff_setup_structure OF rsff_test IS FOR rsff_testarch FOR RSFF_: rsff USE ENTITY WORK.rsff(structure); FOR structure FOR Nor_a: Nor2 USE ENTITY WORK.nor2(fast_arch); END FOR; FOR Nor_b: Nor2 USE ENTITY WORK.nor2(fast_arch); END FOR; END FOR; END FOR; END FOR; END rsff_setup_structure; Simulation: Solution 6 (2) 68

71 e) S R Q Qn Process t= t=5 + Nor b +2 Nor a +3 Nor b t= + Nor a +2 Nor b t=5 + Nor a Nor b +2 Nor a Nor b... The process Nor a is sensitive to S and Q. It is eecuted whenever signal S or Q changes. The process Nor b is eecuted whenever R or Qn changes. For t=5 there is no stable state. The two processes Nor a and Nor b set the signals Q and Qn alternatel to in one - ccle and to in the net -ccle. The circuit oscillates. The simulator is in an infinite loop and the simulation time can not proceed. t S R Q Q n Simulation: Solution 6 (3) 69

72 Problem 2, Solution a) O t O i t = 4 t = 7 t = 8 t = t = 7 t = t = t = 3 t = 7 t = t = 3 t = t = 3 t = 2 t = 3 t = 5 t = 5 t = 3 t = 5 t = 5 t = 8 t = 2 t = 2 t = 2 t = 23 t = 2 t = 23 t = 2 t = 23 t = 23 b) Transport dela: Modeling of a device with infinite bandwidth. Inertial Dela: Modeling of a device with finite bandwidth. (Impulses which are shorter than the dela of the device are suppressed) O t O i t Simulation: Solution 6 (4) 7

73 Problem 3, Solution Process P: Transport dela model St insertion of the transaction into the driver ns 2 ns 2ns using the transport model, transactions at an earlier time sta in the driver ns 2 3 2ns 3ns 4 ns 5ns deletion of all transactions after 5ns (transaction at 2ns and 3ns eliminated) Process P2: Inertial dela model Si ns 2ns 3ns 4ns Input of the waveform into the driver 5 5ns 6 6ns deletion of all former transactions with a value other than 5: ns, 2ns, 3ns, 4ns 6 6 6ns 7ns 6 55ns deletion of all former transactions with a value other than 6: 5ns later transactions (here: 6ns, 7ns) are alwas deleted Simulation: Solution 6 (5) 7

74 III. Testing Tutorial 7: Fault Covering Problem Given is a multipleor ( = a + b). The circuit realization consists eclusivel of 2-input NAND-gates. a g b c d e f h i a) Determine a test set considering the functionalit of the multipleor (functional test generation) consisting of 4 input assignments. b) Compute the value of signal in the fault-free case (good simulation) and for all assumed single stuck-at faults (s-a-, s-a-) (fault simulation). Use the following table: f µ when assuming fault f µ a b c d e f g h i b a t ν Testing: Problems for Tutorial 7 () 72

75 c) Build the entire fault covering table. Which particularit does this table ehibit and what is the reason? d) Give all sets of non-distinguishable faults F U. e) Build the reduced fault covering table onl containing detectable and distinguishable faults. Choose those representative out of each set of non-distinguishable faults which has the smallest fault number. f) Compute the fault covering test set b evaluation of C M,N = V W (t ν Rf µ )τ ν =. µ M ν N Transform the equation such that ou obtain a conjunctive normal form (sum of products) from which ou can directl read off all possible complete test sets. g) Determine a test set using a covering table. Select tests b decreasing number of covered faults. Testing: Problems for Tutorial 7 (2) 73

76 Testing: Solution 7 () Solution of Tutorial 7: Problem, Solution a) b a (a observable at ) (=) a/ a= t 6 a/ a= t 5 (b observable at ) (=) b/ b= t b/ b= t 2 Since opposite values are assigned to signals a and b, faults at are implicitl tested. b) when assuming fault f µ i h g f e d c b a a b f µ t ν c) f µ t ν The faults f 2 and f 4 cannot be tested since the circuit has redundancies. 74

77 d) F U = {f,f 7,f 6 } F U2 = {f 3,f,f 7,f 2 } F U3 = {f 9,f,f 3,f 8 } F U4 = {f 5,f 9,f 22 } e) t ν f µ f) C M,N = (τ 5 + τ 7 ) (τ 4 + τ 6 ) (τ 2 + τ 3 ) (τ + τ ) (τ 5 + τ 6 ) (τ + τ 2 ) τ τ 6 (τ + τ + τ 4 + τ 6 ) (τ 2 + τ 3 + τ 5 + τ 7 ) after appling absorption: C M,N = τ τ 6 (τ 5 + τ 7 ) (τ 2 + τ 3 ) after transformation into a CNF (conjunctive normal form): C M,N = τ τ 6 τ 5 τ 2 + τ τ 6 τ 5 τ 3 + τ τ 6 τ 7 τ 2 + τ τ 6 τ 7 τ 3 all possible minimal complete test sets can be read off: T Cmin = {t,t 6,t 2,t 5 }, T Cmin2 = {t,t 6,t 2,t 7 } T Cmin3 = {t,t 6,t 3,t 5 }, T Cmin4 = {t,t 6,t 3,t 7 } g) t ν f µ F ν selection: t t 6 t 2 t 5 Testing: Solution 7 (2) 75